Si5935CDC Vishay Siliconix Dual P-Channel 20 V (D-S) MOSFET FEATURES PRODUCT SUMMARY RDS(on) (Ω) ID (A)a 0.100 at VGS = - 4.5 V - 4g 0.120 at VGS = - 2.5 V - 4g 0.156 at VGS = - 1.8 V - 3.8 VDS (V) - 20 Qg (Typ.) 6.2 nC • Halogen-free According to IEC 61249-2-21 Definition • TrenchFET® Power MOSFETs • 100 % Rg Tested • Compliant to RoHS Directive 2002/95/EC APPLICATIONS • Load Switch for Portable Devices • Battery Switch 1206-8 ChipFET® 1 S1 S1 D1 G1 D1 S2 Marking Code S2 D2 DK G2 D2 XXX G1 Lot Traceability and Date Code G2 Part # Code Bottom View Ordering Information: Si5935CDC-T1-E3 (Lead (Pb)-free) Si5935CDC-T1-GE3 (Lead (Pb)-free and Halogen-free) D1 D2 P-Channel MOSFET P-Channel MOSFET ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted Parameter Symbol VDS VGS Drain-Source Voltage Gate-Source Voltage Continuous Drain Current (TJ = 150 °C) TC = 25 °C TC = 70 °C TA = 25 °C TA = 70 °C Maximum Power Dissipation TC = 25 °C TA = 25 °C TC = 25 °C TC = 70 °C TA = 25 °C TA = 70 °C V - 4g - 3.8 ID - 3.1b, c - 2.5b, c - 10 - 2.6 IS A - 1.7b, c 3.1 2.0 PD W 1.3b, c 0.8b, c - 55 to 150 TJ, Tstg Operating Junction and Storage Temperature Range Unit ±8 IDM Pulsed Drain Current Source Drain Current Diode Current Limit - 20 Soldering Recommendations (Peak Temperature)d, e °C 260 THERMAL RESISTANCE RATINGS Parameter Junction-to-Ambientb, f t≤5s Symbol RthJA RthJF Typ. Max. 77 33 95 40 Unit Maximum °C/W Maximum Junction-to-Foot (Drain) Steady State Notes: a. Based on TC = 25 °C. b. Surface mounted on 1" x 1" FR4 board. c. t = 5 s. d. See Reliability Manual for profile. The ChipFET is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequade bottom side solder interconnection. e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components. f. Maximum under steady state conditions is 130 °C/W. g. Package limited. Document Number: 68965 S10-0548-Rev. B, 08-Mar-10 www.vishay.com 1 Si5935CDC Vishay Siliconix SPECIFICATIONS TJ = 25 °C, unless otherwise noted Parameter Symbol Test Conditions Min. - 20 Typ.a Max. Unit Static VDS VGS = 0 V, ID = - 250 µA ΔVDS/TJ ID = - 250 µA - 19 ΔVGS(th)/TJ ID = - 250 µA 2.5 VGS(th) VDS = VGS, ID = - 250 µA - 1.0 V IGSS VDS = 0 V, VGS = ± 8 V - 100 nA VDS = - 20 V, VGS = 0 V -1 VDS = - 20 V, VGS = 0 V, TJ = 55 °C -5 Drain-Source Breakdown Voltage VDS Temperature Coefficient VGS(th) Temperature Coefficient Gate Threshold Voltage Gate-Body Leakage Zero Gate Voltage Drain Current IDSS On-State Drain Currentb ID(on) Drain-Source On-State Resistanceb Forward Transconductanceb RDS(on) gfs VDS ≤ - 5 V, VGS = - 4.5 V V - 0.4 mV/°C - 10 µA A VGS = - 4.5 V, ID = - 3.1 A 0.083 0.100 VGS = - 2.5 V, ID = - 2.8 A 0.100 0.120 VGS = - 1.8 V, ID = - 2.5 A 0.130 0.156 VDS = - 10 V, ID = - 3.1 A 9.5 Ω S Dynamica Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Qg Total Gate Charge Gate-Source Charge Qgs Gate-Drain Charge Qgd Gate Resistance Rg 455 VDS = - 10 V, VGS = 0 V, f = 1 MHz 54 VDS = - 10 V, VGS = - 5 V, ID = - 3.1 A VDS = - 10 V, VGS = - 4.5 V, ID = - 3.1 A tr Rise Time td(off) Turn-Off Delay Time Fall Time Turn-On Delay Time f = 1 MHz VDD = - 10 V, RL = 4.2 Ω ID ≅ - 2.4 A, VGEN = - 8 V, Rg = 1 Ω 1.22 6.1 12.2 3 6 11 17 21 32 12 td(on) 10 20 VDD = - 10 V, RL = 4.2 Ω ID ≅ - 2.4 A, VGEN = - 4.5 V, Rg = 1 Ω tf Fall Time 0.85 6 td(off) Turn-Off Delay Time 11 9.3 tf tr Rise Time 7 6.2 nC 1.75 td(on) Turn-On Delay Time pF 70 32 48 25 38 6 12 Ω ns Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current a IS Pulse Diode Forward Current ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Reverse Recovery Fall Time ta Reverse Recovery Rise Time tb TC = 25 °C - 2.6 A - 10 IS = - 2.4 A, VGS = 0 V IF = - 2.4 A, dI/dt = 100 A/µs, TJ = 25 °C - 0.8 - 1.2 V 21 32 ns 13 20 nC 17 4 ns Notes: a. Guaranteed by design, not subject to production testing. b. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. www.vishay.com 2 Document Number: 68965 S10-0548-Rev. B, 08-Mar-10 Si5935CDC Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 10 3.0 VGS = 5 V thru 2 V 2.4 I D - Drain Current (A) I D - Drain Current (A) 8 6 VGS = 1.5 V 4 2 1.8 TC = 25 °C 1.2 TC = 125 °C 0.6 VGS = 1 V TC = - 55 °C 0 0 1 2 3 4 0.0 0.0 5 0.4 VDS - Drain-to-Source Voltage (V) 0.8 1.6 2.0 VGS - Gate-to-Source Voltage (V) Output Characteristics Transfer Characteristics 0.20 900 750 0.16 VGS = 1.8 V C - Capacitance (pF) R DS(on) - On-Resistance (Ω) 1.2 VGS = 2.5 V 0.12 VGS = 4.5 V 0.08 600 Ciss 450 300 Coss 0.04 150 Crss 0.00 0 0 2 4 6 8 10 0 4 8 16 ID - Drain Current (A) VDS - Drain-to-Source Voltage (V) On-Resistance vs. Drain Current and Gate Voltage Capacitance 20 1.5 5 ID = 3.1 A VGS = - 2.5 V, ID = - 2.8 A 4 3 VDS = 16 V 2 1.3 (Normalized) VDS = 10 V R DS(on) - On-Resistance VGS - Gate-to-Source Voltage (V) 12 1.1 VGS = - 4.5 V, ID = - 3.1 A 0.9 1 0 0 1 2 3 4 5 6 7 8 0.7 - 50 - 25 0 25 50 75 100 125 Qg - Total Gate Charge (nC) TJ - Junction Temperature (°C) Gate Charge On-Resistance vs. Junction Temperature Document Number: 68965 S10-0548-Rev. B, 08-Mar-10 150 www.vishay.com 3 Si5935CDC Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 0.18 100 ID = - 3.1 A R DS(on) - On-Resistance (Ω) I S - Source Current (A) 0.15 10 TJ = 25 °C TJ = 150 °C 1 0.12 TJ = 125 °C 0.09 TJ = 25 °C 0.06 0.03 0.00 0.1 0.1 0.3 0.5 0.7 0.9 1.1 0 1.3 2 VSD - Source-to-Drain Voltage (V) 4 6 8 VGS - Gate-to-Source Voltage (V) Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage 40 0.8 0.7 30 ID = 250 µA Power (W) VGS(th) (V) 0.6 0.5 20 0.4 10 0.3 0.2 - 50 - 25 0 25 50 75 100 125 0 10-4 150 10-3 10-2 10-1 1 10 TJ - Temperature (°C) Time (s) Threshold Voltage Single Pulse Power 100 1000 100 I D - Drain Current (A) Limited by RDS(on)* 10 100 µs 1 1 ms 10 ms 0.1 TA = 25 °C Single Pulse 0.01 0.1 BVDSS Limited 1 100 ms 1 s, 10 s DC 10 100 VDS - Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Safe Operating Area, Junction-to-Case www.vishay.com 4 Document Number: 68965 S10-0548-Rev. B, 08-Mar-10 Si5935CDC Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 6 I D - Drain Current (A) 5 4 Package Limited 3 2 1 0 0 25 50 75 100 125 150 TC - Case Temperature (°C) Current Derating* 4.0 1.2 3.2 Power (W) Power (W) 0.9 2.4 1.6 0.6 0.3 0.8 0.0 0.0 0 25 50 75 100 125 TC - Case Temperature (°C) Power Derating, Junction-to-Foot 150 0 25 50 75 100 125 150 TA - Ambient Temperature (°C) Power Derating, Junction-to-Ambient * The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit. Document Number: 68965 S10-0548-Rev. B, 08-Mar-10 www.vishay.com 5 Si5935CDC Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 2 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.1 0.2 Notes: 0.1 PDM t1 0.05 t2 1. Duty Cycle, D = 0.02 t1 t2 2. Per Unit Base = RthJA = 110 °C/W 3. TJM - TA = PDMZthJA(t) 4. Surface Mounted Single Pulse 0.01 10-4 10-3 10-2 10-1 1 10 100 600 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient 2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10-4 10-3 10-2 10-1 Square Wave Pulse Duration (s) 1 10 Normalized Thermal Transient Impedance, Junction-to-Foot Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?68965. www.vishay.com 6 Document Number: 68965 S10-0548-Rev. B, 08-Mar-10 Package Information Vishay Siliconix 1206-8 ChipFETR 4 L D 8 7 6 5 4 1 S 2 e 3 E1 5 6 7 8 4 3 2 1 E 4 b x c Backside View 2X 0.10/0.13 R C1 A DETAIL X NOTES: 1. All dimensions are in millimeaters. 2. Mold gate burrs shall not exceed 0.13 mm per side. 3. Leadframe to molded body offset is horizontal and vertical shall not exceed 0.08 mm. 4. Dimensions exclusive of mold gate burrs. 5. No mold flash allowed on the top and bottom lead surface. MILLIMETERS Dim A b c c1 D E E1 e L S INCHES Min Nom Max Min Nom Max 1.00 − 1.10 0.039 − 0.043 0.25 0.30 0.35 0.010 0.012 0.014 0.1 0.15 0.20 0.004 0.006 0.008 0 − 0.038 0 − 0.0015 2.95 3.05 3.10 0.116 0.120 0.122 1.825 1.90 1.975 0.072 0.075 0.078 1.55 1.65 1.70 0.061 0.065 0.067 0.65 BSC 0.28 − 0.0256 BSC 0.42 0.011 − 0.55 BSC 0.022 BSC 5_Nom 5_Nom 0.017 ECN: C-03528—Rev. F, 19-Jan-04 DWG: 5547 Document Number: 71151 15-Jan-04 www.vishay.com 1 AN812 Vishay Siliconix Dual-Channel 1206-8 ChipFETr Power MOSFET Recommended Pad Pattern and Thermal Performance INTRODUCTION New Vishay Siliconix ChipFETs in the leadless 1206-8 package feature the same outline as popular 1206-8 resistors and capacitors but provide all the performance of true power semiconductor devices. The 1206-8 ChipFET has the same footprint as the body of the LITTLE FOOTR TSOP-6, and can be thought of as a leadless TSOP-6 for purposes of visualizing board area, but its thermal performance bears comparison with the much larger SO-8. This technical note discusses the dual ChipFET 1206-8 pin-out, package outline, pad patterns, evaluation board layout, and thermal performance. 80 mil 25 mil 43 mil 18 mil 10 mil 26 mil PIN-OUT FIGURE 2. Figure 1 shows the pin-out description and Pin 1 identification for the dual-channel 1206-8 ChipFET device. The pin-out is similar to the TSOP-6 configuration, with two additional drain pins to enhance power dissipation and thus thermal performance. The legs of the device are very short, again helping to reduce the thermal path to the external heatsink/pcb and allowing a larger die to be fitted in the device if necessary. Dual 1206-8 ChipFET S1 G1 S2 Footprint With Copper Spreading The pad pattern with copper spreading shown in Figure 2 improves the thermal area of the drain connections (pins 5 and 6, pins 7 and 8) while remaining within the confines of the basic footprint. The drain copper area is 0.0019 sq. in. or 1.22 sq. mm. This will assist the power dissipation path away from the device (through the copper leadframe) and into the board and exterior chassis (if applicable) for the dual device. The addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further. An example of this method is implemented on the Vishay Siliconix Evaluation Board described in the next section (Figure 3). G2 D1 THE VISHAY SILICONIX EVALUATION BOARD FOR THE DUAL 1206-8 D1 D2 D2 FIGURE 1. For package dimensions see the 1206-8 ChipFET package outline drawing (http://www.vishay.com/doc?71151). BASIC PAD PATTERNS The basic pad layout with dimensions is shown in Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs, (http://www.vishay.com/doc?72286). This is sufficient for low power dissipation MOSFET applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. Document Number: 71127 12-Dec-03 The dual ChipFET 1206-08 evaluation board measures 0.6 in by 0.5 in. Its copper pad pattern consists of an increased pad area around each of the two drain leads on the top-side— approximately 0.0246 sq. in. or 15.87 sq. mm—and vias added through to the underside of the board, again with a maximized copper pad area of approximately the board-size dimensions, split into two for each of the drains. The outer package outline is for the 8-pin DIP, which will allow test sockets to be used to assist in testing. The thermal performance of the 1206-8 on this board has been measured with the results following on the next page. The testing included comparison with the minimum recommended footprint on the evaluation board-size pcb and the industry standard one-inch square FR4 pcb with copper on both sides of the board. www.vishay.com 1 AN812 Vishay Siliconix Front of Board Back of Board ChipFETr vishay.com FIGURE 3. Junction-to-Foot Thermal Resistance (the Package Performance) Thermal performance for the 1206-8 ChipFET measured as junction-to-foot thermal resistance is 30_C/W typical, 40_C/W maximum for the dual device. The “foot” is the drain lead of the device as it connects with the body. This is identical to the dual SO-8 package RQjf performance, a feat made possible by shortening the leads to the point where they become only a small part of the total footprint area. Junction-to-Ambient Thermal Resistance (dependent on pcb size) The typical RQja for the dual-channel 1206-8 ChipFET is 90_C/W steady state, identical to the SO-8. Maximum ratings are 110_C/W for both the 1206-8 and the SO-8. Both packages have comparable thermal performance on the 1” square pcb footprint with the 1206-8 dual package having a quarter of the body area, a significant factor when considering board area. The results show that a major reduction can be made in the thermal resistance by increasing the copper drain area. In this example, a 57_C/W reduction was achieved without having to increase the size of the board. If increasing board size is an option, a further 38_C/W reduction was obtained by maximizing the copper from the drain on the larger 1” square PCB. 200 Min. Footprint 160 Thermal Resistance (C/W) THERMAL PERFORMANCE Dual EVB 120 80 40 1” Square PCB Testing To aid comparison further, Figure 4 illustrates ChipFET 1206-8 dual thermal performance on two different board sizes and three different pad patterns.The results display the thermal performance out to steady state and produce a graphic account on how an increased copper pad area for the drain connections can enhance thermal performance. The measured steady state values of RQja for the Dual 1206-8 ChipFET are : 1) Minimum recommended pad pattern (see Figure 2) on the evaluation board size of 0.5 in x 0.6 in. 185_C/W 2) The evaluation board with the pad pattern described on Figure 3. 128_C/W 3) Industry standard 1” square pcb with maximum copper both sides. 90_C/W www.vishay.com 2 0 10-5 10-4 10-3 10-2 10-1 1 10 100 1000 Time (Secs) FIGURE 4. Dual 1206-8 ChipFET SUMMARY The thermal results for the dual-channel 1206-8 ChipFET package display identical power dissipation performance to the SO-8 with a footprint reduction of 80%. Careful design of the package has allowed for this performance to be achieved. The short leads allow the die size to be maximized and thermal resistance to be reduced within the confines of the TSOP-6 body size. ASSOCIATED DOCUMENT 1206-8 ChipFET Single Thermal performance, AN811, (http://www.vishay.com/doc?71126). Document Number: 71127 12-Dec-03 Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR 1206-8 ChipFET® 0.093 0.026 0.016 0.010 (0.650) (0.406) (0.244) 0.036 (0.914) 0.022 (0.559) (2.032) 0.080 (2.357) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index APPLICATION NOTE Return to Index www.vishay.com 2 Document Number: 72593 Revision: 21-Jan-08 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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We confirm that all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU. Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000