VISHAY SI5935DC-T1-E3

Si5935DC
Vishay Siliconix
Dual P-Channel 1.8 V (G-S) MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
- 20
RDS(on) (Ω)
ID (A)
0.086 at VGS = - 4.5 V
- 4.1
0.121 at VGS = - 2.5 V
- 3.4
0.171 at VGS = - 1.8 V
- 2.9
1206-8 ChipFET®
APPLICATIONS
• Load Switch
• PA Switch
• Battery Switch
1
S1
D1
Marking Code
G1
D1
S1
S2
DF XX
S2
D2
• Halogen-free According to IEC 61249-2-21
Definition
• TrenchFET® Power MOSFETs
• Low RDS(on) Dual and Excellent Power
Handling in a Compact Footprint
• Compliant to RoHS Directive 2002/95/EC
Lot Traceability
and Date Code
G2
D2
G1
Part # Code
G2
Bottom View
Ordering Information: Si5935DC-T1-E3 (Lead (Pb)-free)
Si5935DC-T1-GE3 (Lead (Pb)-free and Halogen-free)
D1
D2
P-Channel MOSFET
P-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter
Symbol
5s
Steady State
Drain-Source Voltage
VDS
- 20
Gate-Source Voltage
VGS
±8
Continuous Drain Current (TJ = 150 °C)a
TA = 25 °C
TA = 85 °C
Pulsed Drain Current
IS
TA = 25 °C
TA = 85 °C
PD
-3
- 2.9
- 2.2
- 15
- 1.8
- 0.9
2.1
1.1
1.1
0.6
TJ, Tstg
Operating Junction and Storage Temperature Range
V
- 4.1
IDM
Continuous Source Current (Diode Conduction)a
Maximum Power Dissipationa
ID
Unit
- 55 to 150
Soldering Recommendations (Peak Temperature)b, c
A
W
°C
260
THERMAL RESISTANCE RATINGS
Parameter
Maximum Junction-to-Ambienta
Maximum Junction-to-Foot (Drain)
Symbol
t≤5s
Steady State
Steady State
RthJA
RthJF
Typical
Maximum
50
60
90
110
30
40
Unit
°C/W
Notes:
a. Surface mounted on 1" x 1" FR4 board.
b. See reliability manual for profile. The ChipFET is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result
of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure
adequate bottom side solder interconnection.
c. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
Document Number: 72220
S10-0936-Rev. C, 19-Apr-10
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1
Si5935DC
Vishay Siliconix
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
Parameter
Symbol
Test Conditions
Min.
- 0.4
Typ.
Max.
Unit
Static
VGS(th)
VDS = VGS, ID = - 250 µA
- 1.0
V
Gate-Body Leakage
IGSS
VDS = 0 V, VGS = ± 8 V
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = - 20 V, VGS = 0 V
-1
VDS = - 20 V, VGS = 0 V, TJ = 85 °C
-5
On-State Drain Currenta
ID(on)
Gate Threshold Voltage
Drain-Source On-State Resistancea
RDS(on)
Diode Forward Voltage
- 15
A
VGS = - 4.5 V, ID = - 3 A
0.069
0.086
VGS = - 2.5 V, ID = - 2.5 A
0.097
0.121
0.171
VGS = - 1.8 V, ID = - 0.6 A
0.137
gfs
VDS = - 10 V, ID = - 3 A
8
VSD
IS = - 0.9 A, VGS = 0 V
- 0.8
- 1.2
5.5
8.5
Forward Transconductancea
a
VDS ≤ - 5 V, VGS = - 4.5 V
µA
Ω
S
V
Dynamicb
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Turn-On Delay Time
td(on)
Rise Time
VDS = - 10 V, VGS = - 4.5 V, ID = - 3 A
td(off)
Fall Time
tf
Source-Drain Reverse Recovery Time
trr
nC
1.6
tr
Turn-Off Delay Time
0.91
18
30
VDD = - 10 V, RL = 10 Ω
ID ≅ - 1 A, VGEN = - 4.5 V, Rg = 6 Ω
32
50
42
65
26
40
IF = - 0.9 A, dI/dt = 100 A/µs
30
60
ns
Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
15
15
VGS = 5 V thru 3 V
TC = - 55 °C
2.5 V
12
I D - Drain Current (A)
I D - Drain Current (A)
12
9
2V
6
3
25 °C
125 °C
9
6
3
1.5 V
1V
0
0
1
2
3
4
VDS - Drain-to-Source Voltage (V)
Output Characteristics
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2
5
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VGS - Gate-to-Source Voltage (V)
Transfer Characteristics
Document Number: 72220
S10-0936-Rev. C, 19-Apr-10
Si5935DC
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
800
0.30
VGS = 1.8 V
600
C - Capacitance (pF)
R DS(on) - On-Resistance (Ω)
0.25
0.20
0.15
VGS = 2.5 V
0.10
VGS = 4.5 V
Ciss
400
200
Coss
0.05
Crss
0
0.00
0
3
6
9
12
0
15
8
12
16
ID - Drain Current (A)
VDS - Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current
Capacitance
20
1.6
5
VGS = 4.5 V
ID = 3 A
VDS = 10 V
ID = 3 A
1.4
3
2
(Normalized)
4
R DS(on) - On-Resistance
VGS - Gate-to-Source Voltage (V)
4
1.2
1.0
0.8
1
0.6
- 50
0
0
1
2
3
4
5
6
7
8
- 25
0
Qg - Total Gate Charge (nC)
Gate Charge
50
75
100
125
150
On-Resistance vs. Junction Temperature
0.4
R DS(on) - On-Resistance (Ω)
20
I S - Source Current (A)
10
TJ = 150 °C
1
0.0
25
TJ - Junction Temperature (°C)
TJ = 25 °C
0.3
ID = 0.6 A
0.2
ID = 3 A
0.1
0.0
0.2
0.4
0.6
0.8
1.0
1.2
VSD - Source-to-Drain Voltage (V)
Source-Drain Diode Forward Voltage
Document Number: 72220
S10-0936-Rev. C, 19-Apr-10
1.4
0
1
2
3
4
5
VGS - Gate-to-Source Voltage (V)
On-Resistance vs. Gate-to-Source Voltage
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Si5935DC
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
0.4
50
0.3
40
0.2
30
Power (W)
VGS(th) Variance (V)
ID = 250 µA
0.1
20
0.0
10
- 0.1
- 0.2
- 50
- 25
0
25
50
75
100
125
0
10-4
150
10-3
10-2
10-1
TJ - Temperature (°C)
1
10
100
600
Time (s)
Threshold Voltage
Single Pulse Power
100
IDM Limited
Limited by RDS(on)*
I D - Drain Current (A)
10
1
0.1
P(t) = 0.0001
P(t) = 0.001
ID(on)
Limited
P(t) = 0.01
P(t) = 0.1
P(t) = 1
P(t) = 10
DC
TC = 25 °C
Single Pulse
BVDSS Limited
0.01
0.1
1
10
100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum V GS at which R DS(on) is specified
Safe Operating Area
2
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
Notes:
0.1
PDM
0.1
0.05
t1
t2
1. Duty Cycle, D =
0.02
t1
t2
2. Per Unit Base = R thJA = 90 °C/W
3. T JM - TA = PDMZthJA(t)
Single Pulse
4. Surface Mounted
0.01
10-4
10-3
10-2
10-1
1
10
100
600
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
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Document Number: 72220
S10-0936-Rev. C, 19-Apr-10
Si5935DC
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
2
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10-4
10-3
10-2
10-1
1
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?72220.
Document Number: 72220
S10-0936-Rev. C, 19-Apr-10
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Package Information
Vishay Siliconix
1206-8 ChipFETR
4
L
D
8
7
6
5
4
1
S
2
e
3
E1
5
6
7
8
4
3
2
1
E
4
b
x
c
Backside View
2X 0.10/0.13 R
C1
A
DETAIL X
NOTES:
1.
All dimensions are in millimeaters.
2.
Mold gate burrs shall not exceed 0.13 mm per side.
3.
Leadframe to molded body offset is horizontal and vertical shall not exceed
0.08 mm.
4.
Dimensions exclusive of mold gate burrs.
5.
No mold flash allowed on the top and bottom lead surface.
MILLIMETERS
Dim
A
b
c
c1
D
E
E1
e
L
S
INCHES
Min
Nom
Max
Min
Nom
Max
1.00
−
1.10
0.039
−
0.043
0.25
0.30
0.35
0.010
0.012
0.014
0.1
0.15
0.20
0.004
0.006
0.008
0
−
0.038
0
−
0.0015
2.95
3.05
3.10
0.116
0.120
0.122
1.825
1.90
1.975
0.072
0.075
0.078
1.55
1.65
1.70
0.061
0.065
0.067
0.65 BSC
0.28
−
0.0256 BSC
0.42
0.011
−
0.55 BSC
0.022 BSC
5_Nom
5_Nom
0.017
ECN: C-03528—Rev. F, 19-Jan-04
DWG: 5547
Document Number: 71151
15-Jan-04
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1
AN812
Vishay Siliconix
Dual-Channel 1206-8 ChipFETr Power MOSFET Recommended
Pad Pattern and Thermal Performance
INTRODUCTION
New Vishay Siliconix ChipFETs in the leadless 1206-8
package feature the same outline as popular 1206-8 resistors
and capacitors but provide all the performance of true power
semiconductor devices. The 1206-8 ChipFET has the same
footprint as the body of the LITTLE FOOTR TSOP-6, and can
be thought of as a leadless TSOP-6 for purposes of visualizing
board area, but its thermal performance bears comparison
with the much larger SO-8.
This technical note discusses the dual ChipFET 1206-8
pin-out, package outline, pad patterns, evaluation board
layout, and thermal performance.
80 mil
25 mil
43 mil
18 mil
10 mil
26 mil
PIN-OUT
FIGURE 2.
Figure 1 shows the pin-out description and Pin 1 identification
for the dual-channel 1206-8 ChipFET device. The pin-out is
similar to the TSOP-6 configuration, with two additional drain
pins to enhance power dissipation and thus thermal
performance. The legs of the device are very short, again
helping to reduce the thermal path to the external heatsink/pcb
and allowing a larger die to be fitted in the device if necessary.
Dual 1206-8 ChipFET
S1
G1
S2
Footprint With Copper Spreading
The pad pattern with copper spreading shown in Figure 2
improves the thermal area of the drain connections (pins 5 and
6, pins 7 and 8) while remaining within the confines of the basic
footprint. The drain copper area is 0.0019 sq. in. or
1.22 sq. mm. This will assist the power dissipation path away
from the device (through the copper leadframe) and into the
board and exterior chassis (if applicable) for the dual device.
The addition of a further copper area and/or the addition of vias
to other board layers will enhance the performance still further.
An example of this method is implemented on the Vishay
Siliconix Evaluation Board described in the next section
(Figure 3).
G2
D1
THE VISHAY SILICONIX EVALUATION
BOARD FOR THE DUAL 1206-8
D1
D2
D2
FIGURE 1.
For package dimensions see the 1206-8 ChipFET package
outline drawing (http://www.vishay.com/doc?71151).
BASIC PAD PATTERNS
The basic pad layout with dimensions is shown in Application
Note 826, Recommended Minimum Pad Patterns With Outline
Drawing
Access
for
Vishay Siliconix
MOSFETs,
(http://www.vishay.com/doc?72286). This is sufficient for low
power dissipation MOSFET applications, but power
semiconductor performance requires a greater copper pad
area, particularly for the drain leads.
Document Number: 71127
12-Dec-03
The dual ChipFET 1206-08 evaluation board measures 0.6 in
by 0.5 in. Its copper pad pattern consists of an increased pad
area around each of the two drain leads on the top-side—
approximately 0.0246 sq. in. or 15.87 sq. mm—and vias
added through to the underside of the board, again with a
maximized copper pad area of approximately the board-size
dimensions, split into two for each of the drains. The outer
package outline is for the 8-pin DIP, which will allow test
sockets to be used to assist in testing.
The thermal performance of the 1206-8 on this board has been
measured with the results following on the next page. The
testing included comparison with the minimum recommended
footprint on the evaluation board-size pcb and the industry
standard one-inch square FR4 pcb with copper on both sides
of the board.
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AN812
Vishay Siliconix
Front of Board
Back of Board
ChipFETr
vishay.com
FIGURE 3.
Junction-to-Foot Thermal Resistance (the Package
Performance)
Thermal performance for the 1206-8 ChipFET measured as
junction-to-foot thermal resistance is 30_C/W typical, 40_C/W
maximum for the dual device. The “foot” is the drain lead of the
device as it connects with the body. This is identical to the dual
SO-8 package RQjf performance, a feat made possible by
shortening the leads to the point where they become only a
small part of the total footprint area.
Junction-to-Ambient Thermal Resistance
(dependent on pcb size)
The typical RQja for the dual-channel 1206-8 ChipFET is
90_C/W steady state, identical to the SO-8. Maximum ratings
are 110_C/W for both the 1206-8 and the SO-8. Both packages
have comparable thermal performance on the 1” square pcb
footprint with the 1206-8 dual package having a quarter of the
body area, a significant factor when considering board area.
The results show that a major reduction can be made in the
thermal resistance by increasing the copper drain area. In this
example, a 57_C/W reduction was achieved without having to
increase the size of the board. If increasing board size is an
option, a further 38_C/W reduction was obtained by
maximizing the copper from the drain on the larger 1” square
PCB.
200
Min. Footprint
160
Thermal Resistance (C/W)
THERMAL PERFORMANCE
Dual EVB
120
80
40
1” Square PCB
Testing
To aid comparison further, Figure 4 illustrates ChipFET 1206-8
dual thermal performance on two different board sizes and
three different pad patterns.The results display the thermal
performance out to steady state and produce a graphic
account on how an increased copper pad area for the drain
connections can enhance thermal performance. The
measured steady state values of RQja for the Dual 1206-8
ChipFET are :
1) Minimum recommended pad pattern (see
Figure 2) on the evaluation board size of
0.5 in x 0.6 in.
185_C/W
2) The evaluation board with the pad pattern
described on Figure 3.
128_C/W
3) Industry standard 1” square pcb with
maximum copper both sides.
90_C/W
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2
0
10-5 10-4
10-3
10-2
10-1
1
10
100
1000
Time (Secs)
FIGURE 4.
Dual 1206-8 ChipFET
SUMMARY
The thermal results for the dual-channel 1206-8 ChipFET
package display identical power dissipation performance to
the SO-8 with a footprint reduction of 80%. Careful design of
the package has allowed for this performance to be achieved.
The short leads allow the die size to be maximized and thermal
resistance to be reduced within the confines of the TSOP-6
body size.
ASSOCIATED DOCUMENT
1206-8 ChipFET Single Thermal performance, AN811,
(http://www.vishay.com/doc?71126).
Document Number: 71127
12-Dec-03
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR 1206-8 ChipFET®
0.093
0.026
0.016
0.010
(0.650)
(0.406)
(0.244)
0.036
(0.914)
0.022
(0.559)
(2.032)
0.080
(2.357)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
APPLICATION NOTE
Return to Index
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Document Number: 72593
Revision: 21-Jan-08
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Revision: 02-Oct-12
1
Document Number: 91000