Si8409DB Datasheet

Si8409DB
www.vishay.com
Vishay Siliconix
P-Channel 30 V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
-30
RDS(on) ()
ID (A)
0.046 at VGS = -4.5 V
-6.3
0.065 at VGS = -2.5 V
-5.3
Qg (TYP.)
17
• TrenchFET® power MOSFET
• MICRO FOOT® chipscale packaging reduces
footprint area profile (0.62 mm) and
on-resistance per footprint area
• Pin compatible to industry standard Si8401DB
MICRO FOOT® 1.6 x 1.6
D
3
6
1.
9
840xx
x
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
D
2
APPLICATIONS
m
m
m
6m
1
1.
Backside View
S
• Load switch, battery switch, and PA
switch for portable devices
1
G
4
S
Bump Side View
G
Marking: 8409
Ordering Information: 
Si8409DB-T1-E1 (Lead (Pb)-free and halogen-free)
D
P-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
5s
STEADY STATE
Drain-Source Voltage
VDS
-30
Gate-Source Voltage
VGS
± 12
Continuous Drain Current (TJ = 150 °C) a
TA = 25 °C
TA = 70 °C
Pulsed Drain Current
IS
TA = 25 °C
TA = 70 °C
Operating Junction and Storage Temperature Range
Package Reflow Conditions b
PD
V
-6.3
-4.6
-5.1
-3.7
IDM
Continuous Source Current (Diode Conduction) a
Maximum Power Dissipation a
ID
-25
-2.5
-1.3
2.77
1.47
1.77
0.94
TJ, Tstg
-55 to 150
IR / convection
UNIT
A
W
°C
260
THERMAL RESISTANCE RATINGS
PARAMETER
Maximum Junction-to-Ambient a
Maximum Junction-to-Foot (drain)
SYMBOL
t5s
Steady state
Steady state
RthJA
RthJF
TYPICAL
MAXIMUM
35
45
72
85
16
20
UNIT
°C/W
Notes
a. Surface mounted on 1" x 1" FR4 board.
b. Refer to IPC / JEDEC® (J-STD-020), no manual or hand soldering.
S15-1692-Rev. D, 20-Jul-15
Document Number: 73111
1
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si8409DB
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Vishay Siliconix
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
VGS(th)
VDS = VGS, ID = -250 μA
-0.6
-
-1.4
V
Gate-Body Leakage
Gate Threshold Voltage
IGSS
VDS = 0 V, VGS = ± 12 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
On-State Drain Current a
ID(on)
Drain-Source On-State Resistance a
VDS = -30 V, VGS = 0 V
-
-
-1
VDS = -30 V, VGS = 0 V, TJ = 70 °C
-
-
-5
VDS  -5 V, VGS = -4.5 V
-5
-
-
A
VGS = -4.5 V, ID = -1 A
-
0.038
0.046
VGS = -2.5 V, ID = -1 A
-
0.052
0.065

RDS(on)
μA
Forward Transconductance a
gfs
VDS = -10 V, ID = -1 A
-
6.4
-
S
Diode Forward Voltage a
VSD
IS = -1 A, VGS = 0 V
-
-0.8
-1.1
V
-
17
26
VDS = -10 V, VGS = -4.5 V, ID = -1 A
-
2.2
-
-
5.7
-
-
22
-
-
20
30
Dynamic b
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Reverse Recovery Charge
Rg
Turn-On Delay Time
f = 1 MHz
td(on)
Rise Time
VDD = -10 V, RL = 10 
ID  -1 A, VGEN = -4.5 V, RG = 6 
tr
Turn-Off Delay Time
td(off)
Fall Time
tf
Source-Drain Reverse Recovery Time
trr
IF = -1 A, dI/dt = 100 A/μs
nC

-
35
55
-
140
210
-
90
135
-
85
130
ns
Notes
a. Pulse test; pulse width  300 μs, duty cycle  2 %.
b. Guaranteed by design, not subject to production testing.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
25
25
VGS = 5 thru 3 V
2.5 V
20
I D - Drain Current (A)
I D - Drain Current (A)
20
15
2V
10
5
15
10
TC = 125 °C
5
25 °C
1.5 V
- 55 °C
0
0
1
2
3
4
VDS - Drain-to-Source Voltage (V)
Output Characteristics
S15-1692-Rev. D, 20-Jul-15
5
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VGS - Gate-to-Source Voltage (V)
Transfer Characteristics
Document Number: 73111
2
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si8409DB
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Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
1500
0.16
1200
0.12
C - Capacitance (pF)
RDS(on) - On-Resistance (Ω)
0.14
0.10
0.08
VGS = 2.5 V
0.06
VGS = 4.5 V
Ciss
900
600
0.04
Coss
300
0.02
Crss
0.00
0
0
5
10
15
20
25
0
5
ID - Drain Current (A)
10
25
30
Capacitance
5
1.6
RDS(on) - On-Resistance (Normalized)
VGS - Gate-to-Source Voltage (V)
20
VDS - Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current
VDS = 10 V
ID = 1 A
4
3
2
1
0
0
4
8
12
16
1.5
VGS = 4.5 V
ID = 1 A
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
- 50
20
Qg - Total Gate Charge (nC)
- 25
0
25
50
75
100
125
150
TJ - Junction Temperature ( C)
On-Resistance vs. Junction Temperature
Gate Charge
0.10
RDS(on) - On-Resistance (Ω)
30
IS - Source Current (A)
15
TJ = 150 °C
10
TJ = 25 °C
1
0.0
0.08
ID = 1 A
0.06
0.04
0.02
0.00
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VSD - Source-to-Drain Voltage (V)
Source-Drain Diode Forward Voltage
S15-1692-Rev. D, 20-Jul-15
1.6
0
1
2
3
4
5
VGS - Gate-to-Source Voltage (V)
On-Resistance vs. Gate-to-Source Voltage
Document Number: 73111
3
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si8409DB
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Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
0.6
80
ID = 250 µA
0.5
60
0.3
Power (W)
V GS(th) Variance (V)
0.4
0.2
40
0.1
20
0.0
- 0.1
- 0.2
- 50
0
- 25
0
25
50
75
100
125
150
0.001
0.01
0.1
TJ - Temperature (°C)
1
10
100
600
Time (s)
Threshold Voltage
Single Pulse Power, Junction-to-Ambient
100
IDM Limited
Limited RDS(on)*
I D - Drain Current (A)
10
P(t) = 0.001
1
ID(on)
Limited
P(t) = 0.01
P(t) = 0.1
0.1
TA = 25 °C
Single Pulse
P(t) = 1
P(t) = 10
BVDSS Limited
0.01
0.1
DC
1
10
100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area
2
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
Notes:
0.1
PDM
0.1
0.05
t1
t2
1. Duty Cycle, D =
t1
t2
2. Per Unit Base = RthJA = 72 °C/W
0.02
3. TJM - TA = PDMZthJA(t)
Single Pulse
4. Surface Mounted
0.01
10- 4
10-3
10-2
10-1
1
Square Wave Pulse Duration (s)
10
100
600
Normalized Thermal Transient Impedance, Junction-to-Ambient
S15-1692-Rev. D, 20-Jul-15
Document Number: 73111
4
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Si8409DB
www.vishay.com
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
2
Normalized Effective Transient
Thermal Impedance
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10- 4
10-3
10-2
10-1
Square Wave Pulse Duration (s)
1
10
Normalized Thermal Transient Impedance, Junction-to-Foot
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Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?73111.
S15-1692-Rev. D, 20-Jul-15
Document Number: 73111
5
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
MICRO FOOT®: 4-Bumps
(1.6 mm x 1.6 mm, 0.8 mm Pitch, 0.290 mm Bump Height)
4x Ø b1
4x 0.30 to .31
(Note 3)
Solder mask-0.4
S
Mark on backside of die
D
S
G
e
e
Recommended land pattern
S
XXX
D
e
E
XXXX
S
e
S
D
b
Note 5
A1
A
A2
b1
K
Notes
1. Bumps are 95.5/3.8/0.7 Sn/Ag/Cu.
2. Backside surface is coated with a Ti/Ni/Ag layer.
3. Non-solder mask defined copper landing pad.
4. Laser marks on the silicon die back.
5. “b1” is the diameter of the solderable substrate surface, defined by an opening in the solder resist layer solder mask defined.
6. • is the location of pin 1
DIM.
MILLIMETERS
INCHES
MIN.
NOM.
MAX.
MIN.
NOM.
MAX.
A
0.550
0.575
0.600
0.0217
0.0226
0.0236
A1
0.260
0.275
0.290
0.0102
0.0108
0.0114
A2
0.290
0.300
0.310
0.0114
0.0118
0.0122
b
0.370
0.390
0.410
0.0146
0.0153
0.0161
b1
0.300
e
0.0118
0.800
0.0314
s
0.360
0.380
0.400
0.0141
0.0150
D
1.520
1.560
1.600
0.0598
0.0614
0.0157
0.0630
E
1.520
1.560
1.600
0.0598
0.0614
0.0630
K
0.155
0.185
0.215
0.0061
0.0073
0.0085
Note
• Use millimeters as the primary measurement.
ECN: T15-0175-Rev. A, 27-Apr-15
DWG: 6038
Revision: 27-Apr-15
1
Document Number: 69378
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
AN824
Vishay Siliconix
PCB Design and Assembly Guidelines
For MICRO FOOTr Products
Johnson Zhao
INTRODUCTION
Vishay Siliconix’s MICRO FOOT product family is based on a
wafer-level chip-scale packaging (WL-CSP) technology that
implements a solder bump process to eliminate the need for an
outer package to encase the silicon die. MICRO FOOT
products include power MOSFETs, analog switches, and
power ICs.
For battery powered compact devices, this new packaging
technology reduces board space requirements, improves
thermal performance, and mitigates the parasitic effect typical
of leaded packaged products. For example, the 6−bump
MICRO FOOT Si8902EDB common drain power MOSFET,
which measures just 1.6 mm x 2.4 mm, achieves the same
performance as TSSOP−8 devices in a footprint that is 80%
smaller and with a 50% lower height profile (Figure 1). A
MICRO FOOT analog switch, the 6−bump DG3000DB, offers
low charge injection and 1.4 W on−resistance in a footprint
measuring just 1.08 mm x 1.58 mm (Figure 2).
Vishay Siliconix MICRO FOOT products can be handled with
the same process techniques used for high-volume assembly
of packaged surface-mount devices. With proper attention to
PCB and stencil design, the device will achieve reliable
performance without underfill. The advantage of the device’s
small footprint and short thermal path make it an ideal option
for space-constrained applications in portable devices such as
battery packs, PDAs, cellular phones, and notebook
computers.
This application note discusses the mechanical design and
reliability of MICRO FOOT, and then provides guidelines for
board layout, the assembly process, and the PCB rework
process.
FIGURE 1. 3D View of MICRO FOOT Products Si8902DB and
Si8900EDB
3
2
1
0.18 ~ 0.25
A
1.08
0.5
B
0.285
0.285
0.5
1.58
FIGURE 2. Outline of MICRO FOOT CSP & Analog
Switch DG3000DB
Document Number: 71990
06-Jan-03
www.vishay.com
1
AN824
Vishay Siliconix
TABLE 1
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Main Parameters of Solder Bumps in MICRO FOOT Designs
MICRO FOOT CSP
Bump Material
MICRO FOOT CSP MOSFET
Eutectic Solder:
63Sm/37Pb
MICRO FOOT CSP Analog Switch
MICRO FOOT UCSP Analog Switch
Bump Pitch*
Bump Diameter*
Bump Height*
0.8
0.37-0.41
0.26-0.29
0.5
0.18-0.25
0.14-0.19
0.5
0.32-0.34
0.21-0.24
* All measurements in millimeters
MICRO FOOT’S DESIGN AND RELIABILITY
BOARD LAYOUT GUIDELINES
As a mechanical, electrical, and thermal connection between
the device and PCB, the solder bumps of MICRO FOOT
products are mounted on the top active surface of the die.
Table 1 shows the main parameters for solder bumps used in
MICRO FOOT products. A silicon nitride passivation layer is
applied to the active area as the last masking process in
fabrication,ensuring that the device passes the pressure pot
test. A green laser is used to mark the backside of the die
without damaging it. Reliability results for MICRO FOOT
products mounted on a FR-4 board without underfill are shown
in Table 2.
Board materials. Vishay Siliconix MICRO FOOT products are
designed to be reliable on most board types, including organic
boards such as FR-4 or polyamide boards. The package
qualification information is based on the test on 0.5-oz. FR-4
and polyamide boards with NSMD pad design.
TABLE 2
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
MICRO FOOT Reliability Results
Test Condition C: −65_ to 150_C
>500 Cycles
Test condition B: −40_ to 125_C
>1000 Cycles
121_C @ 15PSI 100% Humidity Test
96 Hours
The main failure mechanism associated with wafer-level
chip-scale packaging is fatigue of the solder joint. The results
shown in Table 2 demonstrate that a high level of reliability can
be achieved with proper board design and assembly
techniques.
Land patterns. Two types of land patterns are used for
surface-mount packages. Solder mask defined (SMD) pads
have a solder mask opening smaller than the metal pad
(Figure 3), whereas on-solder mask defined (NSMD) pads
have a metal pad smaller than the solder-mask opening
(Figure 4).
NSMD is recommended for copper etch processes, since it
provides a higher level of control compared to SMD etch
processes. A small-size NSMD pad definition provides more
area (both lateral and vertical) for soldering and more room for
escape routing on the PCB. By contrast, SMD pad definition
introduces a stress concentration point near the solder mask
on the PCB side that may result in solder joint cracking under
extreme fatigue conditions.
Copper pads should be finished with an organic solderability
preservative
(OSP)
coating.
For
electroplated
nickel-immersion gold finish pads, the gold thickness must be
less than 0.5 mm to avoid solder joint embrittlement.
Solder Mask
Copper
Copper
FIGURE 3. SMD
www.vishay.com
2
Solder Mask
FIGURE 4. NSMD
Document Number: 71990
06-Jan-03
AN824
Vishay Siliconix
TABLE 3
Dimensions of Copper Pad and Solder Mask
Opening in PCB and Stencil Aperture
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
Pitch
Copper Pad
Solder Mask
Opening
Stencil
Aperture
0.80 mm
0.30 " 0.01 mm
0.41 " 0.01 mm
0.33 " 0.01 mm
in ciircle aperture
0.50 mm
0.17 " 0.01 mm
0.27 " 0.01 mm
0.30 " 0.01 mm
in square aperture
ASSEMBLY PROCESS
MICRO FOOT products’ surface-mount-assembly operations
include solder paste printing, component placement, and
solder reflow as shown in the process flow chart (Figure 5).
Chip pick-and-placement. MICRO FOOT products can be
picked and placed with standard pick-and-place equipment.
The recommended pick-and-place force is 150 g. Though the
part will self-center during solder reflow, the maximum
placement offset is 0.02 mm.
Reflow Process. MICRO FOOT products can be assembled
using standard SMT reflow processes. Similar to any other
package, the thermal profile at specific board locations must
be determined. Nitrogen purge is recommended during reflow
operation. Figure 6 shows a typical reflow profile.
Thermal Profile
250
200
Temperature (_C)
Board pad design. The landing-pad size for MICRO FOOT
products is determined by the bump pitch as shown in Table 3.
The pad pattern is circular to ensure a symmetric,
barrel-shaped solder bump.
150
100
50
Stencil Design
IIncoming Tape and Reel Inspection
0
0
Solder Paste Printing
100
200
300
400
Time (Seconds
Chip Placement
FIGURE 6. Reflow Profile
Reflow
Solder Joint Inspection
Pack and Ship
FIGURE 5. SMT Assembly Process Flow
PCB REWORK
To replace MICRO FOOT products on PCB, the rework
procedure is much like the rework process for a standard BGA
or CSP, as long as the rework process duplicates the original
reflow profile. The key steps are as follows:
1.
Stencil design. Stencil design is the key to ensuring
maximum solder paste deposition without compromising the
assembly yield from solder joint defects (such as bridging and
extraneous solder spheres). The stencil aperture is dependent
on the copper pad size, the solder mask opening, and the
quantity of solder paste.
Remove the MICRO FOOT device using a convection
nozzle to create localized heating similar to the original
reflow profile. Preheat from the bottom.
2.
Once the nozzle temperature is +190_C, use tweezers to
remove the part to be replaced.
3.
In MICRO FOOT products, the stencil is 0.125-mm (5-mils)
thick. The recommended apertures are shown in Table 3 and
are fabricated by laser cut.
Resurface the pads using a temperature-controlled
soldering iron.
4.
Apply gel flux to the pad.
5.
Use a vacuum needle pick-up tip to pick up the
replacement part, and use a placement jig to placed it
accurately.
6.
Reflow the part using the same convection nozzle, and
preheat from the bottom, matching the original reflow
profile.
Solder-paste printing. The solder-paste printing process
involves transferring solder paste through pre-defined
apertures via application of pressure.
In MICRO FOOT products, the solder paste used is UP78
No-clean eutectic 63 Sn/37Pb type3 or finer solder paste.
Document Number: 71990
06-Jan-03
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RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular
purpose, non-infringement and merchantability.
Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical
requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements
about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular
product with the properties described in the product specification is suitable for use in a particular application. Parameters
provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All
operating parameters, including typical parameters, must be validated for each customer application by the customer’s
technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase,
including but not limited to the warranty expressed therein.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please
contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by
any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.
Material Category Policy
Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
(EEE) - recast, unless otherwise specified as non-compliant.
Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.
Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free
requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21
conform to JEDEC JS709A standards.
Revision: 02-Oct-12
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Document Number: 91000