DG3000 Datasheet

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DG3000
Vishay Siliconix
Low-Voltage Single SPDT MICRO FOOT®Analog Switch
DESCRIPTION
FEATURES
The DG3000 is a single-pole/double-throw monolithic CMOS
analog switch designed for high performance switching of
analog signals. Combining low power, high speed
(tON: 24 ns, tOFF: 9 ns), low on-resistance (RDS(on): 1.4 Ω)
and small physical size (MICRO FOOT, 6-bump), the
DG3000 is ideal for portable and battery powered
applications requiring high performance and efficient use of
board space.
• MICRO FOOT® Chip Scale Package
(1.07 x 1.57 mm)
• Low Voltage Operation (1.8 V to 5.5 V)
• Low On-Resistance - RDS(on): 1.4 Ω
• Fast Switching - tON: 24 ns, tOFF: 9 ns
• Low Power Consumption
• TTL/CMOS Compatible
The DG3000 is built on Vishay Siliconix’s low voltage JI2
process. An epitaxial layer prevents latchup. Break-before make is guaranteed for DG3000.
BENEFITS
Each switch conducts equally well in both directions when
on, and blocks up to the power supply level when off.
As a committed partner to the community and the
environment, Vishay Siliconix manufactures this product
with the lead (Pb)-free device terminations. For MICRO
FOOT analog switching products manufactured with
tin/silver/copper (Sn/Ag/Cu) device terminations, the
lead (Pb)-free "-E1" suffix is being used as a designator.
•
•
•
•
Available
Available
Reduced Power Consumption
Simple Logic Interface
High Accuracy
Reduce Board Space
APPLICATIONS
•
•
•
•
•
•
Cellular Phones
Communication Systems
Portable Test Equipment
Battery Operated Systems
PCM Cards
PDA
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
MICRO FOOT
(6-Bump)
TRUTH TABLE
IN
B1
A1
NO (Source1)
V+
B2
A2
COM
GND
B3
A3
NC (Source2)
Logic
NC
NO
0
ON
OFF
1
OFF
ON
ORDERING INFORMATION
Temp Range
Top View
A1 Locator
- 40 °C to 85 °C
Package
MICRO FOOT: 6-Bump
3 x 2, 0.5 mm Pitch
165 µm nom. bump height
(Eutectic, SnPb)
XXX
3000
MICRO FOOT: 6-Bump
3 x 2, 0.5 mm pitch,
238 µm nom. bump height
(Lead (Pb)-free, Sn/Ag/Cu)
Part Number
DG3000DB-T1
DG3000DB-T1E1
Device Marking: 3000
xxx = Date/Lot Traceability Code
* Pb containing terminations are not RoHS compliant, exemptions may apply.
Document Number: 71742
S-70853–Rev. F, 30-Apr-07
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DG3000
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
Parameter
Referenced V+ to GND
Limit
- 0.3 to + 6 V
- 0.3 V to (V+ + 0.3 V)
± 50
± 200
- 65 to 150
IN, COM, NC, NOa
Continuous Current (Any Terminal)
Peak Current (Pulsed at 1 ms, 10 % duty cycle)
Storage Temperature (D Suffix)
Package Reflow Conditionsb
VPR (Eutectic)
IR/Convection (Eutectic)
IR/Convection (Lead (Pb)-free)
Power Dissipation (Packages)c
Unit
V
mA
°C
215
220
250
250
6-Bump, 3 x 2 MICRO FOOTd
°C
mW
Notes:
a. Signals on NC, NO, or COM or IN exceeding V+ will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
b. Refer to IPC/JEDEC (J-STD-020A). No hand/manual solder rework recommended.
c. All bumps soldered to PC Board.
d. Derate 3.1 mW/°C above 70 °C.
SPECIFICATIONS (V+ = 2 V)
Parameter
Symbol
Test Conditions
Otherwise Unless Specified
V+ = 2 V, ± 10 %, VIN = 0.4 V or 1.6 Ve
Limits
- 40 °C to 85 °C
Temp.a
Min.b
Full
0
Typ.c
Max.b
Unit
V+
V
Analog Switch
VNO, VNC
VCOM
Analog Signal Ranged
On-Resistance
rON Flatnessd
Switch Off Leakage Currentf
rON
V+ = 1.8 V, VCOM = 1 V, INO, INC = 10 mA
Room
Fulld
17
rON
Flatness
V+ = 1.8 V, VCOM = 0 to V+, INO, INC = 10 mA
Room
14
INO(off)
INC(off)
ICOM(off)
Channel-On Leakage Currentf
Digital Control
Input High Voltage
Input Low Voltage
Input Capacitanced
Input Currentd
Dynamic Characteristics
ICOM(on)
VINH
VINL
Cin
IINL or IINH
Turn-On Time
tON
Turn-Off Time
tOFF
td
QINJ
OIRR
XTALK
Break-Before-Make Time
Charge Injection
Off-Isolationd
Crosstalkd
d
NO, NC Off Capacitanced
Channel-On Capacitance
Power Supply
Power Supply Range
Power Supply Currentd
Power Consumption
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d
CNO(off)
CNC(off)
Ω
Room
Fulld
- 700
- 11
700
11
pA
nA
Room
Fulld
- 700
- 11
700
11
pA
nA
V+ = 2.2 V, VNO, VNC = VCOM = 0.5 V/1.5 V
Room
Fulld
- 700
- 11
700
11
pA
nA
1.6
VIN = 0 or V+
Full
Full
Full
Full
V+ = 2.2 V
VNO, VNC = 0.5 V/1.5 V, VCOM = 1.5 V/0.5 V
VNO or VNC = 1.5 V, RL = 300 Ω, CL = 35 pF
Figures 1 and 2
CL = 1 nF, VGEN = 0 V, RGEN = 0 Ω, Figure 3
RL = 50 Ω, CL = 5 pF, f = 1 MHz
VIN = 0 or V+, f = 1 MHz
CON
V+
I+
PC
20
22.5
0.4
5
-1
1
Room
Fulld
61
76
79
Room
Fulld
17
33
36
Room
Room
Room
Room
1
45
2
- 61
- 67
Room
31
Room
98
1.8
VIN = 0 or V+
0.1
V
pF
µA
ns
pC
dB
pF
2.2
1
2.2
V
µA
µW
Document Number: 71742
S-70853–Rev. F, 30-Apr-07
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THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Product is End of Life
DG3000
Vishay Siliconix
SPECIFICATIONS (V+ = 3 V)
Parameter
Symbol
Test Conditions
Otherwise Unless Specified
V+ = 3 V, ± 10 %, VIN = 0.4 V or 2 Ve
Limits
- 40 °C to 85 °C
Temp.a
Min.b
Full
0
Typ.c
Unit
Max.b
Analog Switch
VNO, VNC
VCOM
Analog Signal Ranged
On-Resistanced
RON Flatnessd
Switch Off Leakage Current
f
RON
V+ = 2.7 V, VCOM = 1.5 V, INO, INC = 10 mA
Room
Full
3.3
3.4
RON
Flatness
V+ = 2.7 V, VCOM = 0 to V+, INO, INC = 10 mA
Room
1.3
INO(off)
INC(off)
ICOM(off)
Channel-On Leakage Currentf
V+
ICOM(on)
V+ = 3.3 V
VNO, VNC = 1 V/3 V, VCOM = 3 V/1 V
V+ = 3.3 V, VNO, VNC = VCOM = 1 V/3 V
4.1
4.2
V
Ω
Room
Full
- 800
- 13
800
13
pA
nA
Room
Full
- 800
- 13
800
13
pA
nA
Room
Full
- 800
- 13
800
13
pA
nA
2
Digital Control
Input High Voltage
VINH
Full
Input Low Voltage
VINL
Full
Input Capacitanced
d
Cin
IINL or IINH
Input Current
0.4
Full
VIN = 0 or V+
Full
5
-1
V
pF
1
µA
Dynamic Characteristics
Turn-On Timed
tON
Turn-Off Timed
tOFF
Break-Before-Make Timed
Charge Injection
Off-Isolation
d
d
Crosstalkd
Channel-On
td
QINJ
OIRR
XTALK
NO, NC Off Capacitanced
Capacitanced
VNO or VNC = 2 V, RL = 300 Ω, CL = 35 pF
Figures 1 and 2
CNO(off)
CNC(off)
Room
Full
34
49
52
Room
Full
12
30
33
Room
CL = 1 nF, VGEN = 0 V, RGEN = 0 Ω, Figure 3
RL = 50 Ω, CL = 5 pF, f = 1 MHz
VIN = 0 or V+, f = 1 MHz
CON
1
ns
23
Room
4
Room
- 61
Room
- 67
Room
31
Room
47
pC
dB
pF
Power Supply
Power Supply Range
V+
Power Supply Currentd
I+
Power Consumption
PC
Document Number: 71742
S-70853–Rev. F, 30-Apr-07
2.7
VIN = 0 or V+
0.1
3.3
V
1
µA
3.3
µW
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Vishay Siliconix
SPECIFICATIONS (V+ = 5 V)
Parameter
Symbol
Test Conditions
Otherwise Unless Specified
V+ = 5 V, ± 10 %, VIN = 0.8 V or 2.4 Ve
Limits
- 40 °C to 85 °C
Temp.a
Min.b
Full
0
Typ.c
Unit
Max.b
Analog Switch
Analog Signal Ranged
VNO, VNC
VCOM
V+
On- Resistance
RON
V+ = 4.5 V, VCOM = 3 V, INO, INC = 10 mA
Room
Full
1.4
1.6
RON Flatnessd
RON
Flatness
V+ = 4.5 V, VCOM = 0 to V+, INO, INC = 10 mA
Room
0.5
Switch Off Leakage Current
INO(off)
INC(off)
ICOM(off)
Channel-On Leakage Current
ICOM(on)
V+ = 5.5 V
VNO, VNC = 1 V/4.5 V, VCOM = 4.5 V/1 V
V+ = 5.5 V, V+ = 5.5 V
VNO, VNC = VCOM = 1 V/4.5 V
2.3
2.8
Room
Full
- 1.2
- 21
1.2
21
Room
Full
- 1.2
- 21
1.2
21
Room
Full
- 1.2
- 21
1.2
21
2.4
V
Ω
nA
Digital Control
Input High Voltage
VINH
Full
Input Low Voltage
VINL
Full
Input Capacitance
Cin
IINL or IINH
Input Current
0.8
Full
VIN = 0 or V+
Full
5
-1
V
pF
1
µA
Dynamic Characteristics
Turn-On Timed
tON
Turn-Off Timed
tOFF
Break-Before-Make Timed
Charge Injection
d
VNO or VNC = 3 V, RL = 300 Ω, CL = 35 pF
Figures 1 and 2
td
QINJ
Off-Isolationd
OIRR
Crosstalkd
XTALK
Source-Off Capacitanced
CNO(off)
CNC(off)
Channel-On Capacitanced
CON
Room
Full
24
36
39
Room
Full
9
22
25
Room
CL = 1 nF, VGEN = 0 V, RGEN = 0 Ω, Figure 3
RL = 50 Ω, CL = 5 pF, f = 1 MHz
VIN = 0 or V+, f = 1 MHz
1
ns
15
Room
38
Room
- 61
Room
- 67
Room
30
Room
96
pC
dB
pF
Power Supply
Power Supply Range
V+
Power Supply Current
I+
Power Consumption
PC
4.5
VIN = 0 or V+
0.1
5.5
V
1
µA
5.5
µW
Notes:
a. Room = 25 °C, full = as determined by the operating suffix.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
c. Typical values are for design aid only, not guaranteed nor subject to production testing.
d. Guarantee by design, nor subjected to production test.
e. VIN = input voltage to perform proper function.
f. Guaranteed by 5 V leakage testing, not production tested.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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Document Number: 71742
S-70853–Rev. F, 30-Apr-07
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Product is End of Life
DG3000
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
20
RON - On-Resistance ()
16
V+ = 1.8 V
12
8
V+ = 2 V
4
V+ = 3 V
V+ = 5 V
0
0
1
2
3
4
5
VCOM - Analog Voltage (V)
RON vs. VCOM and Supply Voltage
14
5
V+ = 3 V
12
RON - On-Resistance ()
RON - On-Resistance ()
4
10
8
V+ = 2 V
6
85 °C
25 °C
- 40 °C
4
V+ = 5 V
85 °C
25 °C
- 40 °C
25 °C
85 °C
3
2
- 40 °C
1
2
0
0
1
2
3
4
VCOM - Analog Voltage (V)
0
0.0
5
1.0
1.5
2.0
2.5
3.0
VCOM - Analog Voltage (V)
RON vs. Analog Voltage and Temperature
RON vs. Analog Voltage and Temperature
10 m
10
V+ = 5 V
VIN = 0 V
1m
I+ - Supply Current (A)
I+ - Supply Current (nA)
0.5
1
0.1
100 µ
10 µ
1µ
100 n
0.01
- 60
10 n
- 40
- 20
0
20
40
60
80
Temperature (°C)
Supply Current vs. Temperature
Document Number: 71742
S-70853–Rev. F, 30-Apr-07
100
10
100
1K
10 K
100 K
1M
Input Switching Frequency (Hz)
10 M
Supply Current vs. Input Switching Frequency
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
200
10 000
V+ = 5.5 V
V+ = 5 V
T = 25 °C
0
INO(off)/INC(off)
100
- 200
Leakage Current (pA)
Leakage Current (pA)
1000
ICOM(off)
ICOM(on)
- 400
INO(off)/INC(off)
ICOM(on)
- 600
- 800
10
ICOM(off)
- 1000
1
- 60
- 1200
- 40
- 20
0
20
40
60
80
100
0
1
70
10
Loss, OIRR, XTALK (dB)
50
40
tON V+ = 3 V
30
tON V+ = 5 V
20
tOFF V+ = 2 V
tOFF V+ = 3 V
tOFF V+ = 5 V
10
0
- 60
- 40
- 20
0
4
5
LOSS
0
tON V+ = 2 V
60
3
Leakage vs. Analog Voltage
Leakage Current vs. Temperature
t ON, t OFF - Switching Time (ns)
2
VCOM, V NO, V NC - Analog Voltage
Temperature (°C)
20
40
60
80
- 10
- 20
- 30
- 40
- 50
OIRR
- 60
V+ = 3 V
RL = 50
- 70
XTALK
- 80
- 90
100 K
100
1M
Temperature (°C)
Switching Time vs. Temperature and Supply Voltage
10 M
Frequency (Hz)
100 M
1G
Insertion Loss, Off-Isolation, Crosstalk vs. Frequency
40
2.0
20
1.6
Q - Charge Injection (pC)
V T - Switching Threshold (V)
1.8
1.4
1.2
1.0
0.8
0.6
0.4
V+ = 3 V
0
V+ = 2 V
- 20
- 40
V+ = 5 V
- 60
0.2
- 80
0.0
0
1
2
3
4
5
6
0
1
2
3
4
V+ - Supply Voltage (V)
VCOM - Analog Voltage (v)
Switching Threshold vs. Supply Voltage
Charge Injection vs. Analog Voltage
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Document Number: 71742
S-70853–Rev. F, 30-Apr-07
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Product is End of Life
DG3000
Vishay Siliconix
TEST CIRCUITS
V+
VINH
Logic
Input
VINL
V+
NO or NC
Switch
Input
tr < 5 ns
tf < 5 ns
50 %
Switch Output
COM
VOUT
0.9 x VOUT
Switch
Output
IN
Logic
Input
RL
300 Ω
GND
CL
35 pF
0V
tOFF
tON
Logic "1" = Switch On
Logic input waveforms inverted for switches that have
the opposite logic sense.
CL (includes fixture and stray capacitance)
RL
VOUT = VCOM
R L + R ON
Figure 1. Switching Time
V+
Logic
Input
V+
tr < 5 ns
tf < 5 ns
VINL
COM
NO
VNO
VINH
VO
NC
VNC
RL
300 Ω
IN
CL
35 pF
VNC = VNO
VO
GND
Switch
Output
90 %
0V
tD
tD
CL (includes fixture and stray capacitance)
Figure 2. Break-Before-Make Interval
V+
Rgen
ΔVOUT
V+
COM
NC or NO
VOUT
VOUT
+
Vgen
IN
CL = 1 nF
IN
On
Off
On
GND
Q = ΔVOUT x CL
VIN = 0 - V+
IN depends on switch configuration: input polarity
determined by sense of switch.
Figure 3. Charge Injection
Document Number: 71742
S-70853–Rev. F, 30-Apr-07
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Product is End of Life
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TEST CIRCUITS
V+
10 nF
V+
NC or NO
0 V, 2.4 V
IN
COM
RL
VCOM
Off Isolation = 20 log V
NO/ NC
GND
Analyzer
Figure 4. Off-Isolation
V+
10 nF
V+
COM
Meter
IN
0 V, 2.4 V
NC or NO
HP4192A
Impedance
Analyzer
or Equivalent
GND
f = 1 MHz
Figure 5. Channel Off/On Capacitance
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Document Number: 71742
S-70853–Rev. F, 30-Apr-07
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Product is End of Life
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Vishay Siliconix
PACKAGE OUTLINE
MICRO FOOT: 6-BUMP (3 x 2, 0.5 mm PITCH)
6 x Ø 0.150 ∼ 0.229
Note b
Solder Mask Ø ∼ Pad Dia. + 0.1
0.5
Silicon
0.5
A2
A
A1
Recommended Land Pattern
Bump
Note a
Index-Bump A1
Note c
3
2
1
b Diameter
A
XXX
3000
E
e
B
S
S
Top Side (Die Back)
e
D
Notes (Unless Otherwise Specified):
a. Bump is Eutectic 63/57 Sn/Pb or Lead (Pb)-free Sn/Ag/Cu.
b. Non-solder mask defined copper landing pad.
c. Laser Mark on silicon die back; no coating. Shown is not actual marking; sample only.
EUTECTIC (Sn/Pb)
LEAD (Pb)-FREE (Sn/Ag/Cu)
Millimeters
Inches
a
Inches
Millimetersa
Dim.
Min.
Max.
Min.
Max.
Dim.
Min.
Max.
Min.
Max.
A
0.615
0.715
0.0242
0.0281
A
0.688
0.753
0.0271
0.0296
A1
0.140
0.190
0.0055
0.0075
A1
0.218
0.258
0.0086
0.0102
A2
0.470
0.495
0.0185
0.0195
A2
0.470
0.495
0.0185
0.0195
b
0.180
0.250
0.0071
0.0098
b
0.306
0.346
0.0120
0.0136
D
1.555
1.585
0.0612
0.0624
D
1.555
1.585
0.0612
0.0624
E
1.055
1.085
0.0415
0.0427
E
1.055
1.085
0.0415
0.0427
e
S
0.5 BASIC
0.278
0.293
0.0197 BASIC
0.0109
Notes:
a. Use millimeters as the primary measurement.
0.0115
e
S
0.5 BASIC
0.278
0.293
0.0197 BASIC
0.0109
0.0115
Notes:
a. Use millimeters as the primary measurement.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?71742.
Document Number: 71742
S-70853–Rev. F, 30-Apr-07
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Package Information
Vishay Siliconix
MICRO FOOT: 6-BUMP (3 mm x 2 mm, 0.5 mm PITCH, 165 μm BUMP HEIGHT)
6 x Ø 0.150 ~ 0.229
Note b
Solder Mask Ø ~ Pad Dia. + 0.1
0.5
Silicon
0.5
A2
A
A1
Recommended Land Pattern
Bump
Note a
Index-Bump A1
Note c
3
2
1
b Diameter
A
XXX
3003
E
e
B
S
S
Top Side (Die Back)
e
D
Notes
(unless otherwise specified)
a. Bump is Eutectic 63/57 Sn/Pb or lead (Pb)-free Sn/Ag/Cu.
b. Non-solder mask defined copper landing pad.
c. Laser mark on silicon die back; no coating. Shown is not actual marking; sample only.
EUTECTIC (Sn/Pb)
DIM.
LEAD (Pb)-FREE (Sn/Ag/Cu)
MILLIMETERSa
INCHES
MIN.
MAX.
MIN.
MAX.
A
0.610
0.685
0.0240
0.0270
A1
0.140
0.190
0.0055
A2
0.470
0.495
0.0185
b
0.180
0.250
D
1.490
E
0.990
e
S
MILLIMETERSa
INCHES
MIN.
MAX.
MIN.
MAX.
A
0.688
0.753
0.0271
0.0296
0.0075
A1
0.218
0.258
0.0086
0.0102
0.0195
A2
0.470
0.495
0.0185
0.0195
0.0071
0.0098
b
0.306
0.346
0.0120
0.0136
1.515
0.0587
0.0596
D
1.490
1.515
0.0587
0.0596
1.015
0.0390
0.0400
E
0.990
1.015
0.0390
0.0400
0.5 BASIC
0.245
DIM.
0.258
0.0197 BASIC
0.0096
Note
a. Use millimeters as the primary measurement.
0.0101
e
S
0.5 BASIC
0.245
0.258
0.0197 BASIC
0.0096
0.0101
Note
a. Use millimeters as the primary measurement.
ECN: S11-1065-Rev. A, 13-Jun-11
DWG: 6003
Document Number: 63270
Revision: 13-Jun-11
www.vishay.com
1
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
AN824
Vishay Siliconix
PCB Design and Assembly Guidelines
For MICRO FOOTr Products
Johnson Zhao
INTRODUCTION
Vishay Siliconix’s MICRO FOOT product family is based on a
wafer-level chip-scale packaging (WL-CSP) technology that
implements a solder bump process to eliminate the need for an
outer package to encase the silicon die. MICRO FOOT
products include power MOSFETs, analog switches, and
power ICs.
For battery powered compact devices, this new packaging
technology reduces board space requirements, improves
thermal performance, and mitigates the parasitic effect typical
of leaded packaged products. For example, the 6−bump
MICRO FOOT Si8902EDB common drain power MOSFET,
which measures just 1.6 mm x 2.4 mm, achieves the same
performance as TSSOP−8 devices in a footprint that is 80%
smaller and with a 50% lower height profile (Figure 1). A
MICRO FOOT analog switch, the 6−bump DG3000DB, offers
low charge injection and 1.4 W on−resistance in a footprint
measuring just 1.08 mm x 1.58 mm (Figure 2).
Vishay Siliconix MICRO FOOT products can be handled with
the same process techniques used for high-volume assembly
of packaged surface-mount devices. With proper attention to
PCB and stencil design, the device will achieve reliable
performance without underfill. The advantage of the device’s
small footprint and short thermal path make it an ideal option
for space-constrained applications in portable devices such as
battery packs, PDAs, cellular phones, and notebook
computers.
This application note discusses the mechanical design and
reliability of MICRO FOOT, and then provides guidelines for
board layout, the assembly process, and the PCB rework
process.
FIGURE 1. 3D View of MICRO FOOT Products Si8902DB and
Si8900EDB
3
2
1
0.18 ~ 0.25
A
1.08
0.5
B
0.285
0.285
0.5
1.58
FIGURE 2. Outline of MICRO FOOT CSP & Analog
Switch DG3000DB
Document Number: 71990
06-Jan-03
www.vishay.com
1
AN824
Vishay Siliconix
TABLE 1
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Main Parameters of Solder Bumps in MICRO FOOT Designs
MICRO FOOT CSP
Bump Material
MICRO FOOT CSP MOSFET
Eutectic Solder:
63Sm/37Pb
MICRO FOOT CSP Analog Switch
MICRO FOOT UCSP Analog Switch
Bump Pitch*
Bump Diameter*
Bump Height*
0.8
0.37-0.41
0.26-0.29
0.5
0.18-0.25
0.14-0.19
0.5
0.32-0.34
0.21-0.24
* All measurements in millimeters
MICRO FOOT’S DESIGN AND RELIABILITY
BOARD LAYOUT GUIDELINES
As a mechanical, electrical, and thermal connection between
the device and PCB, the solder bumps of MICRO FOOT
products are mounted on the top active surface of the die.
Table 1 shows the main parameters for solder bumps used in
MICRO FOOT products. A silicon nitride passivation layer is
applied to the active area as the last masking process in
fabrication,ensuring that the device passes the pressure pot
test. A green laser is used to mark the backside of the die
without damaging it. Reliability results for MICRO FOOT
products mounted on a FR-4 board without underfill are shown
in Table 2.
Board materials. Vishay Siliconix MICRO FOOT products are
designed to be reliable on most board types, including organic
boards such as FR-4 or polyamide boards. The package
qualification information is based on the test on 0.5-oz. FR-4
and polyamide boards with NSMD pad design.
TABLE 2
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
MICRO FOOT Reliability Results
Test Condition C: −65_ to 150_C
>500 Cycles
Test condition B: −40_ to 125_C
>1000 Cycles
121_C @ 15PSI 100% Humidity Test
96 Hours
The main failure mechanism associated with wafer-level
chip-scale packaging is fatigue of the solder joint. The results
shown in Table 2 demonstrate that a high level of reliability can
be achieved with proper board design and assembly
techniques.
Land patterns. Two types of land patterns are used for
surface-mount packages. Solder mask defined (SMD) pads
have a solder mask opening smaller than the metal pad
(Figure 3), whereas on-solder mask defined (NSMD) pads
have a metal pad smaller than the solder-mask opening
(Figure 4).
NSMD is recommended for copper etch processes, since it
provides a higher level of control compared to SMD etch
processes. A small-size NSMD pad definition provides more
area (both lateral and vertical) for soldering and more room for
escape routing on the PCB. By contrast, SMD pad definition
introduces a stress concentration point near the solder mask
on the PCB side that may result in solder joint cracking under
extreme fatigue conditions.
Copper pads should be finished with an organic solderability
preservative
(OSP)
coating.
For
electroplated
nickel-immersion gold finish pads, the gold thickness must be
less than 0.5 mm to avoid solder joint embrittlement.
Solder Mask
Copper
Copper
FIGURE 3. SMD
www.vishay.com
2
Solder Mask
FIGURE 4. NSMD
Document Number: 71990
06-Jan-03
AN824
Vishay Siliconix
TABLE 3
Dimensions of Copper Pad and Solder Mask
Opening in PCB and Stencil Aperture
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
Pitch
Copper Pad
Solder Mask
Opening
Stencil
Aperture
0.80 mm
0.30 " 0.01 mm
0.41 " 0.01 mm
0.33 " 0.01 mm
in ciircle aperture
0.50 mm
0.17 " 0.01 mm
0.27 " 0.01 mm
0.30 " 0.01 mm
in square aperture
ASSEMBLY PROCESS
MICRO FOOT products’ surface-mount-assembly operations
include solder paste printing, component placement, and
solder reflow as shown in the process flow chart (Figure 5).
Chip pick-and-placement. MICRO FOOT products can be
picked and placed with standard pick-and-place equipment.
The recommended pick-and-place force is 150 g. Though the
part will self-center during solder reflow, the maximum
placement offset is 0.02 mm.
Reflow Process. MICRO FOOT products can be assembled
using standard SMT reflow processes. Similar to any other
package, the thermal profile at specific board locations must
be determined. Nitrogen purge is recommended during reflow
operation. Figure 6 shows a typical reflow profile.
Thermal Profile
250
200
Temperature (_C)
Board pad design. The landing-pad size for MICRO FOOT
products is determined by the bump pitch as shown in Table 3.
The pad pattern is circular to ensure a symmetric,
barrel-shaped solder bump.
150
100
50
Stencil Design
IIncoming Tape and Reel Inspection
0
0
Solder Paste Printing
100
200
300
400
Time (Seconds
Chip Placement
FIGURE 6. Reflow Profile
Reflow
Solder Joint Inspection
Pack and Ship
FIGURE 5. SMT Assembly Process Flow
PCB REWORK
To replace MICRO FOOT products on PCB, the rework
procedure is much like the rework process for a standard BGA
or CSP, as long as the rework process duplicates the original
reflow profile. The key steps are as follows:
1.
Stencil design. Stencil design is the key to ensuring
maximum solder paste deposition without compromising the
assembly yield from solder joint defects (such as bridging and
extraneous solder spheres). The stencil aperture is dependent
on the copper pad size, the solder mask opening, and the
quantity of solder paste.
Remove the MICRO FOOT device using a convection
nozzle to create localized heating similar to the original
reflow profile. Preheat from the bottom.
2.
Once the nozzle temperature is +190_C, use tweezers to
remove the part to be replaced.
3.
In MICRO FOOT products, the stencil is 0.125-mm (5-mils)
thick. The recommended apertures are shown in Table 3 and
are fabricated by laser cut.
Resurface the pads using a temperature-controlled
soldering iron.
4.
Apply gel flux to the pad.
5.
Use a vacuum needle pick-up tip to pick up the
replacement part, and use a placement jig to placed it
accurately.
6.
Reflow the part using the same convection nozzle, and
preheat from the bottom, matching the original reflow
profile.
Solder-paste printing. The solder-paste printing process
involves transferring solder paste through pre-defined
apertures via application of pressure.
In MICRO FOOT products, the solder paste used is UP78
No-clean eutectic 63 Sn/37Pb type3 or finer solder paste.
Document Number: 71990
06-Jan-03
www.vishay.com
3
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Disclaimer
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definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
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Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
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Revision: 02-Oct-12
1
Document Number: 91000