REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Redrawn. Paragraphs updated to MIL-PRF-38535 requirements. - drw 13-08-27 Charles F. Saffle B Add device 02. - drw 16-06-01 Charles F. Saffle REV SHEET REV B B B B SHEET 15 16 17 18 REV STATUS REV B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Rajesh Pithadia STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http://www.landandmaritime.dla.mil CHECKED BY Rajesh Pithadia APPROVED BY THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A Robert M. Heber DRAWING APPROVAL DATE 07-08-22 REVISION LEVEL B MICROCIRCUIT, DIGITAL-LINEAR, 14-BIT, 400 MSPS DIGITAL TO ANALOG CONVERTER, MONOLITHIC SILICON SIZE CAGE CODE A 67268 SHEET DSCC FORM 2233 APR 97 5962-07204 1 OF 18 5962-E385-16 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 07204 Federal stock class designator \ RHA designator (see 1.2.1) 01 V X C Device type (see 1.2.2) Device class designator (see 1.2.3) Case outline (see 1.2.4) Lead finish (see 1.2.5) / \/ Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type. The device type identifies the circuit function as follows: Device type Generic number 01 DAC5675A 02 DAC5675A Circuit function 14 bit, 400 MSPS digital-to-analog converter, TJ = -55°C to +125°C 14 bit, 400 MSPS digital-to-analog converter, TJ = -55°C to +115°C 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline. The case outline are as designated in MIL-STD-1835 and as follows: Outline letter X Descriptive designator See figure 1 Terminals Package style 52 Quad flat pack with non-conductive tie bar 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-07204 A REVISION LEVEL B SHEET 2 1.3 Absolute maximum ratings. 1/ Supply voltage range: AVDD ...................................................................................................................... DVDD ...................................................................................................................... AVDD to DVDD ......................................................................................................... Voltage between AGND and DGND .......................................................................... CLK, CLKC ................................................................................................................ Digital input D[13…0]A, D[13…0]B 3/, SLEEP, DLLOFF ......................................... IOUT1, OUT2 ............................................................................................................ EXTIO, BIAS .............................................................................................................. Peak input current (any input) .................................................................................... Peak total input current (all inputs) ............................................................................ Storage temperature range (TSTG) .............................................................................. Lead temperature 1.6 mm (1/16 inch) from the case for 10 seconds ........................ Thermal resistance, junction-to-ambient (θJA) ............................................................ Thermal resistance, junction-to-case (θJC) ................................................................. -0.3 V to +3.6 V 2/ -0.3 V to +3.6 V 3/ -3.6 V to +3.6 V -0.3 V to +0.5 V -0.3 V to AVDD +0.3 V 2/ -0.3 V to DVDD +0.3 V -1 V to AVDD + 0.3 V 2/ -1 V to AVDD + 0.3 V 2/ 20 mA -30 mA -65°C to +150°C +260°C 21.813°C/W 4/, 5/ 0.849°C/W 4/, 5/, 6/ 1.4 Recommended operating conditions. Supply voltage : AVDD ...................................................................................................................... DVDD ...................................................................................................................... Operating junction temperature range (TJ): Device type 01 ........................................................................................................ Device type 02 ........................................................................................................ Estimated device life at elevated temperatures electromigration fail modes: 3.3 V 3.3 V -55°C to +125°C -55°C to +115°C ________ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Measured with respect to AGND. 3/ Measured with respect to DGND. 4/ Heat slug connected to PCB thermal plane. Airflow is at 0 LFM (no airflow). 5/ Specified with the thermal bond pad on the backside of the package soldered to a 2 ounce CU plate PCB thermal plane. 6/ Per MIL-STD-883 method 1012.1. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-07204 A REVISION LEVEL B SHEET 3 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 MIL-STD-1835 - Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 MIL-HDBK-780 - List of Standard Microcircuit Drawings. Standard Microcircuit Drawings. (Copies of these documents are available online at http://quicksearch.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 as specified herein, or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Block diagram. The block diagram shall be as specified on figure 3. 3.2.4 Timing waveform. The timing waveform shall be as specified on figure 4. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full junction operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in MIL-PRF-38535. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-07204 A REVISION LEVEL B SHEET 4 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ unless otherwise specified Group A subgroups Device type Limits Min Resolution DC accuracy section Unit Max 1, 2, 3 All 14 Bit All -4 4.6 LSB LSB 2/ Integral nonlinearity INL 1, 2, 3 Differential nonlinearity DNL 1, 2 -2 2.2 3 -2 2.5 2 20 mA Analog output section Full scale output current IO(FS) 1, 2, 3 All Output compliance range AVDD = 3.15 V to 3.45 V, IO(FS) = 20 mA 1, 2, 3 AVDD -1 AVDD + 0.3 V Gain error Without internal reference 1, 2, 3 -10 10 %FSR -10 10 With internal reference Output resistance 1 300 typical kΩ Output capacitance 1 5 typical pF Reference output section Reference voltage V(EXTIO) 1, 2, 3 All 1.17 1.3 V V(EXTIO) 1, 2, 3 All 0.6 1.25 V Input resistance RIN 1 1 typical MΩ Input capacitance CIN 1 100 typical pF Analog supply voltage AVDD 1, 2, 3 Digital supply voltage DVDD 1, 2, 3 Reference input section Input reference voltage Power supply section Power dissipation Analog and digital power supply rejection ratio PD APSRR AVDD = 3.3 V, DVDD = 3.3 V AVDD = 3.15 to 3.45 V 1, 2, 3 1, 2, 3 All 3.15 3.6 V 3.15 3.6 V 01 900 mW 02 850 All DPSRR Analog supply current Digital supply current I(AVDD) I(DVDD) 3/ 3/ 1, 2, 3 1, 2, 3 -0.9 0.9 -0.9 0.9 01 148 02 138 01 130 02 120 %FSR/ V mA mA See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-07204 A REVISION LEVEL B SHEET 5 TABLE I. Electrical performance characteristics – continued. Test Symbol Conditions 1/ unless otherwise specified Group A subgroups Device type Limits Min Unit Max Analog output section Output update rate fCLK 9, 10, 11 All 400 9, 10 01 60 02 62 11 01, 02 57 9, 10 01 62 02 63 11 01, 02 61 9, 10, 11 All 60 All 90 MSPS AC linearity section Total harmonic distortion THD fCLK = 400 MSPS, fOUT = 20.0 MHz fCLK = 400 MSPS, fOUT = 20.0 MHz, for TMIN Spurious free dynamic range to Nyquist 4/, 5/ SFDR fCLK = 400 MSPS, fOUT = 20.0 MHz fCLK = 400 MSPS, fOUT = 20.0 MHz, for TMIN Signal-to-Noise Ratio SNR fCLK = 400 MSPS, fOUT = 20.0 MHz dBc dBc dBc LVDS interface section: nodes D[13…0]A, D[13…0]B Internal termination impedance ZT 1, 2, 3 Input capacitance CI 1 Ω 132 2 typical pF CMOS interface (SLEEP) section High level input voltage VIH 1, 2, 3 Low level input voltage VIL 1, 2, 3 High level input current IIH 1, 2, 3 Low level input current IIL 1, 2, 3 Input capacitance CI 1 All 2 V 0.8 V -10 100 µA -10 10 µA 2 typical pF Clock interface (CLK, CLKC) section Clock differential input voltage |CLKCLKC| 9, 10, 11 Clock duty cycle Common mode voltage range VCM All 0.4 0.8 VPP 9, 10, 11 40 60 % 9, 10, 11 1.6 2.4 V Input resistance Node CLK, CLKC 1 670 typical Ω Input capacitance Node CLK, CLKC 1 2 typical pF See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-07204 A REVISION LEVEL B SHEET 6 TABLE I. Electrical performance characteristics – continued. Test Symbol Conditions 1/ unless otherwise specified Group A subgroups Device type Limits Min Unit Max Clock interface (CLK, CLKC) section - continued Input resistance Differential 1 Input capacitance Differential 1 All 1.3 typical kΩ 1 typical pF Timing section Input setup time tSU 9, 10, 11 Input hold time tH 9, 10, 11 1/ 2/ 3/ 4/ 5/ All 1.5 ns 0 ns Unless otherwise specified, AVDD = 3.3 V, DVDD = 3.3 V, IO(FS) = 20 mA, differential transformer-coupled output, and 50Ω doubly terminated load. -55°C ≤ TJ ≤ +125°C for device type 01. -55°C ≤ TJ ≤ +115°C for device type 02. Measured differential at IOUT1 and IOUT2; 25Ω to AVDD. Measured at fCLK = 400 MSPS and fOUT = 70 MHz. See figure 5. See figure 6. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-07204 A REVISION LEVEL B SHEET 7 Case X FIGURE 1. Case outline. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-07204 A REVISION LEVEL B SHEET 8 Case X Dimensions Symbol Inches Min Max Min Max A1 ---- 0.090 ---- 2.29 A2 ---- 0.105 ---- 2.68 A3 0.002 0.014 0.05 0.36 A4 0.03 BSC 0.762 BSC b 0.006 0.010 0.15 0.25 c 0.004 0.008 0.10 0.20 D1/E1 0.542 0.558 13.77 14.17 D2/E2 0.300 BSC D3/E3 0.940 D4/E4 7.62 BSC 0.960 23.88 0.394 BSC e 24.38 10.0 BSC 0.025 BSC 0.64 BSC F 0.125 0.145 3.18 3.68 J 0.030 0.040 0.76 1.02 K ---- 0.020 ---- 0.51 K1 ---- 0.018 ---- 0.46 L 1.584 1.616 40.23 41.05 N NOTES: 1. 2. 3. 4. 5. 6. Millimeters 52 Controlling dimensions are inches, millimeter dimensions are given for reference only. Ceramic quad flat pack with flat leads brazed to non-conductive tie bar carrier. This package is hermetically sealed with a metal lid. The leads are gold plated and can be solder dipped. All leads are not shown for clarity purposes. Lid and heat sink are connected to GND leads. FIGURE 1. Case outline – continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-07204 A REVISION LEVEL B SHEET 9 Device type All Device type All Case outline X Case outline X Terminal number Terminal symbol Terminal number Terminal symbol 1 D13A 27 D5A 2 D13B 28 D5B 3 D12A 29 D4A 4 D12B 30 D4B 5 D11A 31 D3A 6 D11B 32 D3B 7 D10A 33 D2A 8 D10B 34 D2B 9 D9A 35 D1A 10 D9B 36 D1B 11 D8A 37 D0A 12 D8B 38 D0B 13 AGND 39 AGND 14 D7A 40 SLEEP 15 D7B 41 NC 16 DVDD 42 BIASJ 17 DGND 43 EXTIO 18 DVDD 44 AGND 19 DGND 45 AVDD 20 AGND 46 IOUT1 21 AVDD 47 IOUT2 22 CLKC 48 AVDD 23 CLK 49 AGND 24 D6A 50 AGND 25 D6B 51 AVDD 26 AGND 52 AGND FIGURE 2. Terminal connections. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-07204 A REVISION LEVEL B SHEET 10 Terminal I/O Description AGND I Analog negative supply voltage (ground); pin 13 internally connected to the heat slug and lid (lid is also grounded internally). AVDD I Analog positive supply voltage BIASJ O Full scale output current bias. CLK I External clock input CLKC I Complementary external clock D13A – D0A I LVDS positive input, data bits 13 through 0. D13A is the most significant data bit (MSB). D0A is the least significant data bit (LSB). D13B – D0B I LVDS negative input, data bits 13 through 0. D13B is the most significant data bit (MSB). D0B is the least significant data bit (LSB). DGND I Digital negative supply voltage (ground). DVDD I Digital positive supply voltage. EXTIO I/O IOUT1 O IOUT2 O NC --- SLEEP I Internal reference output or external reference input. Requires a 0.1 µF decoupling capacitor to AGND when used as reference output. DAC current output. Full scale when all input bits are set 0. Connect the reference side of the DAC load resistors to AVDD. DAC complementary current output. Full scale when all input bits are 1. Connect the reference side of the DAC load resistors to AVDD. Not connected in chip. Can be high or low. Asynchronous hardware power down input. Active high. Internal pulldown. FIGURE 2. Terminal connections – continued. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-07204 A REVISION LEVEL B SHEET 11 FIGURE 3. Block diagram. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-07204 A REVISION LEVEL B SHEET 12 FIGURE 4. Timing waveforms. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-07204 A REVISION LEVEL B SHEET 13 FIGURE 5. Spurious free dynamic range vs. frequency. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-07204 A REVISION LEVEL B SHEET 14 FIGURE 6. Spurious free dynamic range vs frequency. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-07204 A REVISION LEVEL B SHEET 15 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall be provided with each lot of microcircuits delivered to this drawing. 4. VERIFICATION 4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. 4.2.1 Additional criteria for device classes Q and V. a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as specified in table IIA herein. c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in MIL-PRF-38535, appendix B. 4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. 4.4.1 Group A inspection. a. Tests shall be as specified in table IIA herein. b. Subgroups 4, 5, 6, 7, and 8 in table I, method 5005 of MIL-STD-883 shall be omitted. 4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein. 4.4.2.1 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-883. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-07204 A REVISION LEVEL B SHEET 16 TABLE IIA. Electrical test requirements. Subgroups (in accordance with MIL-PRF-38535, table III) Device Device class Q class V Test requirements Interim electrical parameters (see 4.2) Final electrical parameters (see 4.2) Group A test requirements (see 4.4) Group C end-point electrical parameters (see 4.4) Group D end-point electrical parameters (see 4.4) Group E end-point electrical parameters (see 4.4) 1, 9 1, 9 1, 2, 3, 9, 10, 11 1/ 1, 2, 3, 9, 10, 11 1/, 2/ 1, 2, 3, 9, 10, 11 1, 2, 3, 9, 10, 11 1, 9 1, 9 2/ 1, 9 1, 9 --- --- 1/ PDA applies to subgroup 1. 2/ Delta limits as specified in table IIB shall be required where specified, and the delta limits shall be computed with reference to the zero hour electrical parameters. TABLE IIB. Burn-in and operating life test. Delta parameters (+25°C). Parameters 1/ Delta limits Reference output, V(EXTIO) ±60 mV Analog supply current, I(AVDD) ±7 mA 1/ These parameters shall be recorded before and after the required burn-in and life test to determine delta limits 4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein. 4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured (see 3.5 herein). a. End-point electrical parameters shall be as specified in table IIA herein. b. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535 for the RHA level being tested. All device classes must meet the postirradiation end-point electrical parameter limits as defined in table I at TA = +25°C ±5°C, after exposure, to the subgroups specified in table IIA herein. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-07204 A REVISION LEVEL B SHEET 17 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes Q and V. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor prepared specification or drawing. 6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. 6.3 Record of users. Military and industrial users should inform DLA Land and Maritime when a system application requires configuration control and which SMD's are applicable to that system. DLA Land and Maritime will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962) should contact DLA Land and Maritime -VA, telephone (614) 692-8108. 6.4 Comments. Comments on this drawing should be directed to DLA Land and Maritime -VA, Columbus, Ohio 43218-3990, or telephone (614) 692-0540. 6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-PRF-38535 and MIL-HDBK-1331. 6.6 Sources of supply. 6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in MIL-HDBK-103 and QML-38535. The vendors listed in MIL-HDBK-103 and QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DLA Land and Maritime -VA and have agreed to this drawing. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-07204 A REVISION LEVEL B SHEET 18 STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 16-06-01 Approved sources of supply for SMD 5962-07204 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DLA Land and Maritime -VA. This information bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DLA Land and Maritime maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/. Standard microcircuit drawing PIN 1/ Vendor CAGE number Vendor similar PIN 2/ 5962-0720401VXC 01295 DAC5675AMHFG-V 5962-0720402VXC 01295 DAC5675AWHFG-V 1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed contact the vendor to determine its availability. 2/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. Vendor CAGE number 01295 Vendor name and address Texas Instruments, Incorporated Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin.