REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add footnotes to figure 3, switching waveforms and test circuit. Update the boilerplate to current requirements as specified in MIL-PRF-38535. Editorial changes throughout – jak. 06-03-09 Thomas M. Hess B Update boilerplate paragraphs to the current MIL-PRF-38535 requirements. LTG 12-04-19 Thomas M. Hess REV SHEET REV SHEET REV STATUS REV B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 PMIC N/A PREPARED BY DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http://www.landandmaritime.dla.mil Marcia B. Kelleher STANDARD MICROCIRCUIT DRAWING CHECKED BY Monica L. Poelking APPROVED BY Michael A. Frye THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A DSCC FORM 2233 APR 97 DRAWING APPROVAL DATE 89-11-20 REVISION LEVEL B MICROCIRCUIT, DIGITAL, HIGH SPEED CMOS, PHASE LOCKED LOOP WITH VOLTAGE CONTROLLED OSCILLATOR, MONOLITHIC SILICON SIZE CAGE CODE A 67268 SHEET 5962-89609 1 OF 13 5962-E209-12 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-89609 01 E A Drawing number Device type (see 1.2.1) Case outline (see 1.2.2) Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number 01 Circuit function 54HC4046A Phase-locked loop with voltage controlled oscillator 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter E Descriptive designator GDIP1-T16 or CDIP2-T16 Terminals Package style 16 Dual-in-line 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range (VCC) ........................................................................... DC input voltage range (VIN) ......................................................................... DC output voltage range (VOUT) .................................................................... Clamp diode current (IIK, IOK) ........................................................................ DC drain current (IOUT) .................................................................................. DC VCC or GND current (ICC, IGND) ................................................................ Storage temperature range (TSTG) ................................................................ Maximum power dissipation (PD) .................................................................. Lead temperature (soldering, 10 seconds) ................................................... Thermal resistance, junction-to-case (θJC) .................................................... Junction temperature (TJ) ............................................................................. -0.5 V dc to +7.0 V dc -0.5 V dc to VCC + 0.5 V dc -0.5 V dc to VCC + 0.5 V dc ±20 mA ±25 mA ±50 mA -65°C to +150°C 500 mW 4/ +300°C See MIL-STD-1835 +175°C 1.4 Recommended operating conditions. 2/ 3/ Supply voltage range (VCC) ........................................................................... Case operating temperature range (TC) ........................................................ Input voltage range (VIN) ............................................................................... Output voltage range (VOUT).......................................................................... Input rise or fall time (tr, tf): VCC = 2.0 V ................................................................................................ VCC = 4.5 V ................................................................................................ VCC = 6.0 V ................................................................................................ +2.0 V dc to +6.0 V dc -55°C to +125°C 0.0 V dc to VCC 0.0 V dc to VCC 0 to 1000 ns 0 to 500 ns 0 to 400 ns ________ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Unless otherwise specified, all voltages are referenced to ground. 3/ The limits for the parameters specified herein shall apply over the full specified VCC range and case temperature range of -55°C to +125°C. 4/ For TA = +100°C to +125°C, derate linearly at 8 mW/°C to 300mW. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89609 A REVISION LEVEL B SHEET 2 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 MIL-STD-1835 - Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 MIL-HDBK-780 - List of Standard Microcircuit Drawings. Standard Microcircuit Drawings. (Copies of these documents are available online at https://assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents cited in the solicitation or contract. JEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC Standard No. 7 - Standard for Description of 54/74HCXXXXX and 54/74HCTXXXXX Advanced High-Speed CMOS Devices. (Copies of these documents are available online at http://www.jedec.org or from JEDEC – Solid State Technology th Association, 3103 North 10 Street, Suite 240-S Arlington, VA 22201). 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for nonJAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A "Q" or "QML" certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Logic diagram. The logic diagram shall be as specified on figure 2. 3.2.4 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 3. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89609 A REVISION LEVEL B SHEET 3 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. 3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a "Q" or "QML" certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply shall affirm that the manufacturer's product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime -VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritime's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89609 A REVISION LEVEL B SHEET 4 TABLE I. Electrical performance characteristics. Test Symbol Test conditions 1/ -55°C ≤ TC ≤ +125°C unless otherwise specified VCC Group A subgroups Limits Min Unit Max VOLTAGE-CONTROLLED OSCILLATOR SECTION High level output voltage Low level output voltage High level input voltage Low level input voltage VOH VOL VIH VIL VIN = VIH minimum or VIL maximum IOH = -20 µA 3.0 V 1, 2, 3 2.9 4.5 V 4.4 6.0 V 5.9 V VIN = VIH minimum or VIL maximum IOH = -4.0 mA 4.5 V 1, 2, 3 3.98 V VIN = VIH minimum or VIL maximum IOH = -5.2 mA 6.0 V 1, 2, 3 5.48 V 3.0 V 1, 2, 3 VIN = VIH minimum or VIL maximum IOL = +20 µA 0.1 4.5 V 0.1 6.0 V 0.1 V VIN = VIH minimum or VIL maximum IOL = +4.0 mA 4.5 V 1, 2, 3 0.4 V VIN = VIH minimum or VIL maximum IOL = +5.2 mA 6.0 V 1, 2, 3 0.4 V 2/ 3.0 V 1, 2, 3 2.1 V 4.5 V 1, 2, 3 3.15 V 6.0 V 1, 2, 3 4.2 V 3.0 V 1, 2, 3 0.9 V 4.5 V 1, 2, 3 1.35 V 6.0 V 1, 2, 3 1.8 V 2/ 6.0 V 1, 2, 3 ±1.0 µA R1 and R2 range RRNG 3/ 4/ 4.5 V 1 3.0 300 kΩ C1 capacitance range CRNG 4/ 4.5 V 1 0.0 5/ pF VCOIN operating voltage range VOP 4/ 6/ 3.0 V 1 0.9 1.9 V 4.5 V 1 0.9 3.2 6.0 V 1 0.9 4.6 4.5 V 9 C1 = 50 pF, R1 = 3.5 kΩ R2 = ∞ C1 = 0 pF, R1 = 9.1 kΩ R2 = ∞ 4.5 V 9 24 MHz 4.5 V 9 38 MHz C1 = 40 pF, R1 = 3 kΩ R2 = ∞, VCOIN = VCC/2 4.5 V 9 17 MHz C1 = 100 pF, R1 = 100 kΩ R2 = ∞ 4.5 V 9 R2 = 220 kΩ C1 = 1 nF 4.5 V 9 Input leakage current Frequency stability with temperature change Maximum frequency Center frequency Frequency linearity Offset frequency IIN ∆f/∆T 4/ fMAX 4/ fCTR 4/ ∆fVCO 4/ fOFF 4/ VIN = VCC or GND R1 = 100 kΩ, R2 = ∞ 0.11 %/°C 0.4 % 400 kHz See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89609 A REVISION LEVEL B SHEET 5 TABLE I. Electrical performance characteristics – Continued. Test Symbol Test conditions 1/ -55°C ≤ TC ≤ +125°C unless otherwise specified VCC Group A subgroups Limits Min Unit Max DEMODULATOR SECTION Resistor range RS 4/ Offset voltage, VCOIN to VDEM VOFF 4/ RD 4/ Quiescent supply current Output voltage versus input frequency ICC At RS > 300 kΩ leakage current can influence VDEM OUT VIN = VVCO(IN) = VCC/2, values taken over RS range VDEM(OUT) = VCC/2 VIN = VCC or GND VOUT/fIN R1 = 100 kΩ, R2 = ∞ 4/ C1 = 100 pF, RS = 10 kΩ R3 = 100 kΩ, C2 = 100 pF 50 300 4.5 V 3.0 V 50 300 6.0 V 50 300 3.0 V 1 1 kΩ ±30.0 4.5 V ±20.0 6.0 V ±10.0 3.0 V 1 25 4.5 V 1 0.1 6.0 V 1 0.1 6.0 V 1 8.0 6.0 V 2, 3 160.0 4.5 V 1 330 2.0 V 1, 2, 3 mV Ω µA mV/ kHz PHASE COMPARATOR SECTION High level output voltage Low level output voltage VOH VOL VIN = VIH minimum or VIL maximum IOH = -20 µA CMOS loads 1.9 4.5 V 4.4 6.0 V 5.9 V VIN = VIH minimum or VIL maximum IOH = -4.0 mA TTL loads 4.5 V 1, 2, 3 3.98 V VIN = VIH minimum or VIL maximum IOH = -5.2 mA TTL loads 6.0 V 1, 2, 3 5.48 V VIN = VIH minimum or VIL maximum IOL = +20 µA CMOS loads 2.0 V 1, 2, 3 4.5 V 0.1 V 0.1 6.0 V 0.1 VIN = VIH minimum or VIL maximum IOL = +4.0 mA TTL loads 4.5 V 1, 2, 3 0.4 V VIN = VIH minimum or VIL maximum IOL = +5.2 mA TTL loads 6.0 V 1, 2, 3 0.4 V See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89609 A REVISION LEVEL B SHEET 6 TABLE I. Electrical performance characteristics – Continued. Test Symbol Test conditions 1/ -55°C ≤ TC ≤ +125°C unless otherwise specified VCC Group A subgroups Limits Min Unit Max PHASE COMPARATOR SECTION – Continued. High level input voltage Low level input voltage Input leakage current Three-state output current VIH VIL IIN IOZ Functional tests Propagation delay time, SIGIN or COMPIN to PC1OUT 2.0 V 2/ 1.5 V 4.5 V 3.15 V 6.0 V 4.2 V 2.0 V 2/ VIN = VCC or GND 0.5 V 4.5 V 1.35 V 6.0 V 1.8 V ±5.0 µA 2.0 V VIN = VCC or GND 4.5 V ±29.0 6.0 V ±45.0 6.0 V ±10.0 µA 9 200 ns 10, 11 300 1, 2, 3, ±0.5 7, 8 CL = 50 pF See figure 3 2.0 V 4.5 V tPLH2, tPHL2 7/ 2.0 V 4.5 V 6.0 V Propagation delay time, SIGIN or COMPIN to PC3OUT 1, 2, 3 ±11.0 6.0 V Propagation delay time, SIGIN or COMPIN to PCPOUT 1, 2, 3 3.0 V See 4.3.1d tPLH1, tPHL1 7/ 1, 2, 3 tPLH3, tPHL3 7/ 2.0 V 4.5 V 6.0 V 9 40 10, 11 60 9 34 10, 11 51 9 300 10, 11 450 9 60 10, 11 90 9 70 10, 11 109 9 245 10, 11 307 9 49 10, 11 74 9 42 10, 11 63 ns ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89609 A REVISION LEVEL B SHEET 7 TABLE I. Electrical performance characteristics – Continued. Test Symbol Test conditions 1/ -55°C ≤ TC ≤ +125°C unless otherwise specified VCC Group A subgroups Limits Min Unit Max PHASE COMPARATOR SECTION – Continued. Propagation delay time, output enable, SIGIN or COMPIN to PC2OUT tPZH, tPZL 7/ 2.0 V 4.5 V 6.0 V Propagation delay time, output disable, SIGIN or COMPIN to PC2OUT tPHZ, tPLZ 7/ 2.0 V 4.5 V 6.0 V Output transition time tTHL, tTLH 8/ 2.0 V 4.5 V 6.0 V 9 265 10, 11 400 9 53 10, 11 80 9 45 10, 11 68 9 315 10, 11 475 9 63 10, 11 95 9 74 10, 11 112 9 75 10, 11 110 9 15 10, 11 22 9 13 10, 11 19 ns ns ns 1/ For power supply of 5 V ±10 percent, the worst case output voltages (VOH and VOL) occur for high-speed CMOS at 4.5 V. Thus, the 4.5 V values should be used when designing with this supply. Worst cases VIH and VIL occur at VCC = 5.5 V and 4.5 V, respectively. (The VIH value at VCC = 5.5 V is 3.85 V). The worse case leakage currents (IIN, ICC, and IOZ) occur for CMOS at the higher voltage, so the 6.0 V values should be used. Power dissipation capacitance (CPD), typically 2 40 pF, determines the no load dynamic power consumption, PD = CPDVCC f + ICCVCC, and the no load dynamic current consumption, IS = CPDVCCf + ICC. 2/ VIH and VIL tests are not required if applied as a forcing function for VOH or VOL tests. 3/ The value for R1 and R2 in parallel should exceed 2.7 kΩ. 4/ This parameter is characterization data and is guaranteed, if not tested, to the limits specified in table I. 5/ No maximum limit for C1 capacitance range. 6/ The maximum operating voltage can be as high as VCC – 0.9 V; however, this may result in an increased offset voltage. 7/ AC testing at VCC = 2.0 V and VCC = 6.0 V shall be guaranteed, if not tested, to the specified limits in table I. 8/ Transition time (tTLH, tTHL), if not tested, shall be guaranteed to the specified limits. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89609 A REVISION LEVEL B SHEET 8 Device type 01 Case outline E Terminal number Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PCPOUT PC1OUT COMPIN VCOOUT INH C1A C1B GND VCOIN DEMOUT R1 R2 PC2OUT SIGIN PC3OUT VCC Pin names Pin description PCPOUT Phase comparator pulse output PC1OUT Phase comparator 1 output COMPIN Comparator 1 output VCOOUT VCO output INH Inhibit input C1A Capacitor C1 connection A C1B Capacitor C1 connection B GND Ground VCOIN VCO input DEMOUT Demodulator output R1 Resistor R1 connection R2 Resistor R2 connection PC2OUT Phase comparator 2 output SIGIN Signal input PC3OUT Phase comparator 3 output VCC Positive supply voltage FIGURE 1. Terminal connections. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89609 A REVISION LEVEL B SHEET 9 FIGURE 2. Logic diagram. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89609 A REVISION LEVEL B SHEET 10 NOTES: 1. CL = 50 pF or equivalent (includes test jig and probe capacitance). 2. Input signal from pulse generator: VIN = 0.0 V to VCC; PRR ≤ 1 MHz; ZO = 50Ω; tr = 6.0 ns; tf = 6.0 ns; tr and tf shall be measured from 10% of VCC to 90% of VCC and from 90% of VCC to 10% of VCC, respectively; duty cycle = 50 percent. 3. The outputs are measured one at a time with one transition per measurement. FIGURE 3. Switching waveforms and test circuit. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89609 A REVISION LEVEL B SHEET 11 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA = +125°C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. TABLE II. Electrical test requirements. MIL-STD-883 test requirements Subgroups (in accordance with MIL-STD-883, method 5005, table I) Interim electrical parameters (method 5004) 1 Final electrical test parameters (method 5004) 1*, 2, 3, 7, 8, 9 Group A test requirements (method 5005) 1, 2, 3, 4, 7, 8, 9, 10**, 11** Groups C and D end-point electrical parameters (method 5005) 1, 2, 3 * PDA applies to subgroup 1. ** Subgroups 10 and 11, if not tested, shall be guaranteed to the specified limits in table I. 4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD-883 including groups A, B, C, and D inspections. The following additional criteria shall apply. 4.3.1 Group A inspection. a. Tests shall be as specified in table II herein. b. Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted. c. Subgroup 4 (CIN measurement) shall be measured only for the initial test and after process or design changes which may affect capacitance. Test all applicable pins on 5 devices with zero failures. d. Subgroups 7 and 8 tests shall verify the functionality of the device. These tests form a part of the vendors test tape and shall be maintained and available from the approved source of supply. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89609 A REVISION LEVEL B SHEET 12 4.3.2 Groups C and D inspections. a. End-point electrical parameters shall be as specified in table II herein. b. Steady-state life test conditions, method 1005 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-883. (2) TA = +125°C, minimum. (3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535, appendix A. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractorprepared specification or drawing. 6.3 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. 6.4 Record of users. Military and industrial users shall inform DLA Land and Maritime when a system application requires configuration control and the applicable SMD to that system. DLA Land and Maritime will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronics devices (FSC 5962) should contact DLA Land and Maritime -VA, telephone (614) 692-0544. 6.5 Comments. Comments on this drawing should be directed to DLA Land and Maritime -VA, Columbus, Ohio 432183990, or telephone (614) 692-0540. 6.6 Approved sources of supply. Approved sources of supply are listed in MIL-HDBK-103. The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by DLA Land and Maritime -VA. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-89609 A REVISION LEVEL B SHEET 13 STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 12-04-19 Approved sources of supply for SMD 5962-89609 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DLA Land and Maritime -VA. This information bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DLA Land and Maritime maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/. Standard microcircuit drawing PIN 1/ Vendor CAGE number Vendor similar PIN 2/ 5962-8960901EA 01295 CD54HC4046AF3A 1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed contact the vendor to determine its availability. 2/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. Vendor CAGE number 01295 Vendor name and address Texas Instruments Inc. Semiconductor Group 8505 Forest Ln. P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin.