IRLZ34S, IRLZ34L, SiHLZ34S, SiHLZ34L www.vishay.com Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • • • • • • • 60 RDS(on) () VGS = 5 V 0.05 Qg max. (nC) 35 Qgs (nC) 7.1 Qgd (nC) 25 Configuration Single D Note * This datasheet provides information about parts that are RoHS-compliant and / or parts that are non-RoHS-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant. Please see the information / tables in this datasheet for details. D2PAK (TO-263) I2PAK (TO-262) G G G D S Advanced process technology Surface mount (IRLZ34S, SiHLZ34S) Low-profile through-hole (IRLZ34L, SiHLZ34L) Available 175 °C operating temperature Fast switching Available Fully avalanche rated Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 DESCRIPTION Third generation power MOSFETs from Vishay utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that Power MOSFETs are known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The D2PAK is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible on-resistance in any existing surface mount package. The D2PAK is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0 W in a typical surface mount application. The through-hole version (IRLZ34L, SiHLZ34L) is available for low-profile applications. D S S N-Channel MOSFET ORDERING INFORMATION Package D2PAK (TO-263) I2PAK (TO-262) Lead (Pb)-free and Halogen-free SiHLZ34S-GE3 - Lead (Pb)-free IRLZ34SPbF IRLZ34LPbF ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 60 Gate-Source Voltage VGS ± 10 Continuous Drain Current Pulsed Drain VGS at 5 V TC = 25 °C TC = 100 °C Current a ID IDM Linear Derating Factor Single Pulse Avalanche Energy b EAS Maximum Power Dissipation TC = 25 °C Maximum Power Dissipation (PCB mount) e TA = 25 °C Peak Diode Recovery dV/dt c Operating Junction and Storage Temperature Range Soldering Recommendations (Peak temperature) d for 10 s PD UNIT V 30 21 A 110 0.59 W/°C 128 mJ 88 3.7 dV/dt 4.5 TJ, Tstg -55 to +175 300 W V/ns °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = 25 V, Starting TJ = 25 °C, L = 285 μH, Rg = 25 , IAS = 30 A (see fig. 12). c. ISD 30 A, dI/dt 200 A/μs, VDD VDS, TJ 175 °C. d. 1.6 mm from case. e. When mounted on 1" square PCB (FR-4 or G-10 material). S16-0015-Rev. E, 18-Jan-16 Document Number: 90418 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRLZ34S, IRLZ34L, SiHLZ34S, SiHLZ34L www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL MIN. TYP. MAX. Maximum Junction-to-Ambient (PCB mount) a RthJA - - 40 Maximum Junction-to-Case (Drain) RthJC - - 1.7 UNIT °C/W Note a. When mounted on 1" square PCB (FR-4 or G-10 material). SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS VGS = 0, ID = 250 μA 60 - - V VDS/TJ Reference to 25 °C, ID = 1 mA - 0.07 - V/°C VGS(th) VDS = VGS, ID = 250 μA 1.0 - 2.0 V Gate-Source Leakage IGSS VGS = ± 10 V - - ± 100 nA Zero Gate Voltage Drain Current IDSS VDS = 60 V, VGS = 0 V - - 25 VDS = 48 V, VGS = 0 V, TJ = 150 °C - - 250 Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Drain-Source On-State Resistance Forward Transconductance RDS(on) VGS = 5 V ID = 18 A b - - 0.05 VGS = 4 V ID = 15 A b - - 0.07 gfs VDS = 25 V, ID = 18 A 12 - - VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 - 1600 - - 660 - - 170 - - - 35 - - 7.1 μA S Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd - - 25 Turn-On Delay Time td(on) - 14 - Rise Time Turn-Off Delay Time Fall Time Internal Source Inductance tr td(off) VGS = 5 V ID = 30 A, VDS = 48 V, see fig. 6 and 13 b VDD = 30 V, ID = 30 A, Rg = 6 , RD = 1 , see fig. 10 b tf LS Between lead, and center of die contact - 170 - - 30 - - 56 - - 7.5 - - - 30 - - 110 pF nC ns nH Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Current a Body Diode Voltage IS ISM VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode D A G TJ = 25 °C, IS = 30 A, VGS = 0 S Vb TJ = 25 °C, IF = 30 A, dI/dt = 100 A/μs b - - 1.6 V - 120 180 ns - 700 1300 nC Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width 300 μs; duty cycle 2 %. S16-0015-Rev. E, 18-Jan-16 Document Number: 90418 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRLZ34S, IRLZ34L, SiHLZ34S, SiHLZ34L www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) Fig. 1 - Typical Output Characteristics, TC = 25 °C Fig. 3 - Typical Transfer Characteristics Fig. 2 - Typical Output Characteristics, TC = 175 °C Fig. 4 - Normalized On-Resistance vs. Temperature S16-0015-Rev. E, 18-Jan-16 Document Number: 90418 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRLZ34S, IRLZ34L, SiHLZ34S, SiHLZ34L www.vishay.com Vishay Siliconix Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 8 - Maximum Safe Operating Area S16-0015-Rev. E, 18-Jan-16 Document Number: 90418 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRLZ34S, IRLZ34L, SiHLZ34S, SiHLZ34L www.vishay.com Vishay Siliconix RD VDS VGS D.U.T. Rg + - VDD 5V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Fig. 10a - Switching Time Test Circuit VDS 90 % 10 % VGS td(on) Fig. 9 - Maximum Drain Current vs. Case Temperature tr td(off) tf Fig. 10b - Switching Time Waveforms Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case S16-0015-Rev. E, 18-Jan-16 Document Number: 90418 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRLZ34S, IRLZ34L, SiHLZ34S, SiHLZ34L www.vishay.com Vishay Siliconix L Vary tp to obtain required IAS VDS VDS tp VDD Rg D.U.T. + - I AS V DD VDS 5V 0.01 W tp Fig. 12a - Unclamped Inductive Test Circuit IAS Fig. 12b - Unclamped Inductive Waveforms Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ QG 5V 12 V 0.2 µF 0.3 µF QGS QGD + D.U.T. VG - VDS VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform S16-0015-Rev. E, 18-Jan-16 Fig. 13b - Gate Charge Test Circuit Document Number: 90418 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRLZ34S, IRLZ34L, SiHLZ34S, SiHLZ34L www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + + - - Rg • • • • dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?90418. S16-0015-Rev. E, 18-Jan-16 Document Number: 90418 7 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix I2PAK (TO-262) (HIGH VOLTAGE) A (Datum A) E B c2 A E A L1 Seating plane D1 D C L2 C B B L A c 3 x b2 E1 A1 3xb Section A - A Base metal 2xe b1, b3 Plating 0.010 M A M B c1 c (b, b2) Lead tip Section B - B and C - C Scale: None MILLIMETERS INCHES MILLIMETERS INCHES DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX. A 4.06 4.83 0.160 0.190 D 8.38 9.65 0.330 0.380 A1 2.03 3.02 0.080 0.119 D1 6.86 - 0.270 - b 0.51 0.99 0.020 0.039 E 9.65 10.67 0.380 0.420 b1 0.51 0.89 0.020 0.035 E1 6.22 - 0.245 - b2 1.14 1.78 0.045 0.070 e b3 1.14 1.73 0.045 0.068 L 13.46 14.10 0.530 0.555 c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.065 c1 0.38 0.58 0.015 0.023 L2 3.56 3.71 0.140 0.146 c2 1.14 1.65 0.045 0.065 2.54 BSC 0.100 BSC ECN: S-82442-Rev. A, 27-Oct-08 DWG: 5977 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the outmost extremes of the plastic body. 3. Thermal pad contour optional within dimension E, L1, D1, and E1. 4. Dimension b1 and c1 apply to base metal only. Document Number: 91367 Revision: 27-Oct-08 www.vishay.com 1 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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We confirm that all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU. Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000