SiHG24N65E www.vishay.com Vishay Siliconix E Series Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) at TJ max. • Low Figure-of-Merit (FOM) Ron x Qg 700 RDS(on) max. at 25 °C () VGS = 10 V Qg max. (nC) 122 Qgs (nC) 21 Qgd (nC) • • • • • 0.145 37 Configuration Single Low Input Capacitance (Ciss) Reduced Switching and Conduction Losses Ultra Low Gate Charge (Qg) Avalanche Energy Rated (UIS) Material categorization: For definitions please see www.vishay.com/doc?99912 APPLICATIONS D TO-247AC • • • • Server and Telecom Power Supplies Switch Mode Power Supplies (SMPS) Power Factor Correction Power Supplies (PFC) Lighting - High-Intensity Discharge (HID) - Fluorescent Ballast Lighting • Industrial - Welding - Induction Heating - Motor Drives - Battery Chargers - Renewable Energy - Solar (PV Inverters) G S D G S N-Channel MOSFET ORDERING INFORMATION Package TO-247AC Lead (Pb)-free SiHG24N65E-E3 Lead (Pb)-free and Halogen-free SiHG24N65E-GE3 ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER Drain-Source Voltage Gate-Source Voltage LIMIT VDS 650 VGS Gate-Source Voltage AC (f > 1 Hz) Continuous Drain Current (TJ = 150 °C) SYMBOL VGS at 10 V TC = 25 °C TC = 100 °C Pulsed Drain Currenta ID ± 20 UNIT V 30 24 16 A IDM 70 2 W/°C Single Pulse Avalanche Energyb EAS 508 mJ Maximum Power Dissipation PD 250 W TJ, Tstg - 55 to + 150 °C Linear Derating Factor Operating Junction and Storage Temperature Range Drain-Source Voltage Slope Reverse Diode TJ = 125 °C dV/dtd Soldering Recommendations (Peak Temperature) for 10 s dV/dt 37 11 300c V/ns °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature. b. VDD = 50 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 , IAS = 6 A. c. 1.6 mm from case. d. ISD ID, dI/dt = 100 A/μs, starting TJ = 25 °C. S12-3104-Rev. F, 24-Dec-12 Document Number: 91476 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHG24N65E www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum Junction-to-Ambient RthJA - 62 Maximum Junction-to-Case (Drain) RthJC - 0.5 UNIT °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage (N) Gate-Source Leakage Zero Gate Voltage Drain Current VDS VGS = 0 V, ID = 250 μA 650 - - V VDS/TJ Reference to 25 °C, ID = 250 μA - 0.72 - V/°C VGS(th) VDS = VGS, ID = 250 μA 2 - 4 V nA VGS = ± 20 V - - ± 100 VDS = 650 V, VGS = 0 V - - 1 VDS = 520 V, VGS = 0 V, TJ = 125 °C - - 10 IGSS IDSS μA - 0.120 0.145 gfs VDS = 8 V, ID = 5 A - 7.1 - S Input Capacitance Ciss 2740 - pF Coss - 122 - Reverse Transfer Capacitance Crss VGS = 0 V, VDS = 100 V, f = 1 MHz - Output Capacitance - 4 - Effective Output Capacitance, Energy Relateda Co(er) - 93 - Effective Output Capacitance, Time Relatedb Co(tr) - 352 - Qg - 81 122 - 21 - - 37 - Drain-Source On-State Resistance Forward Transconductance RDS(on) VGS = 10 V ID = 12 A Dynamic Total Gate Charge VDS = 0 V to 520 V, VGS = 0 V VGS = 10 V Gate-Source Charge Qgs Gate-Drain Charge Qgd Turn-On Delay Time td(on) - 24 48 tr - 84 126 - 70 105 Rise Time Turn-Off Delay Time td(off) Fall Time tf Gate Input Resistance Rg ID = 12 A, VDS = 520 V VDD = 520 V, ID = 12 A, VGS = 10 V, Rg = 9.1 f = 1 MHz, open drain nC ns - 69 104 - 0.68 - - - 24 - - 70 - - 1.2 - 433 - ns - 7.3 - μC - 28 - A Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Current ISM Diode Forward Voltage VSD Reverse Recovery Time trr Reverse Recovery Charge Qrr Reverse Recovery Current IRRM MOSFET symbol showing the integral reverse p - n junction diode D A G S TJ = 25 °C, IS = 12 A, VGS = 0 V TJ = 25 °C, IF = IS = 12 A, dI/dt = 100 A/μs, VR = 25 V V Notes a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS. b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS. S12-3104-Rev. F, 24-Dec-12 Document Number: 91476 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHG24N65E www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 3 TOP 15 V 14 V 13 V 12 V 60 TJ = 25 °C ID = 12 A RDS(on), Drain-to-Source On Resistance (Normalized) ID, Drain-to-Source Current (A) 80 11 V 40 10 V 20 9V 2.5 2 1.5 1 VGS = 10 V 0.5 5V 0 0 0 5 10 15 20 25 TJ, Junction Temperature (°C) Fig. 1 - Typical Output Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature 10 000 TOP 15 V 14 V 13 V 12 V 11 V 10 V TJ = 150 °C Ciss Capacitance (pF) ID, Drain-to-Source Current (A) 20 40 60 80 100 120 140 160 VDS, Drain-to-Source Voltage (V) 60 40 - 60 - 40 - 20 0 30 9V 20 VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds Shorted Crss = Cgd Coss = Cds + Cgd 1000 Coss 100 10 8V Crss 5V 1 0 0 5 10 15 20 25 30 0 VDS, Drain-to-Source Voltage (V) 200 400 300 500 600 VDS, Drain-to-Source Voltage (V) Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 2 - Typical Output Characteristics 80 24 VGS, Gate-to-Source Voltage (V) ID, Drain-to-Source Current (A) 100 60 40 TJ = 150 °C 20 TJ = 25 °C 0 VDS = 520 V VDS = 335 V VDS = 130 V 20 16 12 8 4 0 0 5 10 15 20 25 0 30 60 90 120 150 VGS, Gate-to-Source Voltage (V) Qg, Total Gate Charge (nC) Fig. 3 - Typical Transfer Characteristics Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage S12-3104-Rev. F, 24-Dec-12 Document Number: 91476 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHG24N65E www.vishay.com Vishay Siliconix 25 ID, Drain Current (A) ISD, Reverse Drain Current (A) 100 TJ = 150 °C 10 TJ = 25 °C 1 20 15 10 5 VGS = 0 V 0 0.1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 25 1.6 VSD, Source-Drain Voltage (V) 75 100 125 150 TJ, Case Temperature (°C) Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 9 - Maximum Drain Current vs. Case Temperature 825 1000 Operation in this area limited by RDS(on) 800 VDS, Drain-to-Source Brakdown Voltage (V) ID, Drain Current (A) 50 IDM limited 100 10 100 μs Limited by R DS(on)* 1 TC = 25 °C TJ = 150 °C Single Pulse 0.1 1 ms 775 750 725 700 675 BVDSS Limited 10 ms 650 - 60 - 40 - 20 0 1 10 100 10 000 1000 VDS, Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) Fig. 8 - Maximum Safe Operating Area Fig. 10 - Temperature vs. Drain-to-Source Voltage Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 0.0001 0.001 0.01 0.1 1 Pulse Time (s) Fig. 11 - Normalized Thermal Transient Impedance, Junction-to-Case S12-3104-Rev. F, 24-Dec-12 Document Number: 91476 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHG24N65E www.vishay.com Vishay Siliconix RD VDS QG 10 V VGS D.U.T. RG QGS + - VDD QGD VG 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Charge Fig. 12 - Switching Time Test Circuit Fig. 16 - Basic Gate Charge Waveform Current regulator Same type as D.U.T. VDS 90 % 50 kΩ 12 V 0.2 µF 0.3 µF + 10 % VGS D.U.T. td(on) td(off) tf tr - VDS VGS 3 mA Fig. 13 - Switching Time Waveforms IG ID Current sampling resistors Fig. 17 - Gate Charge Test Circuit L Vary tp to obtain required IAS VDS D.U.T RG + - IAS V DD 10 V 0.01 Ω tp Fig. 14 - Unclamped Inductive Test Circuit VDS tp VDD VDS IAS Fig. 15 - Unclamped Inductive Waveforms S12-3104-Rev. F, 24-Dec-12 Document Number: 91476 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHG24N65E www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 18 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91476. S12-3104-Rev. F, 24-Dec-12 Document Number: 91476 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix TO-247AC (High Voltage) A A 4 E B 3 R/2 E/2 7 ØP Ø k M DBM A2 S (Datum B) ØP1 A D2 Q 4 4 2xR (2) D1 D 1 2 4 D 3 Thermal pad 5 L1 C L A See view B 2 x b2 3xb 0.10 M C A M 4 E1 0.01 M D B M View A - A C 2x e A1 b4 Planting Lead Assignments 1. Gate 2. Drain 3. Source 4. Drain D DE (b1, b3, b5) Base metal E C (c) C c1 (b, b2, b4) (4) Section C - C, D - D, E - E View B MILLIMETERS DIM. MIN. MAX. A 4.58 5.31 A1 2.21 2.59 A2 1.17 2.49 b 0.99 1.40 b1 0.99 1.35 b2 1.53 2.39 b3 1.65 2.37 b4 2.42 3.43 b5 2.59 3.38 c 0.38 0.86 c1 0.38 0.76 D 19.71 20.82 D1 13.08 ECN: X13-0103-Rev. D, 01-Jul-13 DWG: 5971 INCHES MIN. MAX. 0.180 0.209 0.087 0.102 0.046 0.098 0.039 0.055 0.039 0.053 0.060 0.094 0.065 0.093 0.095 0.135 0.102 0.133 0.015 0.034 0.015 0.030 0.776 0.820 0.515 - DIM. D2 E E1 e Øk L L1 N ØP Ø P1 Q R S MILLIMETERS MIN. MAX. 0.51 1.30 15.29 15.87 13.72 5.46 BSC 0.254 14.20 16.25 3.71 4.29 7.62 BSC 3.51 3.66 7.39 5.31 5.69 4.52 5.49 5.51 BSC INCHES MIN. MAX. 0.020 0.051 0.602 0.625 0.540 0.215 BSC 0.010 0.559 0.640 0.146 0.169 0.300 BSC 0.138 0.144 0.291 0.209 0.224 0.178 0.216 0.217 BSC Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Contour of slot optional. 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body. 4. Thermal pad contour optional with dimensions D1 and E1. 5. Lead finish uncontrolled in L1. 6. Ø P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154"). 7. Outline conforms to JEDEC outline TO-247 with exception of dimension c. 8. Xian and Mingxin actually photo. Revision: 01-Jul-13 Document Number: 91360 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000