SiHB24N65E www.vishay.com Vishay Siliconix E Series Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) at TJ max. RDS(on) max. at 25 °C (Ω) • Low figure-of-merit (FOM) Ron x Qg 700 VGS = 10 V Qg max. (nC) • • • • • 0.145 122 Qgs (nC) 21 Qgd (nC) 37 Configuration Single D APPLICATIONS • • • • Server and telecom power supplies Switch mode power supplies (SMPS) Power factor correction power supplies (PFC) Lighting - High-intensity discharge (HID) - Fluorescent ballast lighting • Industrial - Welding - Induction heating - Motor drives - Battery chargers - Renewable energy - Solar (PV inverters) D2PAK (TO-263) G S G D S Low input capacitance (Ciss) Reduced switching and conduction losses Ultra low gate charge (Qg) Avalanche energy rated (UIS) Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 N-Channel MOSFET ORDERING INFORMATION D2PAK (TO-263) SiHB24N65E-GE3 SiHB24N65ET1-GE3 SiHB24N65ET5-GE3 Package Lead (Pb)-free and Halogen-free ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 650 Gate-Source Voltage VGS ± 30 Continuous Drain Current (TJ = 150 °C) VGS at 10 V TC = 25 °C TC = 100 °C Pulsed Drain Current a ID Maximum Power Dissipation Operating Junction and Storage Temperature Range Drain-Source Voltage Slope TJ = 125 °C Reverse Diode dV/dt d Soldering Recommendations (Peak Temperature) c for 10 s V 24 16 A IDM 70 2 W/°C EAS 508 mJ Linear Derating Factor Single Pulse Avalanche Energy b UNIT PD 250 W TJ, Tstg -55 to +150 °C dV/dt 37 11 300 V/ns °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature. b. VDD = 50 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 Ω, IAS = 6 A. c. 1.6 mm from case. d. ISD ≤ ID, dI/dt = 100 A/μs, starting TJ = 25 °C. S15-0291-Rev. H, 23-Feb-15 Document Number: 91477 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB24N65E www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum Junction-to-Ambient RthJA - 62 Maximum Junction-to-Case (Drain) RthJC - 0.5 UNIT °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage (N) VDS VGS = 0 V, ID = 250 μA 650 - - V ΔVDS/TJ Reference to 25 °C, ID = 250 μA - 0.72 - V/°C VGS(th) VDS = VGS, ID = 250 μA 2 - 4 V Gate-Source Leakage IGSS Zero Gate Voltage Drain Current IDSS Drain-Source On-State Resistance Forward Transconductance RDS(on) VGS = ± 20 V - - ± 100 nA VGS = ± 30 V - - ±1 μA VDS = 650 V, VGS = 0 V - - 1 VDS = 520 V, VGS = 0 V, TJ = 125 °C - - 10 - 0.120 0.145 Ω - S VGS = 10 V ID = 12 A gfs VDS = 8 V, ID = 5 A - 7.1 Input Capacitance Ciss 2740 - Coss - 122 - Reverse Transfer Capacitance Crss VGS = 0 V, VDS = 100 V, f = 1 MHz - Output Capacitance - 4 - Effective Output Capacitance, Energy Related a Co(er) - 93 - Effective Output Capacitance, Time Related b Co(tr) - 352 - - 81 122 - 21 - - 37 - μA Dynamic pF VDS = 0 V to 520 V, VGS = 0 V Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Turn-On Delay Time td(on) - 24 48 tr VDD = 520 V, ID = 12 A, VGS = 10 V, Rg = 9.1 Ω - 84 126 - 70 105 - 69 104 f = 1 MHz, open drain - 0.68 - - - 24 Rise Time Turn-Off Delay Time td(off) Fall Time tf Gate Input Resistance Rg VGS = 10 V ID = 12 A, VDS = 520 V nC ns Ω Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Current ISM Diode Forward Voltage VSD Reverse Recovery Time trr Reverse Recovery Charge Qrr Reverse Recovery Current IRRM MOSFET symbol showing the integral reverse p - n junction diode D A G S TJ = 25 °C, IS = 12 A, VGS = 0 V TJ = 25 °C, IF = IS = 12 A, dI/dt = 100 A/μs, VR = 25 V - - 70 - - 1.2 V - 433 - ns - 7.3 - μC - 28 - A Notes a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS. b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS. S15-0291-Rev. H, 23-Feb-15 Document Number: 91477 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB24N65E www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 3 TOP 15 V 14 V 13 V 12 V 60 TJ = 25 °C ID = 12 A RDS(on), Drain-to-Source On Resistance (Normalized) ID, Drain-to-Source Current (A) 80 11 V 40 10 V 20 9V 2.5 2 1.5 1 VGS = 10 V 0.5 5V 0 0 0 5 10 15 20 25 TJ, Junction Temperature (°C) Fig. 1 - Typical Output Characteristics Fig. 3 - Normalized On-Resistance vs. Temperature 10 000 TOP 15 V 14 V 13 V 12 V 11 V 10 V TJ = 150 °C Ciss Capacitance (pF) ID, Drain-to-Source Current (A) 20 40 60 80 100 120 140 160 VDS, Drain-to-Source Voltage (V) 60 40 - 60 - 40 - 20 0 30 9V 20 VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds Shorted Crss = Cgd Coss = Cds + Cgd 1000 Coss 100 10 8V Crss 5V 1 0 0 5 10 15 20 25 30 0 VDS, Drain-to-Source Voltage (V) 200 300 400 500 600 VDS, Drain-to-Source Voltage (V) Fig. 4 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 1 - Typical Output Characteristics 80 24 VGS, Gate-to-Source Voltage (V) ID, Drain-to-Source Current (A) 100 60 40 TJ = 150 °C 20 TJ = 25 °C 0 VDS = 520 V VDS = 335 V VDS = 130 V 20 16 12 8 4 0 0 5 10 15 20 25 VGS, Gate-to-Source Voltage (V) Fig. 2 - Typical Transfer Characteristics S15-0291-Rev. H, 23-Feb-15 0 30 60 90 120 150 Qg, Total Gate Charge (nC) Fig. 5 - Typical Gate Charge vs. Gate-to-Source Voltage Document Number: 91477 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB24N65E www.vishay.com Vishay Siliconix 25 ID, Drain Current (A) ISD, Reverse Drain Current (A) 100 TJ = 150 °C 10 TJ = 25 °C 1 20 15 10 5 VGS = 0 V 0 0.1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 25 1.6 VSD, Source-Drain Voltage (V) 75 100 125 150 TJ, Case Temperature (°C) Fig. 6 - Typical Source-Drain Diode Forward Voltage Fig. 8 - Maximum Drain Current vs. Case Temperature 1000 825 VDS, Drain-to-Source Breakdown Voltage (V) Operation in this area limited by RDS(on) ID, Drain Current (A) 50 IDM limited 100 10 100 μs Limited by R DS(on)* 1 TC = 25 °C TJ = 150 °C Single Pulse 0.1 1 ms 800 775 750 725 700 675 BVDSS Limited 10 ms 650 - 60 - 40 - 20 0 1000 10 100 10 000 VDS, Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified 1 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) Fig. 7 - Maximum Safe Operating Area Fig. 9 - Temperature vs. Drain-to-Source Voltage Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 0.0001 0.001 0.01 0.1 1 Pulse Time (s) Fig. 10 - Normalized Thermal Transient Impedance, Junction-to-Case S15-0291-Rev. H, 23-Feb-15 Document Number: 91477 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB24N65E www.vishay.com Vishay Siliconix RD VDS QG 10 V VGS D.U.T. RG QGS + - VDD QGD VG 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Charge Fig. 11 - Switching Time Test Circuit Fig. 15 - Basic Gate Charge Waveform Current regulator Same type as D.U.T. VDS 90 % 50 kΩ 12 V 0.2 µF 0.3 µF + 10 % VGS D.U.T. td(on) td(off) tf tr - VDS VGS 3 mA Fig. 12 - Switching Time Waveforms IG ID Current sampling resistors Fig. 16 - Gate Charge Test Circuit L Vary tp to obtain required IAS VDS D.U.T RG + - IAS V DD 10 V 0.01 Ω tp Fig. 13 - Unclamped Inductive Test Circuit VDS tp VDD VDS IAS Fig. 14 - Unclamped Inductive Waveforms S15-0291-Rev. H, 23-Feb-15 Document Number: 91477 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB24N65E www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 17 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91477. S15-0291-Rev. H, 23-Feb-15 Document Number: 91477 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix TO-263AB (HIGH VOLTAGE) A (Datum A) 3 A 4 4 L1 B A E c2 H Gauge plane 4 0° to 8° 5 D B Detail A Seating plane H 1 2 C 3 C L L3 L4 Detail “A” Rotated 90° CW scale 8:1 L2 B A1 B A 2 x b2 c 2xb E 0.010 M A M B ± 0.004 M B 2xe Plating 5 b1, b3 Base metal c1 (c) D1 4 5 (b, b2) Lead tip MILLIMETERS DIM. MIN. MAX. View A - A INCHES MIN. 4 E1 Section B - B and C - C Scale: none MILLIMETERS MAX. DIM. MIN. INCHES MAX. MIN. MAX. A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 - A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420 6.22 - 0.245 - b 0.51 0.99 0.020 0.039 E1 b1 0.51 0.89 0.020 0.035 e b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625 b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110 2.54 BSC 0.100 BSC c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066 c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070 c2 1.14 1.65 0.045 0.065 L3 D 8.38 9.65 0.330 0.380 L4 0.25 BSC 4.78 5.28 0.010 BSC 0.188 0.208 ECN: S-82110-Rev. A, 15-Sep-08 DWG: 5970 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions are shown in millimeters (inches). 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outmost extremes of the plastic body at datum A. 4. Thermal PAD contour optional within dimension E, L1, D1 and E1. 5. Dimension b1 and c1 apply to base metal only. 6. Datum A and B to be determined at datum plane H. 7. Outline conforms to JEDEC outline to TO-263AB. Document Number: 91364 Revision: 15-Sep-08 www.vishay.com 1 AN826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead 0.420 0.355 0.635 (16.129) (9.017) (10.668) 0.145 (3.683) 0.135 (3.429) 0.200 0.050 (5.080) (1.257) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Document Number: 73397 11-Apr-05 www.vishay.com 1 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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