SiHD6N62E Datasheet

SiHD6N62E
www.vishay.com
Vishay Siliconix
E Series Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V) at TJ max.
• Low figure-of-merit (FOM) Ron x Qg
700
RDS(on) max. at 25 °C (Ω)
VGS = 10 V
Qg max. (nC)
•
•
•
•
•
0.9
34
Qgs (nC)
4
Qgd (nC)
8
Configuration
Single
Low input capacitance (Ciss)
Reduced switching and conduction losses
Ultra low gate charge (Qg)
Avalanche energy rated (UIS)
Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
APPLICATIONS
D
•
•
•
•
Server and telecom power supplies
Switch mode power supplies (SMPS)
Power factor correction power supplies (PFC)
Lighting
- High-intensity discharge (HID)
- Fluorescent ballast lighting
• Industrial
- Welding
- Induction heating
- Motor drives
- Battery chargers
- Renewable energy
- Solar (PV inverters)
DPAK
(TO-252)
D
G
G
S
S
N-Channel MOSFET
ORDERING INFORMATION
Package
DPAK (TO-252)
Lead (Pb)-free and Halogen-free
SiHD6N62E-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
620
Gate-Source Voltage
VGS
± 30
Continuous Drain Current (TJ = 150 °C)
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed Drain Current a
ID
IDM
Linear Derating Factor
UNIT
V
6
4
A
12
0.63
W/°C
Single Pulse Avalanche Energy b
EAS
88
mJ
Maximum Power Dissipation
PD
78
W
TJ, Tstg
-55 to +150
°C
Operating Junction and Storage Temperature Range
Drain-Source Voltage Slope
TJ = 125 °C
Reverse Diode dV/dt d
Soldering Recommendations (Peak Temperature) c
for 10 s
dV/dt
37
12
300
V/ns
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature.
b. VDD = 50 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 Ω, IAS = 2.5 A.
c. 1.6 mm from case.
d. ISD ≤ ID, dI/dt = 100 A/μs, starting TJ = 25 °C.
S15-0291-Rev. B, 23-Feb-15
Document Number: 91558
1
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHD6N62E
www.vishay.com
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
RthJA
-
62
Maximum Junction-to-Case (Drain)
RthJC
-
1.6
UNIT
°C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage (N)
VDS
VGS = 0 V, ID = 250 μA
620
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.76
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
2
-
4
V
Gate-Source Leakage
IGSS
Zero Gate Voltage Drain Current
IDSS
Drain-Source On-State Resistance
Forward Transconductance
RDS(on)
VGS = ± 20 V
-
-
± 100
nA
VGS = ± 30 V
-
-
±1
μA
VDS = 620 V, VGS = 0 V
-
-
1
VDS = 496 V, VGS = 0 V, TJ = 125 °C
-
-
10
-
0.78
0.90
Ω
-
S
VGS = 10 V
ID = 3 A
gfs
VDS = 30 V, ID = 3 A
-
1.8
Input Capacitance
Ciss
578
-
Coss
-
36
-
Reverse Transfer Capacitance
Crss
VGS = 0 V,
VDS = 100 V,
f = 1 MHz
-
Output Capacitance
-
4
-
Effective Output Capacitance, Energy
Related a
Co(er)
-
31
-
Effective Output Capacitance, Time
Related b
Co(tr)
-
87
-
-
17
34
-
4
-
-
8
-
μA
Dynamic
pF
VDS = 0 V to 496 V, VGS = 0 V
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Turn-On Delay Time
td(on)
-
12
24
tr
VDD = 496 V, ID = 3 A,
VGS = 10 V, Rg = 9.1 Ω
-
10
20
-
22
44
-
16
32
f = 1 MHz, open drain
-
1.3
-
-
-
7
Rise Time
Turn-Off Delay Time
td(off)
Fall Time
tf
Gate Input Resistance
Rg
VGS = 10 V
ID = 3 A, VDS = 496 V
nC
ns
Ω
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Current
ISM
Diode Forward Voltage
VSD
Reverse Recovery Time
trr
Reverse Recovery Charge
Qrr
Reverse Recovery Current
IRRM
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
TJ = 25 °C, IS = 3 A, VGS = 0 V
TJ = 25 °C, IF = IS = 3 A,
dI/dt = 100 A/μs, VR = 400 V
S
-
-
12
-
0.9
1.2
V
-
190
-
ns
-
1.3
-
μC
-
11
-
A
Notes
a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS.
b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS.
S15-0291-Rev. B, 23-Feb-15
Document Number: 91558
2
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHD6N62E
www.vishay.com
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
TOP
15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
6V
BOTTOM 5 V
12
9
3
TJ = 25 °C
ID = 3 A
RDS(on), Drain-to-Source
On Resistance (Normalized)
ID, Drain-to-Source Current (A)
15
6
3
2.5
2
1.5
1
0.5
0
- 60 - 40 - 20 0
0
0
5
10
15
20
25
30
TJ, Junction Temperature (°C)
Fig. 1 - Typical Output Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
6V
BOTTOM 5 V
10 000
TJ = 150 °C
Capacitance (pF)
ID, Drain-to-Source Current (A)
TOP
4
Ciss
1000
Coss
ġ
ġ
Crss
10
2
ġ
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted
Crss = Cgd
Coss = Cds + Cgd
100
ġ
1
0
0
5
10
15
20
25
30
0
VDS, Drain-to-Source Voltage (V)
100
200
300
500
600
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
15
VGS, Gate-to-Source Voltage (V)
24
TJ = 25 °C
12
400
VDS, Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
ID, Drain-to-Source Current (A)
20 40 60 80 100 120 140 160
VDS, Drain-to-Source Voltage (V)
8
6
VGS = 10 V
9
TJ = 150 °C
6
3
VDS = 32 V
VDS = 496 V
VDS = 310 V
VDS = 124 V
20
16
12
8
4
0
0
0
5
10
15
20
25
0
5
10
15
20
25
30
VGS, Gate-to-Source Voltage (V)
Qg, Total Gate Charge (nC)
Fig. 3 - Typical Transfer Characteristics
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
S15-0291-Rev. B, 23-Feb-15
Document Number: 91558
3
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHD6N62E
www.vishay.com
Vishay Siliconix
ISD, Reverse Drain Current (A)
6
10
ID, Drain Current (A)
5
TJ = 150 °C
TJ = 25 °C
1
ġ
4
3
2
1
VGS = 0 V
0
0.1
0.2
0.4
0.6
0.8
1
1.2
1.4
25
1.6
VSD, Source-Drain Voltage (V)
IDM = Limited
100 μs
S
Limited
by RD (on)*
1 ms
0.1
10 ms
TC = 25 °C
TJ = 150 °C
Single Pulse
725
700
675
650
625
600
BVDSS Limited
575
- 60 - 40 - 20 0
10
100
1000
VDS, Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
Fig. 8 - Maximum Safe Operating Area
Normalized Effective Transient
Thermal Impedance
150
750
VDS, Drain-to-Source
Breakdown Voltage (V)
ID, Drain Current (A)
125
Fig. 9 - Maximum Drain Current vs. Case Temperature
10
0.01
1
100
775
Operation in this Area
Limited by RDS(on)
1
75
TC, Case Temperature (°C)
Fig. 7 - Typical Source-Drain Diode Forward Voltage
100
50
Fig. 10 - Temperature vs. Drain-to-Source Voltage
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
0.0001
0.001
0.01
0.1
1
Pulse Time (s)
Fig. 11 - Normalized Thermal Transient Impedance, Junction-to-Case
S15-0291-Rev. B, 23-Feb-15
Document Number: 91558
4
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHD6N62E
www.vishay.com
Vishay Siliconix
RD
VDS
QG
10 V
VGS
D.U.T.
RG
QGS
+
- VDD
QGD
VG
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Charge
Fig. 12 - Switching Time Test Circuit
Fig. 16 - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
VDS
90 %
50 kΩ
12 V
0.2 µF
0.3 µF
+
10 %
VGS
D.U.T.
td(on)
td(off) tf
tr
-
VDS
VGS
3 mA
Fig. 13 - Switching Time Waveforms
IG
ID
Current sampling resistors
Fig. 17 - Gate Charge Test Circuit
L
Vary tp to obtain
required IAS
VDS
D.U.T
RG
+
-
IAS
V DD
10 V
0.01 Ω
tp
Fig. 14 - Unclamped Inductive Test Circuit
VDS
tp
VDD
VDS
IAS
Fig. 15 - Unclamped Inductive Waveforms
S15-0291-Rev. B, 23-Feb-15
Document Number: 91558
5
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHD6N62E
www.vishay.com
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 18 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91558.
S15-0291-Rev. B, 23-Feb-15
Document Number: 91558
6
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
TO-252AA Case Outline
E
MILLIMETERS
A
C2
e
b2
D1
e1
E1
L
gage plane height (0.5 mm)
L4
b
L5
H
D
L3
b3
C
A1
INCHES
DIM.
MIN.
MAX.
MIN.
MAX.
A
2.18
2.38
0.086
0.094
A1
-
0.127
-
0.005
b
0.64
0.88
0.025
0.035
b2
0.76
1.14
0.030
0.045
b3
4.95
5.46
0.195
0.215
0.024
C
0.46
0.61
0.018
C2
0.46
0.89
0.018
0.035
D
5.97
6.22
0.235
0.245
D1
4.10
-
0.161
-
E
6.35
6.73
0.250
0.265
E1
4.32
-
0.170
-
H
9.40
10.41
0.370
0.410
e
2.28 BSC
e1
0.090 BSC
4.56 BSC
0.180 BSC
L
1.40
1.78
0.055
0.070
L3
0.89
1.27
0.035
0.050
L4
-
1.02
-
0.040
L5
1.01
1.52
0.040
0.060
ECN: T16-0236-Rev. P, 16-May-16
DWG: 5347
Notes
• Dimension L3 is for reference only.
Revision: 16-May-16
Document Number: 71197
1
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
TO-252AA (HIGH VOLTAGE)
E
b3
E1
L3
D1
D
H
L4
b2
b
A
c2
e
A1
L1
L
c
θ
L2
MILLIMETERS
INCHES
DIM.
MIN.
MAX.
MIN.
MAX.
E
6.40
6.73
0.252
0.265
L
1.40
1.77
0.055
L1
2.743 REF
L2
0.070
0.108 REF
0.508 BSC
0.020 BSC
L3
0.89
1.27
0.035
0.050
L4
0.64
1.01
0.025
0.040
D
6.00
6.22
0.236
0.245
H
9.40
10.40
0.370
0.409
b
0.64
0.88
0.025
0.035
b2
0.77
1.14
0.030
0.045
b3
5.21
5.46
0.205
e
2.286 BSC
0.215
0.090 BSC
A
2.20
2.38
0.087
A1
0.00
0.13
0.000
0.094
0.005
c
0.45
0.60
0.018
0.024
c2
0.45
0.58
0.018
0.023
D1
5.30
-
0.209
-
E1
4.40
-
0.173
-
θ
0'
10'
0'
10'
ECN: S-81965-Rev. A, 15-Sep-08
DWG: 5973
Notes
1. Package body sizes exclude mold flash, protrusion or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 0.10 mm per side.
2. Package body sizes determined at the outermost extremes of the plastic body exclusive of mold flash, gate burrs and interlead flash, but
including any mismatch between the top and bottom of the plastic body.
3. The package top may be smaller than the package bottom.
4. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.10 mm total in excess of "b" dimension at maximum
material condition. The dambar cannot be located on the lower radius of the foot.
Document Number: 91344
Revision: 15-Sep-08
www.vishay.com
1
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR DPAK (TO-252)
0.224
0.243
0.087
(2.202)
0.090
(2.286)
(10.668)
0.420
(6.180)
(5.690)
0.180
0.055
(4.572)
(1.397)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
Return to Index
APPLICATION NOTE
Document Number: 72594
Revision: 21-Jan-08
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Revision: 02-Oct-12
1
Document Number: 91000