SiHB25N50E Datasheet

SiHB25N50E
www.vishay.com
Vishay Siliconix
E Series Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V) at TJ max.
RDS(on) max. at 25 °C (Ω)
• Low figure-of-merit (FOM): Ron x Qg
550
VGS = 10 V
• Low input capacitance (Ciss)
0.145
Qg (Max.) (nC)
86
• Reduced switching and conduction losses
Qgs (nC)
14
• Low gate charge (Qg)
Qgd (nC)
25
• Avalanche energy rated (UIS)
Configuration
Single
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
D
APPLICATONS
D2PAK (TO-263)
• Hard switched topologies
• Power factor correction power supplies (PFC)
G
• Switch mode power supplies (SMPS)
• Computing
G D
- PC silver box / ATX power supplies
S
S
• Lighting
N-Channel MOSFET
- Two stage LED lighting
ORDERING INFORMATION
Package
D2PAK (TO-263)
Lead (Pb)-free and Halogen-free
SiHB25N50E-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
500
Gate-Source Voltage
VGS
± 30
Continuous Drain Current (TJ = 150 °C)
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed Drain Current a
ID
UNIT
V
26
16
A
IDM
50
0.2
W/°C
Single Pulse Avalanche Energy b
EAS
273
mJ
Maximum Power Dissipation
PD
250
W
TJ, Tstg
-55 to +150
°C
Linear Derating Factor
Operating Junction and Storage Temperature Range
Drain-Source Voltage Slope
VDS = 0 V to 80 % VDS
Reverse Diode dV/dt d
Soldering Recommendations (Peak Temperature) c
dV/dt
for 10 s
65
25
300
V/ns
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature.
b. VDD = 50 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 Ω, IAS = 4.4 A.
c. 1.6 mm from case.
d. ISD ≤ ID, dI/dt = 100 A/μs, starting TJ = 25 °C.
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
Maximum Junction-to-Ambient
RthJA
-
62
Maximum Junction-to-Case (Drain)
RthJC
-
0.5
S15-0493-Rev. A, 16-Mar-15
MAX.
UNIT
°C/W
Document Number: 91646
1
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHB25N50E
www.vishay.com
Vishay Siliconix
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage (N)
Gate-Source Leakage
Zero Gate Voltage Drain Current
Drain-Source On-State Resistance
Forward Transconductance
VDS
VGS = 0 V, ID = 250 μA
500
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.59
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
2.0
-
4.0
V
VGS = ± 20 V
-
-
± 100
nA
μA
IGSS
IDSS
RDS(on)
gfs
VGS = ± 30 V
-
-
±1
VDS = 500 V, VGS = 0 V
-
-
1
VDS = 400 V, VGS = 0 V, TJ = 125 °C
-
-
25
-
0.125
0.145
Ω
-
6.6
-
S
VGS = 10 V
ID = 12 A
VDS = 30 V, ID = 12 A
μA
Dynamic
Input Capacitance
Ciss
VGS = 0 V,
-
1980
-
Output Capacitance
Coss
VDS = 100 V,
-
105
-
Reverse Transfer Capacitance
Crss
f = 1 MHz
-
8
-
Effective Output Capacitance, Energy
Related a
Co(er)
-
105
-
Effective Output Capacitance, Time
Related b
Co(tr)
-
285
-
-
57
86
-
14
-
pF
VDS = 0 V to 400 V, VGS = 0 V
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
-
25
-
Turn-On Delay Time
td(on)
-
19
38
tr
-
36
72
-
57
86
-
29
58
-
0.56
-
-
-
12
S
-
-
50
TJ = 25 °C, IS = 16.5 A, VGS = 0 V
-
-
1.2
V
-
338
-
ns
-
5.3
-
μC
-
29
-
A
Rise Time
Turn-Off Delay Time
td(off)
Fall Time
tf
Gate Input Resistance
Rg
VGS = 10 V
ID = 12 A, VDS = 400 V
VDD = 400 V, ID = 12 A
Rg = 9.1 Ω, VGS = 10 V
f = 1 MHz, open drain
nC
ns
Ω
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Current
ISM
Diode Forward Voltage
VSD
Reverse Recovery Time
trr
Reverse Recovery Charge
Qrr
Reverse Recovery Current
IRRM
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
TJ = 25 °C, IF = IS,
dI/dt = 100 A/μs, VR = 25 V
Notes
a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS.
b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS.
S15-0493-Rev. A, 16-Mar-15
Document Number: 91646
2
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHB25N50E
www.vishay.com
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
TOP
15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
6V
BOTTOM 5 V
50
40
ID = 12 A
30
20
10
0
2.5
2.0
1.5
1.0
VGS = 10 V
0.5
0
0
5
10
15
20
25
30
-60 -40 -20
VDS, Drain-to-Source Voltage (V)
Fig. 4 - Normalized On-Resistance vs. Temperature
Fig. 1 - Typical Output Characteristics
40
10 000
15 V
14 V
13 V
12 V
11 V
10 V
9V
8V
7V
6V
BOTTOM 5 V
TJ = 150 °C
Ciss
1000
C, Capacitance (pF)
ID, Drain-to-Source Current (A)
TOP
30
0 20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
20
Coss
100
Crss
10
10
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds shorted
Crss = Cgd
Coss = Cds + Cgd
1
0
0
5
10
15
20
25
VDS, Drain-to-Source Voltage (V)
0
30
100
200
300
400
VDS, Drain-to-Source Voltage (V)
500
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 2 - Typical Output Characteristics
70
12
TJ = 25 °C
5000
10
50
8
Coss
40
Coss (pF)
ID, Drain-to-Source Current (A)
60
TJ = 150 °C
30
Eoss
6
500
Eoss (μJ)
ID, Drain-to-Source Current (A)
60
3.0
TJ = 25 °C
RDS(on), Drain-to-Source On-Resistance
(Normalized)
70
4
20
VDS = 28.6 V
2
10
0
0
5
10
15
20
VGS, Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
S15-0493-Rev. A, 16-Mar-15
25
50
0
0
100
200
300
400
500
VDS
Fig. 6 - COSS and EOSS vs. VDS
Document Number: 91646
3
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHB25N50E
www.vishay.com
Vishay Siliconix
30
VDS = 400 V
VDS = 250 V
VDS = 100 V
20
24
ID, Drain Current (A)
VGS, Gate-to-Source Voltage (V)
24
16
12
8
0
0
20
40
60
80
Qg, Total Gate Charge (nC)
100
120
Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage
25
50
75
100
125
TC, Case Temperature (°C)
150
Fig. 10 - Maximum Drain Current vs. Case Temperature
100
650
VDS, Drain-to-Source Breakdown Voltage (V)
ISD, Reverse Drain Current (A)
12
6
4
0
TJ = 150 °C
10
TJ = 25 °C
1
VGS = 0 V
0.1
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VSD, Source-Drain Voltage (V)
Fig. 8 - Typical Source-Drain Diode Forward Voltage
Operation in this Area
Limited by RDS(on)
100
ID, Drain Current (A)
18
625
600
575
550
525
500
475
ID = 250 μA
450
-60 -40 -20
0 20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
Fig. 11 - Typical Drain-to-Source Voltage vs. Temperature
IDM Limited
10
100 μs
Limited by RDS(on)*
1 ms
1
10 ms
0.1
TC = 25 °C
TJ = 150 °C
Single Pulse
BVDSS Limited
0.01
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Fig. 9 - Maximum Safe Operating Area
S15-0493-Rev. A, 16-Mar-15
Document Number: 91646
4
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHB25N50E
www.vishay.com
Vishay Siliconix
1
Normalized Effective Transient
Thermal Impedance
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
0.0001
0.001
0.01
Pulse Time (s)
0.1
1
Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case
RD
VDS
VDS
tp
VGS
VDD
D.U.T.
RG
+
- VDD
VDS
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
IAS
Fig. 13 - Switching Time Test Circuit
Fig. 16 - Unclamped Inductive Waveforms
VDS
QG
10 V
90 %
QGS
10 %
VGS
QGD
VG
td(on)
td(off) tf
tr
Charge
Fig. 14 - Switching Time Waveforms
Fig. 17 - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
L
Vary tp to obtain
required IAS
VDS
50 kΩ
12 V
0.2 µF
0.3 µF
D.U.T
RG
+
-
IAS
+
V DD
D.U.T.
-
VDS
VGS
10 V
tp
0.01 Ω
3 mA
IG
ID
Current sampling resistors
Fig. 15 - Unclamped Inductive Test Circuit
S15-0493-Rev. A, 16-Mar-15
Fig. 18 - Gate Charge Test Circuit
Document Number: 91646
5
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHB25N50E
www.vishay.com
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 19 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91646.
S15-0493-Rev. A, 16-Mar-15
Document Number: 91646
6
For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
AN826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead
0.420
0.355
0.635
(16.129)
(9.017)
(10.668)
0.145
(3.683)
0.135
(3.429)
0.200
0.050
(5.080)
(1.257)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
Document Number: 73397
11-Apr-05
www.vishay.com
1
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Revision: 02-Oct-12
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Document Number: 91000