HIP6020 ® Data Sheet February 1999 Advanced Dual PWM and Dual Linear Power Controller Features The HIP6020 provides the power control and protection for four output voltages in high-performance, graphics intensive microprocessor and computer applications. The IC integrates two PWM controllers and two linear controllers, as well as the monitoring and protection functions into a 28-pin SOIC package. One PWM controller regulates the microprocessor core voltage with a synchronous-rectified buck converter. The second PWM controller supplies the computer system’s AGP 1.5V or 3.3V bus power with a standard buck converter. The linear controllers regulate power for the 1.5V GTL bus and the 1.8V power for the North/South Bridge core voltage and/or cache memory circuits. The HIP6020 includes an Intel-compatible, TTL 5-input digital-to-analog converter (DAC) that adjusts the core PWM output voltage from 1.3VDC to 2.05VDC in 0.05V steps and from 2.1VDC to 3.5VDC in 0.1V increments. The precision reference and voltage-mode control provide ±1% static regulation. The second PWM controller’s output is userselectable, through a TTL-compatible signal applied at the SELECT pin, for levels of 1.5V or 3.3V with ±3% accuracy. The linear regulators use external N-Channel MOSFETs or bipolar NPN pass transistors to provide fixed output voltages of 1.5V ±3% (VOUT3) and 1.8V ±3% (VOUT4). The HIP6020 monitors all the output voltages. A single Power Good signal is issued when the core is within ±10% of the DAC setting and all other outputs are above their undervoltage levels. Additional built-in over-voltage protection for the core output uses the lower MOSFET to prevent output voltages above 115% of the DAC setting. The PWM controllers’ over-current function monitors the output current by using the voltage drop across the upper MOSFET’s rDS(ON) , eliminating the need for a current sensing resistor. Ordering Information PART NUMBER HIP6020CB HIP6020EVAL1 TEMP. RANGE (oC) 0 to 70 PACKAGE 28 Ld SOIC Evaluation Board PKG. NO. M28.3 • Provides 4 Regulated Voltages - Microprocessor Core, AGP Bus, North/South Bridge and/or Cache Memory, and GTL Bus Power • Drives N-Channel MOSFETs • Linear Regulator Drives Compatible with both MOSFET and Bipolar Series Pass Transistors • Simple Single-Loop Control Designs - Voltage-Mode PWM Control • Fast PWM Converter Transient Response - High-Bandwidth Error Amplifiers - Full 0% to 100% Duty Ratios • Excellent Output Voltage Regulation - Core PWM Output: ±1% Over Temperature - AGP Bus PWM Output: ±3% Over Temperature - Other Outputs: ±3% Over Temperature • TTL-Compatible 5 Bit DAC Microprocessor Core Output Voltage Selection - Wide Range . . . . . . . . . . . . . . . . . . . 1.3VDC to 3.5VDC • Power-Good Output Voltage Monitor • Over-Voltage and Over-Current Fault Monitors - Switching Regulators Do Not Require Extra Current Sensing Elements, Use MOSFET’s rDS(ON) • Small Converter Size - Constant Frequency Operation - 200kHz Free-Running Oscillator; Programmable From 50kHz to Over 1MHz - Small External Component Count Applications • Motherboard Power Regulation for Computers Pinout HIP6020 (SOIC) TOP VIEW UGATE2 1 28 VCC PHASE2 2 27 UGATE1 VID4 3 26 PHASE1 VID3 4 25 LGATE1 VID2 5 24 PGND VID1 6 23 OCSET1 VID0 7 22 VSEN1 PGOOD 8 21 FB1 OCSET2 9 20 COMP1 VSEN2 10 19 VSEN3 SELECT 11 SS 12 FAULT/RT 13 VSEN4 14 1 FN4683 18 DRIVE3 17 GND 16 VAUX 15 DRIVE4 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved SELECT VSEN2 PHASE2 UGATE2 VSEN4 DRIVE4 VCC - + 1.5V or 3.3V x 0.75 x 0.75 - + - + OC2 FAULT / RT FAULT INHIBIT 28μA SS OV VCC SOFTSTART & FAULT LOGIC LUV OCSET2 200μA LINEAR UNDERVOLTAGE OSCILLATOR PWM COMP2 - + ERROR AMP2 - + INHIBIT PWM2 1.26V + GATE CONTROL DRIVE2 - + - - + - + DRIVE3 - 2 + VAUX VSEN3 4.5V DACOUT FB1 ERROR AMP1 x 1.15 x 0.90 x 1.10 - + - + - + + - VSEN1 COMP1 OC1 - PWM1 VID1 POWER-ON VCC SYNCH DRIVE GATE CONTROL DRIVE1 RESET (POR) VID4 VID3 VID2 TTL D/A CONVERTER (DAC) PWM COMP1 VID0 - + + 200μA OCSET1 VCC VCC GND PGND LGATE1 PHASE1 UGATE1 PGOOD VAUX HIP6020 Block Diagram HIP6020 Simplified Power System Diagram +5VIN Q1 Q3 PWM2 CONTROLLER VOUT2 VOUT1 PWM1 CONTROLLER Q2 +3.3VIN HIP6020 Q4 VOUT3 LINEAR CONTROLLER LINEAR CONTROLLER Q5 VOUT4 Typical Application +12VIN +5VIN LIN CIN VCC Q3 VOUT2 LOUT2 1.5V OR 3.3V OCSET2 OCSET1 UGATE2 PGOOD POWERGOOD PHASE2 UGATE1 Q1 LOUT1 PHASE1 COUT2 CR2 LGATE1 VSEN2 PGND SELECT TYPEDET VSEN1 VAUX +3.3VIN HIP6020 Q4 VOUT3 1.5V DRIVE3 FB1 COMP1 VSEN3 COUT3 FAULT / RT VID0 DRIVE4 Q5 VOUT4 1.8V VID1 VID2 VSEN4 VID3 SS COUT4 VID4 CSS GND 3 Q2 COUT1 VOUT1 1.3V TO 3.5V HIP6020 Absolute Maximum Ratings Thermal Information Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15V PGOOD, RT/FAULT, DRIVE, PHASE, and GATE Voltage . . . . . . . . . . . . . . . . . . GND - 0.3V to VCC + 0.3V Input, Output or I/O Voltage . . . . . . . . . . . . . . . . . . GND -0.3V to 7V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance (Typical, Note 1) θJA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only) Operating Conditions Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10% Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . 0oC to 70oC Junction Temperature Range . . . . . . . . . . . . . . . . . . 0oC to 125oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3 PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS UGATE1, LGATE1, UGATE2, DRIVE3, and DRIVE4 Open - 9 - mA Rising VCC Threshold VOCSET = 4.5V - - 10.4 V Falling VCC Threshold VOCSET = 4.5V 8.2 - - V Rising VAUX Threshold VOCSET = 4.5V - 2.5 - V VAUX Threshold Hysteresis VOCSET = 4.5V - 0.5 - V - 1.26 - V 200 215 kHz VCC SUPPLY CURRENT Nominal Supply Current ICC POWER-ON RESET Rising VOCSET1 Threshold OSCILLATOR Free Running Frequency FOSC RT = OPEN 185 6kΩ < RT to GND < 200kΩ -15 - +15 % ΔVOSC RT = Open - 1.9 - VP-P 0.8 V Total Variation Ramp Amplitude DAC AND STANDARD BUCK REGULATOR REFERENCE DAC(VID0-VID4) Input Low Voltage - - DAC(VID0-VID4) Input High Voltage 2.0 - DACOUT Voltage Accuracy V -1.0 - +1.0 % PWM2 Reference Voltage SELECT < 0.8V - 1.5 - V PWM2 Reference Voltage SELECT > 2.0V - 3.3 - V - 3 - % - 3 - % PWM2 Reference Voltage Tolerance 1.5V AND 1.8V LINEAR REGULATORS (VOUT3 AND VOUT4) Regulation VSEN3 Regulation Voltage VREG3 - 1.5 - V VSEN4 Regulation Voltage VREG4 - 1.8 - V - 75 - % VSEN3,4 Under-Voltage Level VSEN3UV VSEN3 Rising VSEN3,4 Under-Voltage Hysteresis VSEN3 Falling Output Drive Current VAUX-VDRIVE > 0.6V - 7 - % 20 40 - mA - 88 - dB - 15 - MHz - 6 - V/μs SYNCHRONOUS PWM CONTROLLER ERROR AMPLIFIER DC Gain Gain-Bandwidth Product GBWP Slew Rate SR 4 COMP1 = 10pF HIP6020 Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3 (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS PWM CONTROLLERS GATE DRIVERS UGATE1,2 Source IUGATE VCC = 12V, VUGATE1 (or VUGATE2) = 6V - 1 - A UGATE1,2 Sink RUGATE VGATE-PHASE = 1V - 1.7 3.5 Ω LGATE Source ILGATE VCC = 12V, VLGATE1 = 1V - 1 - A LGATE Sink RLGATE VLGATE = 1V - 1.4 3.0 Ω PROTECTION VSEN1 Over-Voltage (VSEN1/DACOUT) VSEN1 Rising - 115 120 % IOVP VFAULT/RT = 2.0V - 8.5 - mA IOCSET VOCSET = 4.5VDC 170 200 230 μA - 28 - μA FAULT Sourcing Current OCSET1,2 Current Source Soft-Start Current ISS POWER GOOD VSEN1 Upper Threshold (VSEN1/DACOUT) VSEN1 Rising 108 - 110 % VSEN1 Under-Voltage (VSEN1/DACOUT) VSEN1 Rising 92 - 94 % VSEN1 Hysteresis (VSEN1/DACOUT) Upper/Lower Threshold - 2 - % IPGOOD = -4mA - - 0.8 V PGOOD Voltage Low VPGOOD Typical Performance Curves 140 CUGATE1 = CUGATE2 = CLGATE1 = C 120 VCC = 12V 1000 RT PULLUP TO +12V 100 ICC (mA) RESISTANCE (kΩ) C = 4800pF VIN = 5V 100 80 C = 3600pF 60 C = 1500pF 40 10 RT PULLDOWN TO VSS 10 100 20 1000 0 100 C = 660pF 200 300 SWITCHING FREQUENCY (kHz) FIGURE 1. RT RESISTANCE vs FREQUENCY 400 500 600 700 800 900 1000 SWITCHING FREQUENCY (kHz) FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY Functional Pin Descriptions PGND (Pin 24) VCC (Pin 28) This is the power ground connection. Tie the synchronous PWM converter’s lower MOSFET source to this pin. Provide a 12V bias supply for the IC to this pin. This pin also provides the gate bias charge for all the MOSFETs controlled by the IC. The voltage at this pin is monitored for Power-On Reset (POR) purposes. GND (Pin 17) Signal ground for the IC. All voltage levels are measured with respect to this pin. 5 VAUX (Pin 16) The +3.3V input voltage at this pin is monitored for power-on reset (POR) purposes. Connected to +5V input, this pin provides boost current for the two linear regulator output drives in the event bipolar NPN transistors (instead of N-channel MOSFETs) are employed as pass elements. HIP6020 SS (Pin 12) UGATE1, UGATE2 (Pins 27 and 1) Connect a capacitor from this pin to ground. This capacitor, along with an internal 28μA current source, sets the soft-start interval of the converter. Connect UGATE pins to the respective PWM converter’s upper MOSFET gate. These pins provide the gate drive for the upper MOSFETs. FAULT / RT (Pin 13) LGATE1 (Pin 25) This pin provides oscillator switching frequency adjustment. By placing a resistor (RT) from this pin to GND, the nominal 200kHz switching frequency is increased according to the following equation: Connect LGATE1 to the synchronous PWM converter’s lower MOSFET gate. This pin provides the gate drive for the lower MOSFET. 6 5 × 10 Fs ≈ 200KHz + --------------------R T ( kΩ ) (RT to GND) Conversely, connecting a pull-up resistor (RT) from this pin to VCC reduces the switching frequency according to the following equation: 7 4 × 10 Fs ≈ 200KHz – --------------------R T ( kΩ ) (RT to 12V) Nominally, the voltage at this pin is 1.26V. In the event of an over-voltage or over-current condition, this pin is internally pulled to VCC. PGOOD (Pin 8) PGOOD is an open collector output used to indicate the status of the output voltages. This pin is pulled low when the synchronous regulator output is not within ±10% of the DACOUT reference voltage or when any of the other outputs are below their under-voltage thresholds. The PGOOD output is open for ‘11111’ VID code. VID0, VID1, VID2, VID3, VID4 (Pins 7, 6, 5, 4 and 3) VID0-4 are the TTL-compatible input pins to the 5-bit DAC. The logic states of these five pins program the internal voltage reference (DACOUT). The level of DACOUT sets the microprocessor core converter output voltage, as well as the coresponding PGOOD and OVP thresholds. OCSET1, OCSET2 (Pins 23 and 9) Connect a resistor (ROCSET) from this pin to the drain of the respective upper MOSFET. ROCSET, an internal 200μA current source (IOCSET), and the upper MOSFET’s onresistance (rDS(ON)) set the converter over-current (OC) trip point according to the following equation: COMP1 and FB1 (Pins 20, and 21) COMP1 and FB1 are the available external pins of the synchronous PWM regulator error amplifier. The FB1 pin is the inverting input of the error amplifier. Similarly, the COMP1 pin is the error amplifier output. These pins are used to compensate the voltage-mode control feedback loop of the synchronous PWM converter. VSEN1 (Pin 22) This pin is connected to the synchronous PWM converters’ output voltage. The PGOOD and OVP comparator circuits use this signal to report output voltage status and for overvoltage protection. VSEN2 (Pin 10) Connect this pin to the output of the standard buck PWM regulator. The voltage at this pin is regulated to the level predetermined by the logic-level status of the SELECT pin. This pin is also monitored by the PGOOD comparator circuit. SELECT (Pin 11) This pin determines the output voltage of the AGP bus switching regulator. A low TTL input sets the output voltage to 1.5V, while a high input sets the output voltage to 3.3V. DRIVE3 (Pin 18) Connect this pin to the gate of an external MOSFET. This pin provides the drive for the 1.5V regulator’s pass transistor. VSEN3 (Pin 19) Connect this pin to the output of the 1.5V linear regulator. This pin is monitored for undervoltage events. DRIVE4 (Pin 15) I OCSET × R OCSET I PEAK = ---------------------------------------------------r DS ( ON ) Connect this pin to the gate of an external MOSFET. This pin provides the drive for the 1.8V regulator’s pass transistor. An over-current trip cycles the soft-start function. VSEN4 (Pin 14) The voltage at OCSET1 pin is monitored for power-on reset (POR) purposes. Connect this pin to the output of the linear 1.8V regulator. This pin is monitored for undervoltage events. PHASE1, PHASE2 (Pins 26 and 2) Description Connect the PHASE pins to the respective PWM converter’s upper MOSFET source. These pins represent the gate drive return current path and are used to monitor the voltage drop across the upper MOSFETs for over-current protection. Operation 6 The HIP6020 monitors and precisely controls 4 output voltage levels (Refer to Figures 1, 2, and 3). It is designed for HIP6020 microprocessor computer applications with 3.3V, 5V, and 12V bias input from an ATX power supply. The IC has 2 PWM and two linear controllers. The first PWM controller (PWM1) is designed to regulate the microprocessor core voltage (VOUT1). PWM1 controller drives 2 MOSFETs (Q1 and Q2) in a synchronous-rectified buck converter and regulates the core voltage to a level programmed by the 5-bit digital-to-analog converter (DAC). The second PWM controller (PWM2) is designed to regulate the advanced graphics port (AGP) bus voltage (VOUT2). PWM2 controller drives a MOSFET (Q3) in a standard buck converter and regulates the output voltage to a digitally-programmable level of 1.5V or 3.3V. Selection of either output voltage is achieved by applying the proper logic level at the SELECT pin. The two linear controllers supply the 1.5V GTL bus power (VOUT3) and the 1.8V memory power (VOUT4). error amplifier reference ramps to the final value and the converter regulates the output a voltage proportional to the SS pin voltage. At T3 the input clamp voltage exceeds the reference voltage and the output voltage is in regulation. PGOOD 0V SOFT-START (1V/DIV) 0V VOUT2 ( = 3.3V) Initialization The HIP6020 automatically initializes upon receipt of input power. Special sequencing of the input supplies is not necessary. The Power-On Reset (POR) function continually monitors the input supply voltages. The POR monitors the bias voltage (+12VIN) at the VCC pin, the 5V input voltage (+5VIN) on the OCSET1 pin, and the 3.3V input voltage (+3.3VIN) at the VAUX pin. The normal level on OCSET1 is equal to +5VIN less a fixed voltage drop (see over-current protection). The POR function initiates soft-start operation after all supply voltages exceed their POR thresholds. VOUT1 (DAC = 2.5V) VOUT4 ( = 1.8V) OUTPUT VOLTAGES (0.5V/DIV) 0V T0 T1 Soft-Start The POR function initiates the soft-start sequence. Initially, the voltage on the SS pin rapidly increases to approximately 1V (this minimizes the soft-start interval). Then an internal 28μA current source charges an external capacitor (CSS) on the SS pin to 4.5V. The PWM error amplifiers reference inputs (+ terminal) and outputs (COMP1 pin) are clamped to a level proportional to the SS pin voltage. As the SS pin voltage slews from 1V to 4V, the output clamp allows generation of PHASE pulses of increasing width that charge the output capacitor(s). After the output voltage increases to approximately 70% of the set value, the reference input clamp slows the output voltage rate-of-rise and provides a smooth transition to the final set voltage. Additionally both linear regulators’ reference inputs are clamped to a voltage proportional to the SS pin voltage. This method provides a rapid and controlled output voltage rise. Figure 6 shows the soft-start sequence for the typical application. At T0 the SS voltage rapidly increases to approximately 1V. At T1, the SS pin and error amplifier output voltage reach the valley of the oscillator’s triangle wave. The oscillator’s triangular wave form is compared to the clamped error amplifier output voltage. As the SS pin voltage increases, the pulse-width on the PHASE pin increases. The interval of increasing pulse-width continues until each PWM output reaches sufficient voltage to transfer control to the error amplifier input reference clamp. If we consider the 3.3V output (VOUT2) in Figure 6, this time occurs at T2. During the interval between T2 and T3, the 7 VOUT3 ( = 1.5V) T2 TIME T3 T4 FIGURE 3. SOFT-START INTERVAL The remaining outputs are also programmed to follow the SS pin voltage. The PGOOD signal toggles ‘high’ when all output voltage levels have exceeded their under-voltage levels. See the Soft-Start Interval section under Applications Guidelines for a procedure to determine the soft-start interval. Fault Protection All four outputs are monitored and protected against extreme overload. A sustained overload on any output or an overvoltage on VOUT1 output (VSEN1) disables all outputs and drives the FAULT/RT pin to VCC. HIP6020 S Q OC2 R 0.15V SS + + 4V COUNTER - - R FAULT LATCH VCC S Q UP R POR FAULT OV FIGURE 4. FAULT LOGIC - SIMPLIFIED SCHEMATIC Figure 7 shows a simplified schematic of the fault logic. An over-voltage detected on VSEN1 immediately sets the fault latch. A sequence of three over-current fault signals also sets the fault latch. The over-current latch is set dependent upon the states of the over-current (OC1 and OC2), linear under-voltage (LUV) and the soft-start signals. A window comparator monitors the SS pin and indicates when CSS is fully charged to 4.5V (UP signal). An under-voltage on either linear output (VSEN3 and VSEN4) is ignored until after the soft-start interval (T4 in Figure 6). This allows VOUT3 and VOUT4 to increase without fault at start-up. Cycling the bias input voltage (+12VIN on the VCC pin off then on) resets the counter and the fault latch. Over-Voltage Protection During operation, a short across the synchronous PWM upper MOSFET (Q1) causes VOUT1 to increase. When the output exceeds the over-voltage threshold of 115% of DACOUT, the over-voltage comparator trips to set the fault latch and turns the lower MOSFET (Q2) on. This blows the input fuse and reduces VOUT1. The fault latch raises the FAULT/RT pin to VCC. A separate over-voltage circuit provides protection during the initial application of power. For voltages on the VCC pin below the power-on reset (and above ~4V), the output level is monitored for voltages above 1.3V. Should VSEN1 exceed this level, the lower MOSFET, Q2 is driven on. Over-Current Protection All outputs are protected against excessive over-currents. Both PWM controllers use the upper MOSFET’s onresistance, rDS(ON) to monitor the current for protection against shorted outputs. Both linear regulators monitor their respective VSEN pins for under-voltage to protect against excessive currents. Figure 8 illustrates the over-current protection with an overload on OUT2. The overload is applied at T0 and the current increases through the inductor (LOUT2). At time T1, the OVER-CURRENT2 comparator trips when the voltage across Q3 (iD • rDS(ON)) exceeds the level programmed by 8 The PWM1 controller operates in the same way as PWM2 to over-current faults. Additionally, the two linear controllers monitor the VSEN pins for an under-voltage. Should excessive currents cause VSEN3 or VSEN4 to fall below the linear under-voltage threshold, the LUV signal sets the overcurrent latch, providing CSS is fully charged. Blanking the LUV signal during the CSS charge interval allows the linear outputs to build above the under-voltage threshold during normal operation. Cycling the bias input power off then on resets the counter and the fault latch. FAULT/RT OC1 INHIBIT FAULT REPORTED 10V 0V COUNT =1 SOFT-START OVERCURRENT LATCH ROCSET . This inhibits all outputs, discharges the soft-start capacitor (CSS) with a 28μA current sink, and increments the counter. CSS recharges at T2 and initiates a soft-start cycle with the error amplifiers clamped by soft-start. With OUT2 still overloaded, the inductor current increases to trip the overcurrent comparator. Again, this inhibits all outputs, but the soft-start voltage continues increasing to 4.5V before discharging. The counter increments to 2. The soft-start cycle repeats at T3 and trips the over-current comparator. The SS pin voltage increases to 4.5V at T4 and the counter increments to 3. This sets the fault latch to disable the converter. The fault is reported on the FAULT/RT pin. INDUCTOR CURRENT LUV COUNT =2 COUNT =3 4V 2V 0V OVERLOAD APPLIED 0A T0 T1 T2 TIME T3 T4 FIGURE 5. OVER-CURRENT OPERATION HIP6020 OVER-CURRENT TRIP: V >V DS SET i ×r D DS ( ON ) > I OCSET × R OCSET VIN = +5V ROCSET OCSET IOCSET 200μA OVERCURRENT OC VSET + iD VCC DRIVE UGATE + + VDS PHASE - V PWM = V –V PHASE IN DS V = V –V OCSET IN SET GATE CONTROL FIGURE 6. OVER-CURRENT DETECTION Resistors (ROCSET1 and ROCSET2) program the over-current trip levels for each PWM converter. As shown in Figure 9, the internal 200μA current sink (IOCSET) develops a voltage across ROCSET (VSET) that is referenced to VIN . The DRIVE signal enables the over-current comparator (OVER-CURRENT1 or OVER-CURRENT2). When the voltage across the upper MOSFET (VDS(ON)) exceeds VSET , the over-current comparator trips to set the over-current latch. Both VSET and VDS are referenced to VIN and a small capacitor across ROCSET helps VOCSET track the variations of VIN due to MOSFET switching. The over-current function will trip at a peak inductor current (IPEAK) determined by: I OCSET × R OCSET I PEAK = ---------------------------------------------------r DS ( ON ) The OC trip point varies with MOSFET’s rDS(ON) temperature variations. To avoid over-current tripping in the normal operating load range, determine the ROCSET resistor value from the equation above with: 1. The maximum rDS(ON) at the highest junction temperature 2. The minimum IOCSET from the specification table 3. Determine IPEAK for IPEAK > IOUT(MAX) + (ΔI) / 2, where ΔI is the output inductor ripple current. For an equation for the ripple current see the section under component guidelines titled ‘Output Inductor Selection’. OUT1 Voltage Program The output voltage of the PWM1 converter is programmed to discrete levels between 1.3VDC and 3.5VDC . This output (OUT1) is designed to supply the core voltage of Intel’s advanced microprocessors. The voltage identification (VID) pins program an internal voltage reference (DACOUT) with a TTL-compatible 5-bit digital-to-analog converter (DAC). The level of DACOUT also sets the PGOOD and OVP thresholds. Table 1 specifies the DACOUT voltage for the different combinations of connections on the VID pins. The VID pins can be left open for a logic 1 input, because they are internally pulled up to an internal voltage of about 5V by a 10μA current 9 source. Changing the VID inputs during operation is not recommended and could toggle the PGOOD signal and exercise the over-voltage protection. ‘11111’ VID pin combination disables the IC and opens the PGOOD pin. OUT2 Voltage Selection The AGP regulator output voltage is internally set to one of two discrete levels, based on the status of the SELECT pin. SELECT pin is internally pulled ‘high’, such that left open, the AGP output voltage is by default set to 3.3V. The other discrete setting available is 1.5V, which can be obtained by grounding the SELECT pin using a jumper or another suitable method capable of sinking a few tens of microamperes. The status of the SELECT pin cannot be changed during operation of the IC without immediately causing a fault condition. HIP6020 TABLE 1. OUT1 VOLTAGE PROGRAM PIN NAME occurs during the initial output voltage rise to 70% of the set value. Using the recommended 0.1μF soft start capacitor insures all output voltages ramp up to their set values within 10ms of the input voltages reaching POR levels. VID4 VID3 VID2 VID1 VID0 NOMINAL DACOUT VOLTAGE 0 1 1 1 1 1.30 Shutdown 0 1 1 1 0 1.35 0 1 1 0 1 1.40 0 1 1 0 0 1.45 0 1 0 1 1 1.50 0 1 0 1 0 1.55 Neither PWM output switches until the soft-start voltage (VSS) exceeds the oscillator’s valley voltage. Additionally, the reference on each linear’s amplifier is clamped to the soft-start voltage. Holding the SS pin low (with an open drain or open collector signal) turns off all four regulators. 0 1 0 0 1 1.60 The ‘11111’ VID code, also shuts down the IC. 0 1 0 0 0 1.65 0 0 1 1 1 1.70 Layout Considerations 0 0 1 1 0 1.75 0 0 1 0 1 1.80 0 0 1 0 0 1.85 0 0 0 1 1 1.90 0 0 0 1 0 1.95 0 0 0 0 1 2.00 0 0 0 0 0 2.05 1 1 1 1 1 0 1 1 1 1 0 2.1 1 1 1 0 1 2.2 1 1 1 0 0 2.3 1 1 0 1 1 2.4 1 1 0 1 0 2.5 1 1 0 0 1 2.6 1 1 0 0 0 2.7 1 0 1 1 1 2.8 1 0 1 1 0 2.9 1 0 1 0 1 3.0 1 0 1 0 0 3.1 1 0 0 1 1 3.2 1 0 0 1 0 3.3 1 0 0 0 1 3.4 1 0 0 0 0 3.5 NOTE: 0 = connected to GND, 1 = open or connected to 5V through pull-up resistors Application Guidelines Soft-Start Interval Initially, the soft-start function clamps the error amplifier’s output of the PWM converters. This generates PHASE pulses of increasing width that charge the output capacitor(s). After the output voltage increases to approximately 70% of the set value, the reference input of the error amplifier is clamped to a voltage proportional to the SS pin voltage. The resulting output voltages start-up as shown in Figure 6. The soft-start function controls the output voltage rate of rise to limit the current surge at start-up. The soft-start interval and the surge current are programmed by the soft-start capacitor, CSS. Programming a faster soft-start interval increases the peak surge current. The peak surge current 10 MOSFETs switch very fast and efficiently. The speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. The voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device over-voltage stress. Careful component layout and printed circuit design minimizes the voltage spikes in the converter. Consider, as an example, the turnoff transition of the upper MOSFET. Prior to turn-off, the upper MOSFET was carrying the full load current. During the turn-off, current stops flowing in the upper MOSFET and is picked up by the lower MOSFET or Schottky diode. Any inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selection, tight layout of the critical components, and short, wide circuit traces minimize the magnitude of voltage spikes. There are two sets of critical components in a DC-DC converter using a HIP6020 controller. The switching power components are the most critical because they switch large amounts of energy, and as such, they tend to generate equally large amounts of noise. The critical small signal components are those connected to sensitive nodes or those supplying critical bypass current. The power components and the controller IC should be placed first. Locate the input capacitors, especially the highfrequency ceramic de-coupling capacitors, close to the power switches. Locate the output inductor and output capacitors between the MOSFETs and the load. Locate the PWM controller close to the MOSFETs. The critical small signal components include the bypass capacitor for VCC and the soft-start capacitor, CSS. Locate these components close to their connecting pins on the control IC. Minimize any leakage current paths from SS node, since the internal current source is only 28μA. A multi-layer printed circuit board is recommended. Figure 10 shows the connections of the critical components in the converter. Note that the capacitors CIN and COUT each could represent numerous physical capacitors. Dedicate one solid layer for a ground plane and make all critical component ground connections with vias to this layer. Dedicate another solid layer as a power plane and break this HIP6020 plane into smaller islands of common voltage levels. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the PHASE nodes, but do not unnecessarily oversize these particular islands. Since the PHASE nodes are subjected to very high dV/dt voltages, the stray capacitor formed between these islands and the surrounding circuitry will tend to couple switching noise. Use the remaining printed circuit layers for small signal wiring. The wiring traces from the control IC to the MOSFET gate and source should be sized to carry 2A peak currents. +5VIN +12V COCSET2 PWM COMP Δ VOSC Q3 - LOUT2 VE/A VOUT CO ESR (PARASITIC) ZIN - + ROCSET1 REFERENCE C1 LOUT1 VOUT1 LGATE1 LOAD SS ZFB VOUT ZIN C3 R2 R3 Q1 COUT1 VOUT3 PHASE ZFB C2 PHASE1 COUT2 CR2 CSS DRIVER + COCSET1 UGATE2 UGATE1 PHASE2 VOUT2 LO DETAILED COMPENSATION COMPONENTS CVCC VCC GND OCSET2 OCSET1 ROCSET2 LOAD DRIVER ERROR AMP LIN CIN CR1 Q2 R1 COMP FB + HIP6020 HIP6020 DACOUT VOUT4 COUT3 DRIVE3 DRIVE4 PGND Q4 COUT4 Q5 LOAD LOAD VIN OSC +3.3VIN KEY ISLAND ON POWER PLANE LAYER ISLAND ON CIRCUIT PLANE LAYER VIA CONNECTION TO GROUND PLANE FIGURE 7. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS PWM1 Controller Feedback Compensation Both PWM controllers use voltage-mode control for output regulation. This section highlights the design consideration for a voltage-mode controller requiring external compensation. Apply these methods and considerations only to the synchronous PWM controller. The considerations for the standard PWM controller are presented separately. Figure 11 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (VOUT) is regulated to the Reference voltage level. The reference voltage level is the DAC output voltage (DACOUT) for PWM1. The error amplifier output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (LO and CO). The modulator transfer function is the small-signal transfer function of VOUT /VE/A. This function is dominated by a DC 11 FIGURE 8. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN Gain, given by VIN /VOSC , and shaped by the output filter, with a double pole break frequency at FLC and a zero at FESR . Modulator Break Frequency Equations 1 F LC = ---------------------------------------2π × L O × C O 1 F ESR = ----------------------------------------2π × ESR × CO The compensation network consists of the error amplifier (internal to the HIP6020) and the impedance networks ZIN and ZFB . The goal of the compensation network is to provide a closed loop transfer function with high 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180 degrees. The equations below relate the compensation network’s poles, zeros and gain to the components (R1, R2, R3, C1, C2, and C3) in Figure 11. Use these guidelines for locating the poles and zeros of the compensation network: 1. Pick Gain (R2/R1) for desired converter bandwidth 2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC) 3. Place 2ND Zero at Filter’s Double Pole 4. Place 1ST Pole at the ESR Zero 5. Place 2ND Pole at Half the Switching Frequency 6. Check Gain against Error Amplifier’s Open-Loop Gain 7. Estimate Phase Margin - Repeat if Necessary HIP6020 Compensation Break Frequency Equations 1 F Z1 = ----------------------------------2π × R 2 × C1 1 F P1 = ------------------------------------------------------C1 × C2 2π × R 2 × ⎛ ----------------------⎞ ⎝ C1 + C2⎠ 1 F Z2 = ------------------------------------------------------2π × ( R1 + R3 ) × C3 1 F P2 = ----------------------------------2π × R 3 × C3 Figure 12 shows an asymptotic plot of the DC-DC converter’s gain vs. frequency. The actual Modulator Gain has a high gain peak dependent on the quality factor (Q) of the output filter, which is not shown in Figure 12. Using the above guidelines should yield a Compensation Gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The Closed Loop Gain is constructed on the log-log graph of Figure 12 by adding the Modulator Gain (in dB) to the Compensation Gain (in dB). This is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. FZ1 100 FZ2 FP1 FP2 OPEN LOOP ERROR AMP GAIN ⎛ V IN ⎞ 20 log ⎜ ------------------⎟ ⎝ V P – P⎠ 80 GAIN (dB) 60 COMPENSATION GAIN 40 20 0 -20 -40 -60 R2 20 log ⎛ --------⎞ ⎝ R1⎠ MODULATOR GAIN 10 100 FLC 1K CLOSED LOOP GAIN FESR 10K 100K 1M 10M FREQUENCY (Hz) FIGURE 9. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45 degrees. Include worst case component variations when determining phase margin. PWM2 Controller Feedback Compensation To reduce the number of external small-signal components required by a typical application, the standard PWM controller is internally stabilized. The only stability criteria that needs to be met relates the minimum value of the output inductor to the equivalent ESR of the output capacitor bank, as shown in the following equation: 1.75 ESR OUT × 10 L OUT ( MIN ) = -----------------------------------------------2 × π × BW 12 where LOUT(MIN) - minimum output inductor value at full output current ESROUT - equivalent ESR of the output capacitor bank BW - desired converter bandwidth (not to exceed 0.25 to 0.30 of the switching frequency) The design procedure for this output should follow the following steps: 1. Choose number and type of output capacitors to meet the output transient requirements based on the dynamic loading characteristics of the output. 2. Determine the equivalent ESR of the output capacitor bank and calculate minimum output inductor value. 3. Verify that chosen inductor meets this minimum value criteria (at full output load). It is recommended the chosen output inductor be no more than 30% saturated at full output load. Oscillator Synchronization The PWM controllers use a triangle wave for comparison with the error amplifier output to provide a pulse-width modulated signal. Should the output voltage of the two converters be programmed close to each other, then crosstalk between the converters could cause non-uniform PHASE pulse-widths and increased output voltage ripple. The HIP6020 avoids this problem by synchronizing the two converters 180 degrees out of phase for output voltage settings within the same range. Therefore, for both output voltage settings less than 2.4V or both output voltage settings greater or equal to 2.4V, PWM1 operates out of phase with PWM2. For one PWM output voltage setting below 2.4V and the other PWM output voltage setting of 2.4V and above, PWM1 operates in phase with PWM2. Component Selection Guidelines Output Capacitor Selection The output capacitors for each output have unique requirements. In general the output capacitors should be selected to meet the dynamic regulation requirements. Additionally, the PWM converters require an output capacitor to filter the current ripple. The load transient for the microprocessor core requires high quality capacitors to supply the high slew rate (di/dt) current demands. PWM Output Capacitors Modern microprocessors produce transient load rates above 1A/ns. High frequency capacitors initially supply the transient current and slow the load rate-of-change seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. HIP6020 High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor’s ESR determines the output ripple voltage and the initial voltage drop following a high slew-rate transient’s edge. An aluminum electrolytic capacitor’s ESR value is related to the case size with lower ESR available in larger case sizes. However, the equivalent series inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor’s impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. Linear Output Capacitors The output capacitors for the linear regulators provide dynamic load current. Thus capacitors COUT3 and COUT4 should be selected for transient load regulation. PWM Output Inductor Selection Each PWM converter requires an output inductor. The output inductor is selected to meet the output voltage ripple requirements and sets the converter’s response time to a load transient. Additionally, PWM2 output inductor has to meet the minimum value criteria for loop stability as described in paragraph ‘PWM2 Controller Feedback Compensation’. The inductor value determines the converter’s ripple current and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by the following equations: V IN – V OUT V OUT ΔI = -------------------------------- × ---------------FS × L V IN ΔV OUT = ΔI × ESR Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values increase the converter’s response time to a load transient. One of the parameters limiting the converter’s response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the HIP6020 will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time interval required to slew the inductor current from an initial current value to the post-transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor(s). Minimizing the response time can minimize the output capacitance required. 13 The response time to a transient is different for the application of load and the removal of load. The following equations give the approximate response time interval for application and removal of a transient load: L O × I TRAN t RISE = -------------------------------V IN – V OUT L O × I TRAN t FALL = ------------------------------V OUT where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. Input Capacitor Selection The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select bulk input capacitors with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage. The RMS current rating requirement for the input capacitors of a buck regulator is approximately 1/2 of the summation of the DC output load current. Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use ceramic capacitance for the high frequency decoupling and bulk capacitors to supply the RMS current. Small ceramic capacitors can be placed very close to the upper MOSFET to suppress the voltage induced in the parasitic circuit impedances. For a through-hole design, several electrolytic capacitors (Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX or equivalent) may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge current at power-up. The TPS series available from AVX, and the 593D series from Sprague are both surge current tested. MOSFET Selection/Considerations The HIP6020 requires 5 external transistors. Three N-channel MOSFETs are employed by the PWM converters. The GTL and memory linear controllers can each drive a MOSFET or a NPN bipolar as a pass transistor. All these transistors should be selected based upon rDS(ON) , current gain, saturation voltages, gate supply requirements, and thermal management considerations. PWM1 MOSFET Selection and Considerations In high-current PWM applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components; conduction loss and switching loss. These losses are distributed between the upper and lower MOSFETs according to the duty factor. The conduction losses are the HIP6020 main component of power dissipation for the lower MOSFETs. Only the upper MOSFET has significant switching losses, since the lower device turns on and off into near zero voltage. The equations presented assume linear voltage-current transitions and do not model power loss due to the reverse recovery of the lower MOSFET’s body diode. The gate charge losses are dissipated by the HIP6020 and don't heat the MOSFETs. However, large gate-charge increases the switching time, tSW , which increases the upper MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow. 2 I O × r DS ( ON ) × V OUT I O × V IN × t SW × F S P UPPER = ------------------------------------------------------------ + ---------------------------------------------------V IN 2 2 I O × r DS ( ON ) × ( V IN – V OUT ) P LOWER = --------------------------------------------------------------------------------V IN The rDS(ON) is different for the two equations above even if the same device is used for both. This is because the gate drive applied to the upper MOSFET is different than the lower MOSFET. Figure 13 shows the gate drive where the upper MOSFET’s gate-to-source voltage is approximately VCC less the input supply. For +5V main power and +12VDC for the bias, the gate-to-source voltage of Q1 is 7V. The lower gate drive voltage is +12VDC. A logic-level MOSFET is a good choice for Q1 and a logic-level MOSFET can be used for Q2 if its absolute gate-to-source voltage rating exceeds the maximum voltage applied to VCC . +5V OR LESS +12V VCC HIP6020 Q1 UGATE PHASE - + NOTE: VGS ≈ VCC -5V LGATE Q2 PGND CR1 NOTE: VGS ≈ VCC GND FIGURE 10. UPPER GATE DRIVE - DIRECT VCC DRIVE Rectifier CR1 is a clamp that catches the negative inductor swing during the dead time between the turn off of the lower MOSFET and the turn on of the upper MOSFET. The diode must be a Schottky type to prevent the lossy parasitic MOSFET body diode from conducting. It is acceptable to omit the diode and let the body diode of the lower MOSFET clamp the negative inductor swing, but efficiency could drop, in some 14 cases, one or two percent as a result. The diode's rated reverse breakdown voltage must be greater than the maximum input voltage. PWM2 MOSFET and Schottky Selection The power dissipation in PWM2 converter is similar to PWM1 except that the power losses of the lower device is in a Schottky and not a MOSFET. The power losses of PWM2 converter are distributed between the upper MOSFET and the Schottky. The equations below describe an approximation of this distribution and assume a linear voltage-current switching transitions. 2 I O × r DS ( ON ) × V OUT I O × V IN × t SW × F S P MOS = ------------------------------------------------------------ + ---------------------------------------------------V IN 2 I O × V f × ( V IN – V OUT ) P SCH = ------------------------------------------------------------V IN Linear Controllers Transistor Selection The HIP6020 linear controllers are compatible with both NPN bipolar as well as N-Channel MOSFET transistors. The main criteria for selection of pass transistors for the linear regulators is package selection for efficient removal of heat. The power dissipated in a linear regulator is P LINEAR = I O × ( V IN – V OUT ) Select a package and heatsink that maintains the junction temperature below the maximum desired temperature with the maximum expected ambient temperature. When selecting bipolar NPN transistors for use with the linear controllers, insure the current gain at the given operating VCE is sufficiently large to provide the desired output load current when the base is fed with the minimum driver output current. HIP6020 HIP6020 DC-DC Converter Application Circuit Figure 14 shows an application circuit of a power supply for a microprocessor computer system. The power supply provides the microprocessor core voltage (VOUT1), the AGP bus voltage (VOUT2), the GTL bus voltage (VOUT3), and the memory voltage (VOUT4) from +3.3V, +5VDC, and +12VDC. For detailed information on the circuit, including a Bill-of-Materials and circuit board description, see Application Note AN9836. Also see Intersil’s web page (http://www.intersil.com). +12VIN L1 +5VIN 1μH + GND C1-7 7x1000μF C8 1μF C11 1000pF C9 1000pF C10 1μF VCC 28 R2 2.7K OCSET2 Q3 HUF76107D3S VOUT2 UGATE2 L2 (3.3V/1.5V) PHASE2 6.2μH + C12-14 3x1000μF CR1 MBRD835L VSEN2 SELECT TYPEDET VAUX +3.3VIN 8 26 2 DRIVE3 VSEN3 VOUT3 (1.5V) + VOUT4 Q5 HUF76107D3S (1.8V) DRIVE4 VSEN4 + C28,29 2x1000μF SD POWERGOOD PGOOD Q1,2 HUF76143S3S L3 PHASE1 25 VOUT1 (1.3V-3.5V) C15-22 + 8x1000μF LGATE1 24 PGND 11 22 U1 18 21 20 R3 10.2K VSEN1 FB1 COMP1 R4 1.62K C24 10pF C23 0.22μF 19 C26,27 2x1000μF FAULT/RT 1.0K 4.2μH 10 16 OCSET1 27 UGATE1 1 HIP6020 Q4 HUF76107D3S R1 23 VID0 13 7 15 6 VID1 VID2 5 4 VID3 14 3 C25 2.7nF R5 150K R6 499K VID4 12 SS 9 17 C30 0.1μF GND FIGURE 11. POWER SUPPLY APPLICATION CIRCUIT FOR A MICROPROCESSOR COMPUTER SYSTEM All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 15