INTERSIL ISL8012IRZ

ISL8012
®
Data Sheet
March 11, 2008
2A Low Quiescent Current 1MHz High
Efficiency Synchronous Buck Regulator
The ISL8012 is a high efficiency, monolithic, synchronous
step-down DC/DC converter that can deliver up to 2A
continuous output current from a 2.7V to 5.5V input supply. It
uses a current control architecture to deliver very low duty
cycle operation at high frequency with fast transient
response and excellent loop stability.
The ISL8012 integrates a pair of low ON-resistance
P-Channel and N-Channel internal MOSFETs to maximize
efficiency and minimize external component count. The
100% duty-cycle operation allows less than 240mV dropout
voltage at 2A output current. High 1MHz pulse-width
modulation (PWM) switching frequency allows the use of
small external components.
The ISL8012 can be configured for discontinuous or forced
continuous operation at light load. Forced continuous
operation reduces noise and RF interference while
discontinuous mode provides high efficiency by reducing
switching losses at light loads.
Fault protection is provided by internal current limiting during
short circuit and overcurrent conditions, an output over
voltage comparator and over-temperature monitor circuit. A
power good output voltage monitor indicates when the
output is in regulation.
Features
• High Efficiency Synchronous Buck Regulator with up to
95% Efficiency
• Power-Good (PG) Output with a 1ms Delay
• 2.7V to 5.5V Supply Voltage
• 3% Output Accuracy Over-Temperature/Load/Line
• 2A Guaranteed Output Current
• Start-up with Pre-Biased Output
• Internal Soft-Start - 1ms
• Soft-Stop Output Discharge During Disabled
• 40µA Quiescent Supply Current in PFM Mode
• Selectable Forced PWM Mode and PFM Mode
• Less than 1µA Logic Controlled Shutdown Current
• 100% Maximum Duty Cycle
• Internal Current Mode Compensation
• Peak Current Limiting and Hiccup Mode Short Circuit
Protection
• Over-Temperature Protection
• Small 10 Ld 3mmx3mm DFN
• Pb-Free (RoHS Compliant)
The ISL8012 offers a 1ms Power Good (PG) timer at
power-up. When shutdown, ISL8012 discharges the output
capacitor. Other features include internal soft-start, internal
compensation, overcurrent protection, and thermal
shutdown.
Applications
The ISL8012 is offered in a space saving 3mmx3mm 10 Ld
DFN package lead free package with exposed pad lead
frames for low thermal. The complete converter occupies
less than 0.35in2 area.
• Portable Instruments
Ordering Information
• Small Form Factor (SFP) Modules
PART
NUMBER
(Note)
ISL8012IRZ*
TEMP.
RANGE
PART
(°C)
MARKING
012Z
• DC/DC POL Modules
• µC/µP, FPGA and DSP Power
• Plug-in DC/DC Modules for Routers and Switchers
• Test and Measurement Systems
• Li-ion Battery Powered Devices
• Bar Code Readers
PACKAGE
(Pb-free)
PKG.
DWG. #
Pinout
ISL8012
(10 LD DFN)
TOP VIEW
-40 to +85 10 Ld 3x3 DFN L10.3x3C
*Add “-T” suffix for tape and reel. Please refer to TB347 for details
on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
1
FN6616.0
VIN
1
10 LX
VCC
2
9
PGND
EN 3
8
SGND
4
7
VFB
MODE 5
6
RSI
PG
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL8012
Typical Application
OUTPUT
L
INPUT 2.7V TO 5.5V
1.8V/2A
LX
VIN
C2
22µF
C1
22µF
R2
124k
PGND
C3*
220pF
ISL8012
EN
SGND
R3
100k
R1
100k
PG
VFB
MODE
RSI
*C3 is optional
FIGURE 1. TYPICAL APPLICATION DIAGRAM
2
FN6616.0
March 11, 2008
ISL8012
Block Diagram
MODE
390k
SHUTDOWN
0.8V
BANDGAP
VIN
OSCILLATOR
+
EN
SHUTDOWN
27pF
SOFT-START
+
COMP
EAMP
PWM/PFM
LOGIC
CONTROLLER
PROTECTION
DRIVER
LX
+
GND
VFB
SLOPE
COMP
+
CSA
0.864V
+
+
OCP
1V
+
0.736V
+
SKIP
PG
1ms
DELAY
0.25V
ZERO-CROSS
SENSING
RSI
SCP
0.2V
+
FIGURE 2. FUNCTIONAL BLOCK DIAGRAM
3
FN6616.0
March 11, 2008
ISL8012
Absolute Maximum Ratings (Reference to GND)
Thermal Information
VIN, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V
EN, RSI, PG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN+0.3V
LX. . . . . . . . . . . . . . . . . . . . . . . . . .-1.5V (100ns)/-0.3V (DC) to 6.5V
VFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
Thermal Resistance (Typical, Notes 1, 2) θJA (°C/W) θJC (°C/W)
10 Ld 3x3 DFN Package . . . . . . . . .
49
5.5
Junction Temperature Range. . . . . . . . . . . . . . . . . .-55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
VIN Supply Voltage Range. . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 2A
Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. θJC, “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
3. Limits established by characterization and are not production tested.
4. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested.
Electrical Specifications
Unless otherwise noted, all parameter limits are established over the recommended operating conditions and
the typical specifications are measured at the following conditions: TA = -40°C to +85°C, VIN = 3.6V, EN = VCC,
unless otherwise noted. Typical values are at TA = +25°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 4)
TYP
MAX
(Note 4)
UNITS
2.5
2.7
V
INPUT SUPPLY
VIN Under Voltage Lockout Threshold
VUVLO
Rising
Falling
Quiescent Supply Current
IVIN
Shut Down Supply Current
ISD
2.2
2.4
V
MODE = VIN, no load at the output
40
MODE = VIN, no load at the output and no
switches switching; design info only
15
MODE = SGND, no load at the output
6
8
mA
0.1
2
µA
0.8
0.816
V
VIN = 5.5V, EN = low
60
µA
µA
OUTPUT REGULATION
VFB Regulation Voltage
VVFB
TA = 0°C to +85°C
VFB Bias Current
IVFB
VFB = 0.75V
0.784
0.1
-3
µA
Output Voltage Accuracy
VIN = VO + 0.5V to 5.5V, IO = 0A to 2A
(Note 3)
3
%
Line Regulation
VIN = VO + 0.5V to 5.5V (minimal 2.7V),
IOUT = 400mA
0.2
%/V
Adjustable version, design info only
20
µA/V
COMPENSATION
Error Amplifier Trans-Conductance
LX
P-Channel MOSFET ON-Resistance
N-Channel MOSFET ON-Resistance
VIN = 5.5V, IO = 200mA
0.12
0.22
Ω
VIN = 2.7V, IO = 200mA
0.21
0.27
Ω
VIN = 5.5V, IO = 200mA
0.11
0.22
Ω
0.13
0.27
Ω
3.00
3.50
A
VIN = 2.7V, IO = 200mA
P-Channel MOSFET Peak Current Limit
2.65
IPK
LX Maximum Duty Cycle
%
100
PWM Switching Frequency
fS
4
TA = 0°C to +85°C
0.840
1
1.16
MHz
FN6616.0
March 11, 2008
ISL8012
Electrical Specifications
Unless otherwise noted, all parameter limits are established over the recommended operating conditions and
the typical specifications are measured at the following conditions: TA = -40°C to +85°C, VIN = 3.6V, EN = VCC,
unless otherwise noted. Typical values are at TA = +25°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 4)
TYP
MAX
(Note 4)
UNITS
100
ns
LX Minimum On-Time
MODE = low (forced PWM mode)
80
Soft-Start-Up Time
VIN = 3.6V
1.1
ms
PG
Output Low Voltage
Sinking 1mA, VFB = 0.7V
0.3
Delay Time
1
PG Pin Leakage Current
PG = VIN = 3.6V
Minimum Supply Voltage for Valid PG Signal
0.01
V
ms
0.1
1.2
µA
V
Internal PGOOD Low Rising Threshold
Percentage of nominal regulation voltage
89
92
95
%
Internal PGOOD Low Falling Threshold
Percentage of nominal regulation voltage
85
88
91
%
Internal PGOOD High Rising Threshold
Percentage of nominal regulation voltage
107
110
113
%
Internal PGOOD High Falling Threshold
Percentage of nominal regulation voltage
104
107
110
%
Internal PGOOD Delay Time
30
µs
EN, MODE, RSI
Logic Input Low
0.4
Logic Input High
1.4
Logic Input Leakage Current
Pulled up to 5.5V
5
V
V
0.1
1
µA
FN6616.0
March 11, 2008
ISL8012
Pin Descriptions
VFB (Pin 7)
Input supply voltage. Connect a 10µF ceramic capacitor to
power ground.
Buck regulator output feedback. Connect to the output
through a resistor divider for adjustable output voltage
(ISL8012-ADJ). For preset output voltage, connect this pin to
the output.
VCC (Pin 2)
SGND (Pin 8)
Input supply for the logic. Connect to VIN.
System ground for the control logic. All voltage levels are
measured with respect to this pin.
VIN (Pin 1)
EN (Pin 3)
Regulator enable pin. Enable the output when driven to high.
Shutdown the chip and discharge output capacitor when
driven to low. Do not leave this pin floating.
PG (Pin 4)
1ms timer output. At power-up or EN HI, this output is a 1ms
delayed Power-Good signal for the output voltage. This
output can be reset by a low RSI signal. 1ms starts when
RSI goes to high.
PGND (Pin 9)
Ground connect for the IC and thermal relief for the package.
The exposed pad must be connected to PGND and soldered
to the PCB.
LX (Pin 10)
Switching node connection. Connect to one terminal of
inductor.
Exposed Pad
MODE (Pin 5)
Mode Selection pin. Connect to logic high or input voltage
VIN for PFM mode; connect to logic low or ground for forced
PWM mode. Do not leave this pin floating.
The exposed pad must be connected to the PGND and
SGND pin for proper electrical performance. The exposed
pad must also be connected to as much as possible for
optimal thermal performance.
RSI (Pin 6)
This input resets the 1ms timer. When the output voltage is
within the PGOOD window, an internal timer is started and
generates a PG signal 1ms later when RSI is low. A high RSI
resets PG and RSI high to low transition restarts the internal
counter if the output voltage is within the window, otherwise
the counter is reset by the output voltage condition.
6
FN6616.0
March 11, 2008
ISL8012
Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 2.5V to 5.5V, EN = VIN,
100
100
90
90
80
1.5VOUT
70
EFFICIENCY (%)
EFFICIENCY (%)
MODE = 0V, L = 1.5µH, C1 = 2x10µF, C2 = 2x10µF, IOUT = 0A to 2A).
1.2VOUT
60
50
40
30
20
0.00
2.5VOUT
0.50
70
1.5VOUT
60
50
40
0.75
1.00
1.25
1.50
1.75
20
0.1
2.00
0.2
0.3
100
100
90
90
80
70
1.8VOUT
2.5VOUT
60
50
40
30
3.3VOUT
20
0.00
0.25
0.50
80
70
1.5VOUT
60
0.75
1.00
1.25
1.50
1.75
0.8
1.8VOUT
2.5VOUT
3.3VOUT
1.2VOUT
40
20
0.1
2.00
0.2
0.3
0.4
0.5
0.6
OUTPUT LOAD (A)
0.7
0.8
FIGURE 6. EFFICIENCY vs LOAD (1MHz 5VIN PFM)
1.000
160
0.875
3.3VIN PWM
0.750
0.625
0.500
0.375
5VIN PFM
5VIN PWM
3.3VIN PFM
0.125
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
OUTPUT LOAD (A)
FIGURE 7. POWER DISSIPATION vs LOAD (1MHz, VOUT = 1.8V)
7
POWER DISSIPATION (mW)
POWER DISSIPATION (W)
0.7
30
FIGURE 5. EFFICIENCY vs LOAD (1MHz 5VIN PWM)
0
0.00
0.6
50
OUTPUT LOAD (A)
0.250
0.5
FIGURE 4. EFFICIENCY vs LOAD (1MHz 3.3VIN PFM)
EFFICIENCY (%)
EFFICIENCY (%)
FIGURE 3. EFFICIENCY vs LOAD (1MHz 3.3VIN PWM)
1.2VOUT
0.4
OUTPUT LOAD (A)
OUTPUT LOAD (A)
1.5VOUT
2.5VOUT
1.8VOUT
1.2VOUT
30
1.8VOUT
0.25
80
140
120
100
80
PWM MODE
60
40
20
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VIN (V)
FIGURE 8. POWER DISSIPATION WITH NO LOAD vs VIN
(PWM VOUT = 1.8V)
FN6616.0
March 11, 2008
ISL8012
Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 2.5V to 5.5V, EN = VIN,
0.50
1.24
0.45
1.23
OUTPUT VOLTAGE (V)
POWER DISSIPATION (mW)
MODE = 0V, L = 1.5µH, C1 = 2x10µF, C2 = 2x10µF, IOUT = 0A to 2A). (Continued)
0.40
0.35
0.30
0.25
PFM
0.20
0.15
0.10
2.0
2.5
3.0
3.5
4.0
VIN (V)
4.5
5.0
5.5
1.18
1.83
1.82
3.3VIN PWM
1.52
1.51
1.50
1.49
3.3VIN PFM
1.48
1.47
0.00
0.25
5VIN PFM
0.50
0.75
3.3VIN PFM
5VIN PFM
1.17
0.25
0.50
1.00
1.25
1.50
1.75
1.80
1.79
1.78
3.3VIN PFM
1.77
5VIN PFM
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
OUTPUT LOAD (A)
FIGURE 12. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.8V)
3.36
2.57
3.35
5VIN PWM
2.55
2.53
2.51
2.49
3.3VIN PWM
5VIN PFM
3.3VIN PFM
0.25
0.50
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
2.00
5VIN PWM
1.75
0.00
2.00
2.59
2.43
0.00
1.75
1.76
FIGURE 11. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.5V)
2.45
1.50
3.3VIN PWM
1.81
OUTPUT LOAD (A)
2.47
0.75 1.00 1.25
OUTPUT LOAD (A)
FIGURE 10. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.2V)
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.19
1.54
5VIN PWM
3.3VIN PWM
1.20
1.55
1.53
5VIN PWM
1.21
1.16
0.00
6.0
FIGURE 9. POWER DISSIPATION WITH NO LOAD vs VIN
(PFM VOUT = 1.8V)
1.22
0.75
1.00
1.25
1.50
1.75
2.00
FIGURE 13. VOUT REGULATION vs LOAD (1MHz, VOUT = 2.5V)
8
4.5VIN PWM
5VIN PWM
3.33
3.32
3.31
3.30
3.29
OUTPUT LOAD (A)
5VIN PFM
3.34
3.28
0.00
4.5VIN PFM
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
OUTPUT LOAD (A)
FIGURE 14. VOUT REGULATION vs LOAD (1MHz, VOUT = 3.3V)
FN6616.0
March 11, 2008
ISL8012
Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 2.5V to 5.5V, EN = VIN,
MODE = 0V, L = 1.5µH, C1 = 2x10µF, C2 = 2x10µF, IOUT = 0A to 2A). (Continued)
LX 2V/DIV
LX 2V/DIV
VOUT RIPPLE
20mV/DIV
VOUT RIPPLE
20mV/DIV
IL 0.5A/DIV
IL 0.5A/DIV
FIGURE 15. STEADY STATE OPERATION AT NO LOAD (PWM),
(1µs/DIV)
FIGURE 16. STEADY STATE OPERATION AT NO LOAD (PFM),
(1µs/DIV)
LX 2V/DIV
LX 2V/DIV
VOUT RIPPLE
50mV/DIV
IL 0.5A/DIV
VOUT RIPPLE
20mV/DIV
FIGURE 17. STEADY STATE OPERATION WITH FULL LOAD,
(5µs/DIV)
IL 0.5A/DIV
FIGURE 18. MODE TRANSITION CCM TO DCM, (5µs/DIV)
VOUT RIPPLE
50mV/DIV
LX 2V/DIV
VOUT RIPPLE
50mV/DIV
IL 1A/DIV
IL 0.5A/DIV
FIGURE 19. MODE TRANSITION DCM TO CCM, (50µs/DIV)
9
FIGURE 20. LOAD TRANSIENT (PWM), (50µs/DIV)
FN6616.0
March 11, 2008
ISL8012
Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 2.5V to 5.5V, EN = VIN,
MODE = 0V, L = 1.5µH, C1 = 2x10µF, C2 = 2x10µF, IOUT = 0A to 2A). (Continued)
LX 2V/DIV
EN 5V/DIV
VOUT
0.5V/DIV
VOUT RIPPLE
50mV/DIV
IL 0.5A/DIV
IL 1A/DIV
PG 5V/DIV
FIGURE 21. LOAD TRANSIENT (PFM), (500µs/DIV)
EN 2V/DIV
FIGURE 22. SOFT-START WITH NO LOAD (PWM), (500µs/DIV)
EN 2V/DIV
VOUT
0.5V/DIV
VOUT
0.5V/DIV
IL 0.5A/DIV
IL 0.5A/DIV
PG 5V/DIV
FIGURE 23. SOFT-START AT NO LOAD (PFM), (500µs/DIV)
EN 2V/DIV
PG 5V/DIV
FIGURE 24. SOFT-START WITH PRE-BIASED 1V, (500µs/DIV)
EN 5V/DIV
VOUT
0.5V/DIV
VOUT
0.5V/DIV
IL 1A/DIV
IL 1A/DIV
PG 5V/DIV
PG 5V/DIV
FIGURE 25. SOFT-START AT FULL LOAD, (2ms/DIV)
10
FIGURE 26. SOFT-DISCHARGE SHUTDOWN, (2ms/DIV)
FN6616.0
March 11, 2008
ISL8012
Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 2.5V to 5.5V, EN = VIN,
MODE = 0V, L = 1.5µH, C1 = 2x10µF, C2 = 2x10µF, IOUT = 0A to 2A). (Continued)
RSI 2V/DIV
RSI 2V/DIV
VOUT RIPPLE
20mV/DIV
VOUT RIPPLE
20mV/DIV
PG 2V/DIV
PG 2V/DIV
FIGURE 27. RSI RESET, (200µs/DIV)
FIGURE 28. RSI RESET (ZOOM OUT), (200µs/DIV)
PHASE 2V/DIV
VOUT
1V/DIV
LX 2V/DIV
IL 2A/DIV
IL 2A/DIV
VOUT
0.5V/DIV
PG 5V/DIV
PG 5V/DIV
FIGURE 29. OUTPUT SHORT CIRCUIT, (500µs/DIV)
FIGURE 30. OUTPUT SHORT CIRCUIT RECOVERY, (500µs/DIV)
OUTPUT CURRENT LIMIT (A)
3.2
5.5VIN
3.1
3.0
2.9
2.8
2.7
3.3VIN
2.6
2.5
2.4
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
FIGURE 31. OUTPUT CURRENT LIMIT vs TEMPERATURE
11
FN6616.0
March 11, 2008
ISL8012
Theory of Operation
The ISL8012 is a step-down switching regulator optimized for
battery-powered handheld applications. The regulator operates
at 1MHz fixed switching frequency under heavy load conditions
to allow smaller external inductors and capacitors to be used for
minimal printed-circuit board (PCB) area. At light load, the
regulator reduces the switching frequency (unless forced to the
fixed frequency) to minimize the switching loss and to maximize
the battery life. The quiescent current when the output is not
loaded is typically only 40µA. The supply current is typically
only 0.1µA when the regulator is shut down.
signal to a current output. The voltage loop is internally
compensated with the 27pF and 390kΩ RC network. The
maximum EAMP voltage output is precisely clamped to
1.47V.
VEAMP
VCSA
DUTY
CYCLE
IL
PWM Control Scheme
Pulling the MODE pin LOW (<0.4V) forces the converter into
PWM mode, regardless of output current. The ISL8012
employs the current-mode pulse-width modulation (PWM)
control scheme for fast transient response and pulse-by-pulse
current limiting. Figure 2 shows the block diagram. The current
loop consists of the oscillator, the PWM comparator, current
sensing circuit and the slope compensation for the current loop
stability. The gain for the current sensing circuit is typically
285mV/A. The control reference for the current loops comes
from the error amplifier's (EAMP) output.
The PWM operation is initialized by the clock from the
oscillator. The P-Channel MOSFET is turned on at the
beginning of a PWM cycle and the current in the MOSFET
starts to ramp-up. When the sum of the current amplifier CSA
and the slope compensation (675mV/µs) reaches the control
reference of the current loop, the PWM comparator COMP
sends a signal to the PWM logic to turn off the P-MOSFET
and turn on the N-Channel MOSFET. The N-MOSFET stays
on until the end of the PWM cycle. Figure 32 shows the typical
operating waveforms during the PWM operation. The dotted
lines illustrate the sum of the slope compensation ramp and
the current-sense amplifier’s CSA output.
The output voltage is regulated by controlling the VEAMP
voltage to the current loop. The bandgap circuit outputs a
0.8V reference voltage to the voltage loop. The feedback
signal comes from the VFB pin. The soft-start block only
affects the operation during the start-up and will be
discussed separately. The error amplifier is a
transconductance amplifier that converts the voltage error
VOUT
FIGURE 32. PWM OPERATION WAVEFORMS
SKIP Mode
Pulling the MODE pin HIGH (>1.4V) forces the converter into
PFM mode. The ISL8012 enters a pulse-skipping mode at
light load to minimize the switching loss by reducing the
switching frequency. Figure 33 illustrates the skip-mode
operation. A zero-cross sensing circuit shown in Figure 2
monitors the N-MOSFET current for zero crossing. When 8
consecutive cycles of the inductor current crossing zero are
detected, the regulator enters the skip mode. During the 8
detecting cycles, the current in the inductor is allowed to
become negative. The counter is reset to zero when the
current in any cycle does not cross zero.
Once the skip mode is entered, the pulse modulation starts
being controlled by the SKIP comparator shown in Figure 2.
Each pulse cycle is still synchronized by the PWM clock. The PMOSFET is turned on at the clock's rising edge and turned off
when the output is higher than 1.5% of the nominal regulation
or when its current reaches the peak Skip current limit value.
Then the inductor current is discharging to zero Ampere and
stays at zero. The internal clock is disabled. The output voltage
reduces gradually due to the load current discharging the
output capacitor. When the output voltage drops to the nominal
voltage, the P-MOSFET will be turned on again at the rising
edge of the internal clock as it repeats the previous operations.
CLOCK
8 CYCLES
SKIP CURRENT LIMIT
LOAD CURRENT
IL
0
NOMINAL +1.5%
VOUT
NOMINAL
FIGURE 33. SKIP MODE OPERATION WAVEFORMS
12
FN6616.0
March 11, 2008
ISL8012
The regulator resumes normal PWM mode operation when
the output voltage drops 1.5% below the nominal voltage.
Mode Control
The ISL8012 has a MODE pin that controls the operation
mode. When the MODE pin is driven to low or shorted to
ground, the regulator operates in a forced PWM mode. The
forced PWM mode remains the fixed PWM frequency at light
load instead of entering the skip mode.
Overcurrent Protection
The overcurrent protection is realized by monitoring the CSA
output with the OCP comparator, as shown in Figure 2. The
current sensing circuit has a gain of 285mV/A, from the
P-MOSFET current to the CSA output. When the CSA output
reaches 1V, which is equivalent to 2.9A for the switch current
(0.15V offset), the OCP comparator is tripped to turn off the
P-MOSFET immediately. The overcurrent function protects
the switching converter from a shorted output by monitoring
the current flowing through the upper MOSFET.
Upon detection of overcurrent condition, the upper MOSFET
will be immediately turned off and will not be turned on again
until the next switching cycle.
Short-Circuit Protection
The short-circuit protection SCP comparator monitors the
VFB pin voltage for output short-circuit protection. When the
VFB is lower than 0.2V, the SCP comparator forces the
PWM oscillator frequency to drop to minimum value to
reduce the power dissipation. This comparator is effective
during start-up or an output short-circuit event.
RSI/PG Function
When powering up, the open-collector Power-Good output
holds low for about 1ms after VO reaches the preset voltage.
When the active-HI reset signal RSI is issued, PG goes to
low immediately and holds for the same period of time after
RSI comes back to LOW. The output voltage is unaffected.
Please refer to the timing diagram in Figure 34. When the
function is not used, connect RSI to ground and leave the
pull-up resister R4 open at the PG pin.
The PG output also serves as a 1ms delayed Power-Good
signal when the pull-up resister R1 is installed. The RSI pin
needs to be directly (or indirectly through a resistor)
connected to Ground for PG to be actively monitoring the
output voltage.
UVLO
When the input voltage is below the undervoltage lock-out
(UVLO) threshold, the regulator is disabled.
Soft Start-Up
The soft-start-up reduces the in-rush current during the
start-up. The soft-start block outputs a ramp reference to the
input of the error amplifier. This voltage ramp limits the
inductor current as well as the output voltage speed so that
the output voltage rises in a controlled fashion. When VFB is
less than 0.2V at the beginning of the soft-start, the
switching frequency is reduced to 1/3 of the nominal value
so that the output can start up smoothly at light load
condition. During soft-start, the IC operates in the SKIP
mode to support pre-biased output condition.
Enable
The enable (EN) input allows the user to control the turning
on or off the regulator for purposes such as power-up
sequencing. When the regulator is enabled, there is typically
a 600µs delay for waking up the bandgap reference and then
the soft-start-up begins.
Discharge Mode (Soft-Stop)
When a transition to shutdown mode occurs or the VIN
UVLO is set, the outputs discharge to GND through an
internal 100Ω switch.
Power MOSFETs
The power MOSFETs are optimized for best efficiency. The
ON-resistance for the P-MOSFET is typically 120mΩ and
the ON-resistance for the N-MOSFET is typically 110mΩ.
100% Duty Cycle
The ISL8012 features 100% duty cycle operation to
maximize the battery life. When the battery voltage drops to
a level that the ISL8012 can no longer maintain the
regulation at the output, the regulator completely turns on
the P-MOSFET. The maximum dropout voltage under the
100% duty-cycle operation is the product of the load current
and the ON-resistance of the P-MOSFET.
Thermal Shut-Down
The ISL8012 has built-in thermal protection. When the internal
temperature reaches +140°C, the regulator is completely shut
down. As the temperature drops to +115°C, the ISL8012
resumes operation by stepping through the soft-start.
Applications Information
Output Inductor and Capacitor Selection
VO
MIN
25ns
RSI
1ms
1ms
PG
FIGURE 34. RSI AND PG TIMING DIAGRAM
13
To consider steady state and transient operations, ISL8012
typically uses a 2.2µH output inductor. The higher or lower
inductor value can be used to optimize the total converter
system performance. For example, for higher output voltage
3.3V application, in order to decrease the inductor current
ripple and output voltage ripple, the output inductor value
FN6616.0
March 11, 2008
ISL8012
can be increased. It is recommended to set the ripple
inductor current approximately 30% of the maximum output
current for optimized performance. The inductor ripple
current can be expressed as shown in Equation 1:
VO ⎞
⎛
V O • ⎜ 1 – ---------⎟
V IN⎠
⎝
ΔI = --------------------------------------L • fS
Output Voltage Selection
The output voltage of the regulator can be programmed via an
external resistor divider that is used to scale the output voltage
relative to the internal reference voltage and feed it back to the
inverting input of the error amplifier. Refer to Figure 1.
(EQ. 1)
The inductor’s saturation current rating needs to be at least
larger than the peak current. The ISL8012 protects the
typical peak current 6A. The saturation current needs be
over 7A for maximum output current application.
ISL8012 uses internal compensation network and the output
capacitor value is dependent on the output voltage. The
ceramic capacitor is recommended to be X5R or X7R. The
recommended X5R or X7R minimum output capacitor
values are shown in Table 1.
TABLE 1. OUTPUT CAPACITOR VALUE vs VOUT
VOUT
(V)
COUT
L
0.8
22µF
1.5µH~3.3µH
1.2
22µF
1.5µH~3.3µH
1.5
22µF
1.8µH~3.3µH
1.8
22µF
2.2µH~3.3µH
2.5
22µF
2.2µH~4.7µH
3.3
22µF
2.2µH~4.7µH
3.6
22µF
2.2µH~4.7µH
In Table 1, the minimum output capacitor value is given for
the different output voltage to make sure that the whole
converter system is stable.
14
The output voltage programming resistor, R3, will depend on
the value chosen for the feedback resistor and the desired
output voltage of the regulator. The value for the feedback
resistor is typically between 10kΩ and 100kΩ, as shown in
Equation 2.
R 2 × 0.8V
R 3 = ---------------------------------V OUT – 0.8V
(EQ. 2)
If the output voltage desired is 0.8V, then R3 is left
unpopulated and R2 is shorted. For better performance, add
220pF in parallel with R2 (124kΩ).
Input Capacitor Selection
The main functions for the input capacitor are to provide
decoupling of the parasitic inductance and to provide filtering
function to prevent the switching current from flowing back to
the battery rail. One 22µF X5R or X7R ceramic capacitor is a
good starting point for the input capacitor selection.
Layout Recommendation
The layout is a very important converter design step to make
sure the designed converter works well. For ISL8012 buck
converter, the power loop is composed of the output inductor
L, the output capacitor COUT, LX pin and SGND pin. It is
necessary to make the power loop as small as possible.
The heat of the IC is mainly dissipated through the thermal
pad. Maximizing the copper area connected to the thermal
epad is preferable. In addition, a solid ground plane on the
second layer is helpful for EMI performance. Then connect
the epad to the ground plane with at lease 5 vias for best
thermal performance.
FN6616.0
March 11, 2008
ISL8012
Dual Flat No-Lead Plastic Package (DFN)
L10.3x3C
2X
0.10 C A
A
10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
D
MILLIMETERS
2X
0.10 C B
E
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.85
0.90
0.95
-
A1
-
-
0.05
-
A3
6
INDEX
AREA
b
0.20 REF
0.20
D
TOP VIEW
B
D2
//
A
C
SEATING
PLANE
D2
6
INDEX
AREA
0.08 C
7
8
D2/2
1
2.33
2.38
2.43
7, 8
1.69
7, 8
3.00 BSC
1.59
e
1.64
-
0.50 BSC
-
k
0.20
-
-
-
L
0.35
0.40
0.45
8
N
10
2
Nd
5
3
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
NX k
2. N is the number of terminals.
3. Nd refers to the number of terminals on D.
E2
E2/2
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
NX L
N
N-1
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
NX b
e
(Nd-1)Xe
REF.
BOTTOM VIEW
5
0.10 M C A B
(A1)
9 L
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
CL
NX (b)
5, 8
Rev. 1 4/06
2
(DATUM A)
8
0.30
3.00 BSC
E
E2
A3
SIDE VIEW
(DATUM B)
0.10 C
0.25
-
9. COMPLIANT TO JEDEC MO-229-WEED-3 except for
dimensions E2 & D2.
e
SECTION "C-C"
C C
TERMINAL TIP
FOR ODD TERMINAL/SIDE
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
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from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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15
FN6616.0
March 11, 2008