DATASHEET

PWM DC/DC Controller with VID Inputs for Portable
GPU Core-Voltage Regulator
ISL95870, ISL95870A, ISL95870B
The ISL95870, ISL95870A, ISL95870B ICs are Single-Phase
Synchronous-Buck PWM regulators featuring Intersil’s
proprietary R4 Technology™. The wide 3.3V to 25V input
voltage range is ideal for systems that run on battery or
AC-adapter power sources. The ISL95870A and ISL95870B
are low-cost solutions for applications requiring dynamically
selected slew-rate controlled output voltages. The soft-start
and dynamic setpoint slew-rates are capacitor programmed.
Voltage identification logic-inputs select four (ISL95870A,
ISL95870B) resistor-programmed setpoint reference voltages
that directly set the output voltage of the converter between
0.5V and 1.5V, and up to 5V with a feedback voltage divider.
Features
Compared with R3 modulator, the R4 modulator has
• Extremely Flexible Output Voltage Programmability
- 2-Bit VID Selects Four Independent Setpoint Voltages for
ISL95870B
- 2-Bit VID Selects Four Dependent or Three Independent
Setpoint Voltages for ISL95870A
- Simple Resistor Programming of Setpoint Voltages
equivalent light-load efficiency, faster transient performance,
accurately regulated frequency control and all internal
compensation. These updates, together with integrated
MOSFET drivers and schottky bootstrap diode, allow for a
high-performance regulator that is highly compact and needs
few external components. The differential remote sensing for
output voltage and selectable switching frequency are another
two new functions. For maximum efficiency, the converter
automatically enters diode-emulation mode (DEM) during
light-load conditions such as system standby.
• Input Voltage Range: 3.3V to 25V
• Output Voltage Range: 0.5V to 5V
• Precision Regulation
- Proprietary R4™ Frequency Control Loop
- ±0.5% System Accuracy Over -10°C to +100°C
• Optimal Transient Response
- Intersil’s R4™ Modulator Technology
• Output Remote Sense
• Selectable 300kHz, 500kHz, 600kHz or 1MHz PWM
Frequency in Continuous Conduction
• Automatic Diode Emulation Mode for Highest Efficiency
• Power-Good Monitor for Soft-Start and Fault Detection
Applications
• Mobile PC Graphical Processing Unit VCC Rail
• Mobile PC I/O Controller Hub (ICH) VCC Rail
• Mobile PC Memory Controller Hub (GMCH) VCC Rail
+5V
RVCC
CVCC
VCC
SREF
PGOOD
CIN
QHS
12
11
LO
10
VOUT
0.5V TO 5V
QLS
9
CO
CSEN
RTN1
8
VO
CBOOT
ROCSET
PHASE
VIN
3.3V TO 25V
RPGOOD
13
14
PVCC
LGATE
EN
5
CSOFT
ROFS1
4
UGATE
OCSET
GPIO
RTN
7
3
BOOT
FB
2
GND
6
1
RFB1
FSEL
RTN1
PGND
16
15
CPVCC
RO
ROFS
RFB
0
FIGURE 1. ISL95870 APPLICATION SCHEMATIC WITH ONE OUTPUT VOLTAGE SETPOINT AND DCR CURRENT SENSE
December 2, 2013
FN6899.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2009, 2013. All Rights Reserved
Intersil (and design) and R3 Technology are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL95870, ISL95870A, ISL95870B
Table of Contents
Applications Schematics: ISL95870 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Applications Schematics: ISL95870A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Applications Schematics: ISL95870B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ISL95870 Functional Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ISL95870A Functional Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
ISL95870B Functional Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Start-Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Start-Up and Voltage-Step Operation for ISL95870 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Start-Up and Voltage-Step Operation for ISL95870A, ISL95870B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Programming for ISL95870 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Programming for ISL95870A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Programming for ISL95870B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High Output Voltage Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R4 Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transient Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Diode Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overcurrent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overvoltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Over-Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PGOOD Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Integrated MOSFET Gate-Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adaptive Shoot-Through Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
15
15
15
15
16
16
17
18
18
19
19
20
20
21
21
21
21
21
21
General Application Design Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Selecting the LC Output Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Selecting the Input Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Selecting the Bootstrap Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Driver Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MOSFET Selection and Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
22
22
23
23
23
24
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
L16.2.6x1.8A
16 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
L20.3.2x1.8
20 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE (UTQFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
L20.3x4
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2
FN6899.1
December 2, 2013
ISL95870, ISL95870A, ISL95870B
Applications Schematics: ISL95870
RVCC
+5V
CVCC
CPVCC
UGATE
VOUT
0.5V TO 5V
LO
PHASE
QLS
PGOOD
CO
ROCSET
9
QHS
BOOT
CBOOT
8
10
4
FSEL
RPGOOD
VCC
13
PVCC
14
LGATE
3
5
CSOFT
ROFS1
SREF
11
FB
GPIO
2
CIN
CSEN
VO
EN
12
7
RTN
1
6
GND
RFB1
OCSET
RTN1
15
16
PGND
VIN
3.3V TO 25V
RTN1
RO
RFB
0
ROFS
FIGURE 2. ISL95870 APPLICATION SCHEMATIC WITH ONE OUTPUT VOLTAGE SETPOINT AND DCR CURRENT SENSE
RVCC
+5V
CVCC
CPVCC
RPGOOD
VCC
13
4
9
QHS
BOOT
UGATE
LO
RSEN
PHASE
VOUT
0.5V TO 5V
QLS
PGOOD
CBOOT
VO
8
10
CIN
ROCSET
14
PVCC
LGATE
3
7
CSOFT
ROFS1
SREF
11
6
GPIO
2
FB
EN
12
OCSET
RTN
1
5
RFB1
FSEL
GND
RTN1
15
16
PGND
VIN
3.3V TO 25V
CO
CSEN
RTN1
RO
RFB
ROFS
0
FIGURE 3. ISL95870 APPLICATION SCHEMATIC WITH ONE OUTPUT VOLTAGE SETPOINT AND RESISTOR CURRENT SENSE
3
FN6899.1
December 2, 2013
ISL95870, ISL95870A, ISL95870B
Applications Schematics: ISL95870A
RVCC
PVCC
3
18
4
17
RTN
VID1
GPIO
5
16
6
15
VID0
14
8
13
9
FB
SET1
7
RSET2
RSET3
12
CIN
QHS
BOOT
UGATE
LO
PHASE
VOUT
0.5V TO 5V
QLS
EN
PGOOD
CBOOT
FSEL
VO
CO
CSEN
RTN1
RO
RFB
CSOFT
RSET1
11
SET0
10
SREF
VCC
CVCC
OCSET
ROFS1
RTN1
19
VIN
3.3V TO 25V
ROCSET
GND
RFB1
2
RPGOOD
PGND
20
CPVCC
1
LGATE
+5V
ROFS
0
FIGURE 4. ISL95870A APPLICATION SCHEMATIC WITH FOUR OUTPUT VOLTAGE SETPOINTS AND DCR CURRENT SENSE
RVCC
RFB1
PVCC
19
3
18
4
17
RTN
VID1
5
16
6
15
VID0
SET0
14
8
9
13
FB
SET1
7
RSET2
RSET3
CSOFT
RSET1
11
SREF
10
GPIO
12
CVCC
CIN
QHS
BOOT
UGATE
VOUT
0.5V TO 5V
RSEN
LO
PHASE
EN
QLS
PGOOD
FSEL
CBOOT
VO
CO
CSEN
RTN1
RO
OCSET
ROFS1
RTN1
2
VIN
3.3V TO 25V
ROCSET
GND
VCC
RPGOOD
PGND
20
CPVCC
1
LGATE
+5V
RFB
ROFS
0
FIGURE 5. ISL95870A APPLICATION SCHEMATIC WITH FOUR OUTPUT VOLTAGE SETPOINTS AND RESISTOR CURRENT SENSE
4
FN6899.1
December 2, 2013
ISL95870, ISL95870A, ISL95870B
Applications Schematics: ISL95870B
RPGOOD
VCC
5
12
6
11
7
SET2
UGATE
VOUT
0.5V TO 5V
LO
PHASE
QLS
EN
PGOOD
CO
CBOOT
FSEL
CSEN
RTN1
RO
RFB
ROFS
RSET4
QHS
BOOT
ROCSET
18
13
RSET3
CSOFT
17
LGATE
4
RSET2
SET1
14
GND
CIN
10
SET0
3
CVCC
VO
RSET1
15
9
SREF
2
OCSET
VID0
16
8
VID1
GPIO
VIN
3.3V TO 25V
1
FB
ROFS1
RTN
19
20
RFB1
RTN1
PGND
CPVCC
PVCC
RVCC
+5V
0
FIGURE 6. ISL95870B APPLICATION SCHEMATIC WITH FOUR OUTPUT VOLTAGE SETPOINTS AND DCR CURRENT SENSE
RPGOOD
VCC
17
5
12
6
11
7
SET2
ROFS
RSET4
RSET3
CSOFT
18
13
RSET2
SET1
4
QHS
BOOT
LO
UGATE
RSEN
PHASE
PGOOD
VOUT
0.5V TO 5V
QLS
EN
CBOOT
FSEL
ROCSET
SET0
14
GND
CIN
CO
CSEN
RTN1
10
RSET1
3
CVCC
VO
SREF
15
9
VID0
2
OCSET
GPIO
16
8
VID1
VIN
3.3V TO 25V
1
FB
ROFS1
RTN
19
RFB1
RTN1
LGATE
20
PGND
CPVCC
PVCC
RVCC
+5V
RO
RFB
0
FIGURE 7. ISL95870B APPLICATION SCHEMATIC WITH FOUR OUTPUT VOLTAGE SETPOINTS AND RESISTOR CURRENT SENSE
5
FN6899.1
December 2, 2013
Block Diagram
VCC
POR
SOFT-START
CIRCUITRY
BOOT
EN
6
PGOOD
CIRCUITRY
PGOOD
UGATE
PHASE
DEAD-TIME
GENERATION
FB
INTERNAL
COMPENSATION
AMPLIFIER
PVCC
OVERVOLTAGE/
UNDERVOLTAGE
SREF
DRIVER
+
LGATE
PGND
*SET 0
R4
MODULATOR
*SET 1
VO
**SET2
*VID1
REFERENCE
VOLTAGE
CIRCUITRY
REMOTE SENSE
CIRCUITRY
OVERCURRENT
OCSET
*VID0
Fs SELECTION
CIRCUITRY
GND
*ISL95870A, ISL95870B ONLY
RTN
FSEL
FN6899.1
December 2, 2013
**ISL95870B ONLY
FIGURE 8. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM OF ISL95870, ISL95870A, ISL95870B
ISL95870, ISL95870A, ISL95870B
DRIVER
ISL95870, ISL95870A, ISL95870B
Pin Configurations
1 LGATE
13 VCC
14 PVCC
15 LGATE
16 PGND
PGND 2
20 PVCC
ISL95870A
(20 LD 3.2X1.8 µTQFN)
TOP VIEW
ISL95870
(16 LD 2.6X1.8 µTQFN)
TOP VIEW
19 VCC
RTN 2
11 UGATE
RTN 4
17 UGATE
EN 3
10 PHASE
VID1 5
16 PHASE
SREF 4
9 PGOOD
VID0 6
15 EN
14 PGOOD
SET0 8
13 FSEL
SET1 9
12 VO
OCSET 11
SREF 7
FB 10
VO 8
18 BOOT
OCSET 7
GND 3
FB 6
12 BOOT
17 VCC
18 PVCC
19 LGATE
20 PGND
ISL95870B
(20 LD 3X4 QFN)
TOP VIEW
RTN 1
16 BOOT
VID1 2
15 UGATE
VID0 3
14 PHASE
GND
SREF 4
13 EN
11 FSEL
7
VO 10
SET1 6
OCSET 9
12 PGOOD
FB 8
SET0 5
SET2 7
FSEL 5
GND 1
FN6899.1
December 2, 2013
ISL95870, ISL95870A, ISL95870B
ISL95870 Functional Pin Descriptions
PIN NUMBER
SYMBOL
DESCRIPTION
1
GND
IC ground for bias supply and signal reference.
2
RTN
Negative remote sense input of VOUT. If resistor divider consisting of RFB and ROFS is used at FB pin, the same resistor
divider should be used at RTN pin, i.e. keep RFB1 = RFB, and ROFS1 = ROFS.
3
EN
Enable input for the IC. Pulling EN above the rising threshold voltage initializes the soft-start sequence.
4
SREF
Soft-start and voltage slew-rate programming capacitor input. Connects internally to the inverting input of the VSET voltage
setpoint amplifier.
5
FSEL
Input for programming the regulator switching frequency. Pull this pin to VCC for 1MHz switching. Pull this pin to GND
with a 100kΩ resistor for 600kHz switching. Leave this pin floating for 500kHz switching. Pull this pin directly to GND
for 300kHz switching.
6
FB
Voltage feedback sense input. Connects internally to the inverting input of the control-loop error amplifier. The converter
is in regulation when the voltage at the FB pin equals the voltage on the SREF pin.
7
OCSET
Input for the overcurrent detection circuit. The overcurrent setpoint programming resistor ROCSET connects from this
pin to the sense node.
8
VO
Output voltage sense input for the R4 modulator. The VO pin also serves as the reference input for the overcurrent
detection circuit.
9
PGOOD
Power-good open-drain indicator output. This pin changes to high impedance when the converter is able to supply
regulated voltage.
10
PHASE
Return current path for the UGATE high-side MOSFET driver, VIN sense input for the R4 modulator, and inductor current
polarity detector input.
11
UGATE
High-side MOSFET gate driver output. Connect to the gate terminal of the high-side MOSFET of the converter.
12
BOOT
Positive input supply for the UGATE high-side MOSFET gate driver. The BOOT pin is internally connected to the cathode
of the Schottky boot-strap diode. Connect an MLCC between the BOOT pin and the PHASE pin.
13
VCC
14
PVCC
Input for the LGATE and UGATE MOSFET driver circuits. The PVCC pin is internally connected to the anode of the Schottky
boot-strap diode. Connect +5V to the PVCC pin and decouple with a MLCC to the PGND pin.
15
LGATE
Low-side MOSFET gate driver output. Connect to the gate terminal of the low-side MOSFET of the converter.
16
PGND
Return current path for the LGATE MOSFET driver. Connect to the source of the low-side MOSFET.
Input for the IC bias voltage. Connect +5V to the VCC pin and decouple with at least a MLCC to the GND pin.
8
FN6899.1
December 2, 2013
ISL95870, ISL95870A, ISL95870B
ISL95870A Functional Pin Descriptions
PIN NUMBER
SYMBOL
DESCRIPTION
1
LGATE
Low-side MOSFET gate driver output. Connect to the gate terminal of the low-side MOSFET of the converter.
2
PGND
Return current path for the LGATE MOSFET driver. Connect to the source of the low-side MOSFET.
3
GND
IC ground for bias supply and signal reference.
4
RTN
Negative remote sense input of VOUT. If resistor divider consisting of RFB and ROFS is used at FB pin, the same resistor
divider should be used at RTN pin, i.e. keep RFB1 = RFB, and ROFS1 = ROFS.
5
VID1
Logic input for setpoint voltage selector. Use in conjunction with the VID0 pin to select among four setpoint reference
voltages.
6
VID0
Logic input for setpoint voltage selector. Use in conjunction with the VID1 pin to select among four setpoint reference
voltages.
7
SREF
Soft-start and voltage slew-rate programming capacitor input and setpoint reference voltage programming resistor input.
Connects internally to the inverting input of the VSET voltage setpoint amplifier.
8
SET0
Voltage set-point programming resistor input.
9
SET1
Voltage set-point programming resistor input.
10
FB
11
OCSET
12
VO
13
FSEL
14
PGOOD
15
EN
16
PHASE
Return current path for the UGATE high-side MOSFET driver, VIN sense input for the R4 modulator, and inductor current
polarity detector input.
17
UGATE
High-side MOSFET gate driver output. Connect to the gate terminal of the high-side MOSFET of the converter.
18
BOOT
Positive input supply for the UGATE high-side MOSFET gate driver. The BOOT pin is internally connected to the cathode
of the Schottky boot-strap diode. Connect an MLCC between the BOOT pin and the PHASE pin.
19
VCC
20
PVCC
Voltage feedback sense input. Connects internally to the inverting input of the control-loop error transconductance
amplifier. The converter is in regulation when the voltage at the FB pin equals the voltage on the SREF pin.
Input for the overcurrent detection circuit. The overcurrent setpoint programming resistor ROCSET connects from this
pin to the sense node.
Output voltage sense input for the R4 modulator. The VO pin also serves as the reference input for the overcurrent
detection circuit.
Input for programming the regulator switching frequency. Pull this pin to VCC for 1MHz switching. Pull this pin to GND
with a 100kΩ resistor for 600kHz switching. Leave this pin floating for 500kHz switching. Pull this pin directly to GND
for 300kHz switching.
Power-good open-drain indicator output. This pin changes to high impedance when the converter is able to supply
regulated voltage.
Enable input for the IC. Pulling EN above the rising threshold voltage initializes the soft-start sequence.
Input for the IC bias voltage. Connect +5V to the VCC pin and decouple with at least a MLCC to the GND pin.
Input for the LGATE and UGATE MOSFET driver circuits. The PVCC pin is internally connected to the anode of the Schottky
boot-strap diode. Connect +5V to the PVCC pin and decouple with a MLCC to the PGND pin.
9
FN6899.1
December 2, 2013
ISL95870, ISL95870A, ISL95870B
ISL95870B Functional Pin Descriptions
PIN NUMBER
SYMBOL
DESCRIPTION
1
RTN
Negative remote sense input of VOUT. If resistor divider consisting of RFB and ROFS is used at FB pin, the same
resistor divider should be used at RTN pin, i.e. keep RFB1 = RFB, and ROFS1 = ROFS.
2
VID1
Logic input for setpoint voltage selector. Use in conjunction with the VID0 pin to select among four setpoint reference
voltages.
3
VID0
Logic input for setpoint voltage selector. Use in conjunction with the VID1 pin to select among four setpoint reference
voltages.
4
SREF
Soft-start and voltage slew-rate programming capacitor input and setpoint reference voltage programming resistor
input. Connects internally to the inverting input of the VSET voltage setpoint amplifier.
5
SET0
Voltage set-point programming resistor input.
6
SET1
Voltage set-point programming resistor input.
7
SET2
Voltage set-point programming resistor input.
8
FB
Voltage feedback sense input. Connects internally to the inverting input of the control-loop error transconductance
amplifier. The converter is in regulation when the voltage at the FB pin equals the voltage on the SREF pin.
9
OCSET
Input for the overcurrent detection circuit. The overcurrent setpoint programming resistor ROCSET connects from this
pin to the sense node.
10
VO
Output voltage sense input for the R4 modulator. The VO pin also serves as the reference input for the overcurrent
detection circuit.
11
FSEL
Input for programming the regulator switching frequency. Pull this pin to VCC for 1MHz switching. Pull this pin to GND
with a 100kΩ resistor for 600kHz switching. Leave this pin floating for 500kHz switching. Pull this pin directly to GND
for 300kHz switching.
12
PGOOD
Power-good open-drain indicator output. This pin changes to high impedance when the converter is able to supply
regulated voltage.
13
EN
14
PHASE
Return current path for the UGATE high-side MOSFET driver, VIN sense input for the R4 modulator, and inductor
current polarity detector input.
15
UGATE
High-side MOSFET gate driver output. Connect to the gate terminal of the high-side MOSFET of the converter.
16
BOOT
Positive input supply for the UGATE high-side MOSFET gate driver. The BOOT pin is internally connected to the
cathode of the Schottky boot-strap diode. Connect an MLCC between the BOOT pin and the PHASE pin.
17
VCC
18
PVCC
Input for the LGATE and UGATE MOSFET driver circuits. The PVCC pin is internally connected to the anode of the
Schottky boot-strap diode. Connect +5V to the PVCC pin and decouple with a MLCC to the PGND pin.
19
LGATE
Low-side MOSFET gate driver output. Connect to the gate terminal of the low-side MOSFET of the converter.
20
PGND
Return current path for the LGATE MOSFET driver. Connect to the source of the low-side MOSFET.
Bottom Pad
GND
Enable input for the IC. Pulling EN above the rising threshold voltage initializes the soft-start sequence.
Input for the IC bias voltage. Connect +5V to the VCC pin and decouple with at least a MLCC to the GND pin.
IC ground for bias supply and signal reference.
10
FN6899.1
December 2, 2013
ISL95870, ISL95870A, ISL95870B
Ordering Information
PART NUMBER
(Note 2)
PART
MARKING
TEMP RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL95870HRUZ-T (Notes 1, 4)
GAV
-10 to +100
16 Ld 2.6x1.8 µTQFN
L16.2.6x1.8A
ISL95870AHRUZ-T (Notes 1, 4)
GAW
-10 to +100
20 Ld 3.2x1.8 µTQFN
L20.3.2x1.8
ISL95870BHRZ (Note 3)
870B
-10 to +100
20 Ld 3x4 QFN
L20.3x4
ISL95870BHRZ-T (Notes 1, 3)
870B
-10 to +100
20 Ld 3x4 QFN
L20.3x4
ISL95870IRUZ-T (Notes 1, 4)
GAZ
-40 to +100
16 Ld 2.6x1.8 µTQFN
L16.2.6x1.8A
ISL95870AIRUZ-T (Notes 1, 4)
GAX
-40 to +100
20 Ld 3.2x1.8 µTQFN
L20.3.2x1.8
ISL95870BIRZ (Note 3)
870I
-40 to +100
20 Ld 3x4 QFN
L20.3x4
ISL95870BIRZ-T (Notes 1, 3)
870I
-40 to +100
20 Ld 3x4 QFN
L20.3x4
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. For Moisture Sensitivity Level (MSL), please see device information page for ISL95870, ISL95870A,ISL95870B. For more information on MSL please
see techbrief TB363.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate
- e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
11
FN6899.1
December 2, 2013
ISL95870, ISL95870A, ISL95870B
Absolute Maximum Ratings
Thermal Information
VCC, PVCC, PGOOD, FSEL to GND . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
VCC, PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V
GND to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
EN, SET0, SET1, SET2, VO,
VID0, VID1, FB, RTN, OCSET, SREF . . . . . . . . . . . . -0.3V to GND, VCC + 0.3V
BOOT Voltage (VBOOT-GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 33V
BOOT To PHASE Voltage (VBOOT-PHASE). . . . . . . . . . . . . . . . -0.3V to 7V (DC)
-0.3V to 9V (<10ns)
PHASE Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 28V
GND -8V (<20ns Pulse Width, 10µJ)
UGATE Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . VPHASE - 0.3V (DC) to VBOOT
VPHASE - 5V (<20ns Pulse Width, 10µJ) to VBOOT
LGATE Voltage . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V (DC) to VCC + 0.3V
. . . . . . . . . . . . . . . . . . GND - 2.5V (<20ns Pulse Width, 5µJ) to VCC + 0.3V
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1kV
Latch Up. . . . . . . . . . . . . . . . . . . . . . . . . . . JEDEC Class II Level A at +125°C
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
16 Ld UTQFN (Note 5) . . . . . . . . . . . . . . . . .
90
N/A
20 Ld UTQFN (Note 5) . . . . . . . . . . . . . . . . .
88
N/A
20 Ld QFN (Notes 6, 7) . . . . . . . . . . . . . . . .
44
5
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . . -55°C to +150°C
Operating Temperature Range:
For “H” Version Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
For “I” Version Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range:
For “H” Version Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
For “I” Version Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C
Converter Input Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . . . 3.3V to 25V
VCC, PVCC to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±5%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
ΝΟΤΕΣ:
5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
6. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
7. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications All typical specifications TA = +25°C, VCC = 5V. Boldface limits apply over the operating temperature range,
-40°C to +100°C, unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
(Note 11) TYP (Note 11) UNIT
VCC and PVCC
VCC Input Bias Current
IVCC
VCC Shutdown Current
PVCC Shutdown Current
EN = 5V, VCC = 5V, FB = 0.55V, SREF < FB
-
1.2
1.9
mA
IVCCoff
EN = GND, VCC = 5V
-
0
1.0
µA
IPVCCoff
EN = GND, PVCC = 5V
-
0
1.0
µA
VCC POR THRESHOLD
Rising VCC POR Threshold Voltage
VVCC_THR
4.40
4.52
4.60
V
Falling VCC POR Threshold Voltage
V
4.10
4.22
4.35
V
VID0 = VID1 = VCC, PWM Mode = CCM
(For “H” Version Parts, TA = -10°C to +100°C)
-0.5
-
+0.5
%
VID0 = VID1 = VCC, PWM Mode = CCM
-0.75
+0.5
%
VCC_THF
REGULATION
System Accuracy
PWM
Switching Frequency Accuracy
FSW
PWM Mode = CCM
(For “H” Version Parts, TA = -10°C to +100°C)
-15
-
+15
%
PWM Mode = CCM
-22
-
+15
%
EN = 5V
-
600
-
kΩ
VO
VO Input Impedance
RVO
VO Reference Offset Current
IVOSS
VENTHR < EN, SREF = Soft-Start Mode
-
8.5
-
µA
VO Input Leakage Current
IVOoff
EN = GND, VO = 3.6V
-
0
-
µA
12
FN6899.1
December 2, 2013
ISL95870, ISL95870A, ISL95870B
Electrical Specifications All typical specifications TA = +25°C, VCC = 5V. Boldface limits apply over the operating temperature range,
-40°C to +100°C, unless otherwise stated. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
(Note 11) TYP (Note 11) UNIT
ERROR AMPLIFIER
FB Input Bias Current
IFB
EN = 5V, FB = 0.50V
-20
-
+50
nA
Soft-Start Current
ISS
SREF = Soft-Start Mode
8.5
17
25.5
µA
85
±119
µA
IVS
SREF = Setpoint-Stepping Mode
(For “H” Version Parts, TA = -10°C to +100°C)
±51
Voltage Step Current
SREF = Setpoint-Stepping Mode
±46
±85
±127
µA
SREF (Note 8)
POWER GOOD
PGOOD Pull-down Impedance
RPG
PGOOD = 5mA Sink
-
50
150
Ω
PGOOD Leakage Current
IPG
PGOOD = 5V
-
0.1
1.0
µA
GATE DRIVER
UGATE Pull-Up Resistance (Note 9)
RUGPU
200mA Source Current
-
1.1
1.7
Ω
UGATE Source Current (Note 9)
IUGSRC
UGATE - PHASE = 2.5V
-
1.8
-
A
UGATE Sink Resistance (Note 9)
RUGPD
250mA Sink Current
-
1.1
1.7
Ω
UGATE Sink Current (Note 9)
IUGSNK
UGATE - PHASE = 2.5V
-
1.8
-
A
LGATE Pull-Up Resistance (Note 9)
RLGPU
250mA Source Current
-
1.1
1.7
Ω
LGATE Source Current (Note 9)
ILGSRC
LGATE - GND = 2.5V
-
1.8
-
A
LGATE Sink Resistance (Note 9)
RLGPD
250mA Sink Current
-
0.55
1.0
Ω
LGATE Sink Current (Note 9)
ILGSNK
LGATE - PGND = 2.5V
-
3.6
-
A
UGATE to LGATE Deadtime
tUGFLGR
UGATE falling to LGATE rising, no load
-
21
-
ns
LGATE to UGATE Deadtime
tLGFUGR
LGATE falling to UGATE rising, no load
-
21
-
ns
-
33
-
kΩ
PHASE
PHASE Input Impedance
RPHASE
BOOTSTRAP DIODE
Forward Voltage
VF
PVCC = 5V, IF = 2mA
-
0.58
-
V
Reverse Leakage
IR
VR = 25V
-
0
-
µA
CONTROL INPUTS
EN High Threshold Voltage
VENTHR
2.0
-
-
V
EN Low Threshold Voltage
VENTHF
-
-
1.0
V
0.85
1.7
2.55
µA
-
0
1.0
µA
EN Input Bias Current
IEN
EN Leakage Current
IENoff
EN = 5V
EN = GND
VID<0,1> High Threshold Voltage (Note 10)
VVIDTHR
0.65
-
-
V
VID<0,1> Low Threshold Voltage
(Note 10)
VVIDTHF
-
-
0.5
V
VID<0,1> Input Bias Current (Note 10)
IVID
EN = 5V
-
0.5
-
µA
VID<0,1> Leakage Current (Note 10)
IVIDoff
EN=0V
-
0
-
µA
VOCPTH
VOCSET - VO
-1.75
-
1.75
mV
PROTECTION
OCP Threshold Voltage
13
FN6899.1
December 2, 2013
ISL95870, ISL95870A, ISL95870B
Electrical Specifications All typical specifications TA = +25°C, VCC = 5V. Boldface limits apply over the operating temperature range,
-40°C to +100°C, unless otherwise stated. (Continued)
PARAMETER
SYMBOL
OCP Reference Current
IOCP
TEST CONDITIONS
MIN
MAX
(Note 11) TYP (Note 11) UNIT
EN = 5.0V
(For “H” Version Parts, TA = -10°C to +100°C)
7.65
8.5
9.35
µA
EN = 5.0V
7.05
8.5
9.35
µA
OCSET Input Resistance
ROCSET
EN = 5.0V
-
600
-
kΩ
OCSET Leakage Current
IOCSET
EN = GND
-
0
-
µA
UVP Threshold Voltage
VUVTH
VFB = %VSREF
81
84
87
%
116
120
%
VOVRTH
VFB = %VSREF
(For “H” Version Parts, TA = -10°C to +100°C)
113
OVP Rising Threshold Voltage
VFB = %VSREF
112.5
116
120
%
VFB = %VSREF
98
102
106
%
OVP Falling Threshold Voltage
VOVFTH
OTP Rising Threshold Temperature
(Note 9)
TOTRTH
-
150
-
°C
OTP Hysteresis (Note 9)
TOTHYS
-
25
-
°C
NOTES:
8. For ISL95870,there is one internal reference 0.5V. For ISL95870A, ISL95870B, there are four resistor-programmed reference voltages.
9. Limits established by characterization and are not production tested.
10. VID function is only for ISL95870A, ISL95870B.
11. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
14
FN6899.1
December 2, 2013
ISL95870, ISL95870A, ISL95870B
Theory of Operation
The following sections will provide a detailed description of the
inner workings of the ISL95870, ISL95870A, ISL95870B.
Power-On Reset
The IC is disabled until the voltage at the VCC pin has increased
above the rising power-on reset (POR) threshold voltage
VVCC_THR. The controller will become disabled when the voltage
at the VCC pin decreases below the falling POR threshold voltage
VVCC_THF. The POR detector has a noise filter of approximately
1µs.
Start-Up Timing
Once VCC has ramped above VVCC_THR, the controller can be
enabled by pulling the EN pin voltage above the input-high
threshold VENTHR. Approximately 20µs later, the voltage at the
SREF pin begins slewing to the designated VID set-point. The
converter output voltage at the FB feedback pin follows the
voltage at the SREF pin. During soft-start, The regulator always
operates in CCM until the soft-start sequence is complete.
Start-Up and Voltage-Step Operation for
ISL95870
When the voltage on the VCC pin has ramped above the rising
power-on reset voltage VVCC_THR, and the voltage on the EN pin
has increased above the rising enable threshold voltage VENTHR,
the SREF pin releases its discharge clamp, and enables the
reference amplifier VSET. The soft-start current ISS is limited to
17µA and is sourced out of the SREF pin and charges capacitor
CSOFT until VSREF equals VREF. The regulator controls the PWM
such that the voltage on the FB pin tracks the rising voltage on
the SREF pin. The elapsed time from when the EN pin is asserted
to when VSREF has charged CSOFT to VREF is called the soft-start
delay tSS which is given by Equation 1:
V SREF ⋅ C SOFT
t SS = ------------------------------------------I SS
(EQ. 1)
Where:
- ISS is the soft-start current source at the 17µA limit
- VSREF is the buffered VREF reference voltage
The end of soft-start is detected by ISS tapering off when
capacitor CSOFT charges to VREF. The internal SSOK flag is set,
the PGOOD pin goes high, and diode emulation mode (DEM) is
enabled.
Choosing the CSOFT capacitor to meet the requirements of a
particular soft-start delay tSS is calculated using Equation 2,
which is written as follows:
t SS ⋅ I SS
C SOFT = ----------------------V SREF
(EQ. 2)
Where:
- tSS is the soft-start delay
- ISS is the soft-start current source at the 17µA limit
- VSREF is the buffered VREF reference voltage
Start-Up and Voltage-Step Operation for
ISL95870A, ISL95870B
When the voltage on the VCC pin has ramped above the rising
power-on reset voltage VVCC_THR, and the voltage on the EN pin
has increased above the rising enable threshold voltage VENTHR,
the SREF pin releases its discharge clamp and enables the
reference amplifier VSET. The soft-start current ISS is limited to
17µA and is sourced out of the SREF pin into the parallel RC
network of capacitor CSOFT and resistance RT. The resistance RT
is the sum of all the series connected RSET programming
resistors and is written as Equation 3:
R T = R SET1 + R SET2 + …R SET ( n )
(EQ. 3)
The voltage on the SREF pin rises as ISS charges CSOFT to the
voltage reference setpoint selected by the state of the VID inputs at
the time the EN pin is asserted. The regulator controls the PWM
such that the voltage on the FB pin tracks the rising voltage on the
SREF pin. Once CSOFT charges to the selected setpoint voltage, the
ISS current source comes out of the 17µA current limit and decays
to the static value set by VSREF/RT. The elapsed time from when the
EN pin is asserted to when VSREF has reached the voltage reference
setpoint is the soft-start delay tSS which is given by Equation 4:
V START-UP
t SS = – ( R T ⋅ C SOFT ) ⋅ LN(1 – ------------------------------)
I SS ⋅ R T
(EQ. 4)
Where:
- ISS is the soft-start current source at the 17µA limit
- VSTART-UP is the setpoint reference voltage selected by the
state of the VID inputs at the time EN is asserted
- RT is the sum of the RSET programming resistors
The end of soft-start is detected by ISS tapering off when
capacitor CSOFT charges to the designated VSET voltage
reference setpoint. The SSOK flag is set, and the PGOOD pin goes
high.
The ISS current source changes over to the voltage-step current
source IVS which has a current limit of ±85µA. Whenever the VID
inputs or the external setpoint reference programs a different
setpoint reference voltage, the IVS current source charges or
discharges capacitor CSOFT to that new level at ±85µA. Once
CSOFT charges to the selected setpoint voltage, the IVS current
source comes out of the 85µA current limit and decays to the
static value set by VSREF/RT. The elapsed time to charge CSOFT
to the new voltage is called the voltage-step delay tVS and is
given by Equation 5:
( V NEW – V OLD )
t VS = – ( R T ⋅ C SOFT ) ⋅ LN(1 – -------------------------------------------)
I VS ⋅ R T
(EQ. 5)
Where:
- IVS is the ±85µA setpoint voltage-step current; positive
when VNEW > VOLD, negative when VNEW < VOLD
- VNEW is the new setpoint voltage selected by the VID inputs
- VOLD is the setpoint voltage that VNEW is changing from
- RT is the sum of the RSET programming resistors
Choosing the CSOFT capacitor to meet the requirements of a
particular soft-start delay tSS is calculated with Equation 6,
15
FN6899.1
December 2, 2013
ISL95870, ISL95870A, ISL95870B
Output Voltage Programming for ISL95870A
which is written as:
– t SS
C SOFT = --------------------------------------------------------------------V START-UP ⎞
⎛
⎜ R T ⋅ LN(1 – ------------------------------)⎟
I SS ⋅ R T ⎠
⎝
(EQ. 6)
Where:
- tSS is the soft-start delay
- ISS is the soft-start current source at the 17µA limit
- VSTART-UP is the setpoint reference voltage selected by the
state of the VID inputs at the time EN is asserted
- RT is the sum of the RSET programming resistors
Choosing the CSOFT capacitor to meet the requirements of a
particular voltage-step delay tVS is calculated with Equation 7,
which is written as:
– t VS
C SOFT = -----------------------------------------------------------------------------V NEW – V OLD ⎞
⎛
⎜ R T ⋅ LN(1 – ---------------------------------------)⎟
I VS ⋅ R T
⎝
⎠
(EQ. 7)
Where:
tVS is the voltage-step delay
VNEW is the new setpoint voltage
VOLD is the setpoint voltage that VNEW is changing from
IVS is the ±85µA setpoint voltage-step current; positive
when VNEW > VOLD, negative when VNEW < VOLD
- RT is the sum of the RSET programming resistors
-
Output Voltage Programming for ISL95870
The ISL95870 has a fixed 0.5V reference voltage (VSREF). As
shown in Figure 9, the output voltage is the reference voltage if
RFB is shorted and ROFS is open. A resistor divider consisting of
ROFS and RFB allows the user to scale the output voltage
between 0.5V and 5V. The relation between the output voltage
and the reference voltage is given in Equation 8:
R FB + R OFS
V OUT = V SREF ⋅ ---------------------------------R OFS
VOUT
(EQ. 8)
RFB
FB
VCOMP
-
ROFS
EA
The ISL95870A allows the user to select four different reference
voltages, thus four different output voltages, by voltage
identification pins VID1 and VID0. The maximum reference voltage
cannot be designed higher than 1.5V. The implementation scheme
is shown in Figure 10. The setpoint reference voltages are
programmed with resistors that use the naming convention
RSET(x) where (x) is the first, second, or third programming resistor
connected in series starting at the SREF pin and ending at the GND
pin. As shown in Table 1, different combinations of VID1 and VID0
closes different switches and leaves other switches open. For
example, for the case of VID1 = 1 and VID0 = 0, switch SW1 closes
and all the other three switches SW0, SW2 and SW3 are open. For
one combination of VID1 and VID0, the internal switch connects
the inverting input of the VSET amplifier to a specific node among
the string of RSET programming resistors. All the resistors between
that node and the SREF pin serve as the feedback impedance RF
of the VSET amplifier. Likewise, all the resistors between that node
and the GND pin serve as the input impedance RIN of the VSET
amplifier. Equation 9 gives the general form of the gain equation
for the VSET amplifier:
RF ⎞
⎛
V SETX = V REF ⋅ ⎜ 1 + ----------⎟
R
⎝
IN⎠
(EQ. 9)
Where:
- VREF is the 0.5V internal reference of the IC
- VSETx is the resulting setpoint reference voltage that
appears at the SREF pin
TABLE 1. ISL95870A VID TRUTH TABLE
VID STATE
RESULT
VID1
VID0
CLOSE
VSREF
VOUT
1
1
SW0
VSET1
VOUT1
1
0
SW1
VSET2
VOUT2
0
1
SW2
VSET3
VOUT3
0
0
SW1, SW3
VSET4
VOUT4
Equations 10, 11, 12 and 13 give the specific VSET equations for
the ISL95870A setpoint reference voltages.
The ISL95870A VSET1 setpoint is written as Equation 10:
+
VREF
+
VSET
-
V SET1 = V REF
(EQ. 10)
The ISL95870A VSET2 setpoint is written as Equation 11:
R SET1
⎛
⎞
V SET2 = V REF ⋅ ⎜ 1 + --------------------------------------------⎟
R SET2 + R SET3⎠
⎝
(EQ. 11)
The ISL95870A VSET3 setpoint is written as Equation 12:
SREF
CSOFT
R SET1 + R SET2⎞
⎛
V SET3 = V REF ⋅ ⎜ 1 + --------------------------------------------⎟
R SET3
⎝
⎠
(EQ. 12)
The ISL95870A VSET4 setpoint is written as Equation 13:
FIGURE 9. ISL95870 VOLTAGE PROGRAMMING CIRCUIT
R SET1⎞
⎛
V SET4 = V REF ⋅ ⎜ 1 + ------------------⎟
R SET2⎠
⎝
(EQ. 13)
The VSET1 is fixed at 0.5V because it corresponds to the closure
of internal switch SW0 that configures the VSET amplifier as a
16
FN6899.1
December 2, 2013
ISL95870, ISL95870A, ISL95870B
unity-gain voltage follower for the 0.5V voltage reference VREF.
Theoretically, VSET3 can be higher or lower or equal to VSET4
depending on the selection of RSET1, RSET2 and RSET3. However,
it is recommended to design the four reference voltages in the
following order:
ROFS allows the user to program the output voltage in the range
of 1.5V to 5V. The relation between the output voltage and the
reference voltage is given in Equation 18:
- VSET1 < VSET2 < VSET3 < VSET4 Thus,
- VOUT1 < VOUT2 < VOUT3 < VOUT4
For given four user selected reference voltages VSETx, the
following equation needs to be satisfied in order to have non-zero
solution for RSETx.
In this case, the four output voltages are equal to each of the
corresponding reference voltages multiplying the factor k.
V SET1 ⋅ V SET2 + V
SET3
⋅ V SET4 – V SET2 ⋅ V SET3 – V SET2 ⋅ V SET4 = 0
(EQ. 14)
The programmed resistors RSET1, RSET2 and RSET3 are designed
in the following way. First, assign an initial value to RSET3 of
approximately 100kΩ then calculate RSET1 and RSET2 using
Equations 15 and 16 respectively.
R SET3 ⋅ ( V SET4 – V REF ) ⋅ ( V SET2 – V REF )
R SET1 = --------------------------------------------------------------------------------------------------------------------V REF ⋅ ( V SET4 – V SET2 )
(EQ. 15)
R SET3 ⋅ ( V SET2 – V REF )
R SET2 = -------------------------------------------------------------------V SET4 – V SET2
(EQ. 16)
The sum of all the programming resistors should be
approximately 300kΩ, as shown in Equation 17, otherwise adjust
the value of RSET3 and repeat the calculations.
R SET1 + R SET2 + R SET3 ≅ 300kΩ
VOUT
(EQ. 17)
RFB
FB
VCOMP
-
ROFS
+
+
VSET
-
V OUTx = V SETx ⋅ k
RSET1
(EQ. 19)
Output Voltage Programming for ISL95870B
The ISL95870B allows the user to select four different reference
voltages, thus four different output voltages, by voltage
identification pins VID1 and VID0. The maximum reference
voltage cannot be designed higher than 1.5V. The
implementation scheme is shown in Figure 11. The setpoint
reference voltages are programmed with resistors that use the
naming convention RSET(x) where (x) is the first, second, third, or
fourth programming resistor connected in series starting at the
SREF pin and ending at the GND pin. As shown in Table 2,
different combinations of VID1 and VID0 close different switches
and leave other switches open. For example, for the case of
VID1 = 1 and VID0 = 0, switch SW1 closes and all the other three
switches SW0, SW2 and SW3 are open. For one combination of
VID1 and VID0, the internal switch connects the inverting input of
the VSET amplifier to a specific node among the string of RSET
programming resistors. All the resistors between that node and
the SREF pin serve as the feedback impedance RF of the VSET
amplifier. Likewise, all the resistors between that node and the
GND pin serve as the input impedance RIN of the VSET amplifier.
Equation 20 gives the general form of the gain equation for the
VSET amplifier:
(EQ. 20)
Where:
- VREF is the 0.5V internal reference of the IC
- VSETx is the resulting setpoint reference voltage that
appears at the SREF pin
SW0
SREF
TABLE 2. ISL95870B VID TRUTH TABLE
VID STATE
SW1
RSET2
SET0
SW2
RSET3
SET1
(EQ. 18)
OFS
RF ⎞
⎛
V SETX = V REF ⋅ ⎜ 1 + ----------⎟
R IN⎠
⎝
EA
VREF
0.5V
CSOFT
R FB + R OFS
V OUT = V SREF ⋅ ---------------------------------- = V SREF ⋅ k
R
RESULT
VID1
VID0
CLOSE
VSREF
VOUT
1
1
SW0
VSET1
VOUT1
1
0
SW1
VSET2
VOUT2
0
1
SW2
VSET3
VOUT3
0
0
SW3
VSET4
VOUT4
SW3
Equations 21, 22, 23 and 24 give the specific VSET equations for
the ISL95870B setpoint reference voltages.
The ISL95870B VSET1 setpoint is written as Equation 21:
FIGURE 10. ISL95870A VOLTAGE PROGRAMMING CIRCUIT
If the output voltage is in the range of 0.5V to 1.5V, the external
resistor-divider is not necessary. The output voltage is equal to
one of the reference voltages depending on the status of VID1
and VID0. The external resistor divider consisting of RFB and
17
(EQ. 21)
V SET1 = V REF
The ISL95870B VSET2 setpoint is written as Equation 22:
R SET1
⎛
⎞
V SET2 = V REF ⋅ ⎜ 1 + ---------------------------------------------------------------------⎟
R SET2 + R SET3 + R SET4⎠
⎝
(EQ. 22)
FN6899.1
December 2, 2013
ISL95870, ISL95870A, ISL95870B
The ISL95870B VSET3 setpoint is written as Equation 23:
(EQ. 23)
VOUT
FB
(EQ. 24)
R SET4 ⋅ V SET4 ⋅ ( V SET2 – V REF )
R SET1 = ------------------------------------------------------------------------------------------V REF ⋅ V SET2
(EQ. 25)
R SET4 ⋅ V SET4 ⋅ ( V SET3 – V SET2 )
R SET2 = ---------------------------------------------------------------------------------------------V SET2 ⋅ V SET3
(EQ. 26)
R SET4 ⋅ ( V SET4 – V SET3 )
R SET3 = ----------------------------------------------------------------------V SET3
(EQ. 27)
The sum of all the programming resistors should be
approximately 300kΩ, as shown in Equation 28, otherwise
adjust the value of RSET4 and repeat the calculations.
(EQ. 28)
If the output voltage is in the range of 0.5V to 1.5V, the external
resistor-divider is not necessary. The output voltage is equal to
one of the reference voltages depending on the status of VID1
and VID0. The external resistor divider consisting of RFB and
ROFS allows the user to program the output voltage in the range
of 1.5V to 5V. The relation between the output voltage and the
reference is given in Equation 29:
(EQ. 29)
OFS
In this case, the four output voltages are equal to each of the
corresponding reference voltages multiplying the factor k.
(EQ. 30)
V OUTx = V SETx ⋅ k
18
VREF
0.5V
VSET
-
CSOFT
SREF
RSET2
SET0
RSET3
SET1
SET2
SW0
SW1
SW2
SW3
RSET4
- VSET1 < VSET2 < VSET3 < VSET4 thus,
- VOUT1 < VOUT2 < VOUT3 < VOUT4
For given four user selected reference voltages VSETx, the
programmed resistors RSET1, RSET2, RSET3 and RSET4 are
designed in the following way. First, assign an initial value to RSET4
of approximately 100kΩ then calculate RSET1, RSET2 and RSET3
using Equations 25, 26, and 27 respectively.
R FB + R OFS
V OUT = V SREF ⋅ ---------------------------------- = V SREF ⋅ k
R
+
+
The VSET1 is fixed at 0.5V because it corresponds to the closure
of internal switch SW0 that configures the VSET amplifier as a
unity-gain voltage follower for the 0.5V voltage reference VREF.
The setpoint reference voltages use the naming convention
VSET(x) where (x) is the first, second, third, or fourth setpoint
reference voltage where:
R SET1 + R SET2 + R SET3 + R SET4 ≅ 300kΩ
VCOMP
EA
ROFS
The ISL95870B VSET4 setpoint is written as Equation 24:
R SET1 + R SET2 + R
⎛
SET3⎞
V SET4 = V REF ⋅ ⎜ 1 + ---------------------------------------------------------------------⎟
R
⎝
⎠
SET4
RFB
RSET1
R SET1 + R SET2⎞
⎛
V SET3 = V REF ⋅ ⎜ 1 + --------------------------------------------⎟
R SET3 + R SET4⎠
⎝
FIGURE 11. ISL95870B VOLTAGE PROGRAMMING CIRCUIT
High Output Voltage Programming
The ISL95870 has a fixed 0.5V reference voltage (VSREF). For
high output voltage application, the resistor divider consisting of
RFB and ROFS requires large ratio (RFB :ROFS = 9:1 for 5V
output). The FB pin with large ratio resistor divider is noise
sensitive and the PCB layout should be carefully routed. It is
recommended to use small value resistor divider such as
RFB=1kΩ.
In general the ISL95870A and ISL95870B have much better
jitter performance than the ISL95870 when the output voltage is
in the range of 3.3V to 5V, particularly in DCM. This is because
VSREF voltage can be set to 1.5V and a smaller ratio resistor
divider can be used. This makes the singal to noise ratio at FB pin
much better. So for 3.3V to 5V output, the ISL95870A and
ISL95870B are recommended with VSREF set to 1.5V.
R4 Modulator
The R4 modulator is an evolutionary step in R3 technology. Like
R3, the R4 modulator allows variable frequency in response to
load transients and maintains the benefits of current-mode
hysteretic controllers. However, in addition, the R4 modulator
reduces regulator output impedance and uses accurate
referencing to eliminate the need for a high-gain voltage
amplifier in the compensation loop. The result is a topology that
can be tuned to voltage-mode hysteretic transient speed while
maintaining a linear control model and removes the need for any
compensation. This greatly simplifies the regulator design for
customers and reduces external component cost.
FN6899.1
December 2, 2013
ISL95870, ISL95870A, ISL95870B
Stability
The removal of compensation derives from the R4 modulator’s
lack of need for high DC gain. In traditional architectures, high DC
gain is achieved with an integrator in the voltage loop. The
integrator introduces a pole in the open-loop transfer function at
low frequencies. That, combined with the double-pole from the
output L/C filter, creates a three pole system that must be
compensated to maintain stability.
Classic control theory requires a single-pole transition through
unity gain to ensure a stable system. Current-mode architectures
(includes peak, peak-valley, current-mode hysteretic, R3 and R4)
generate a zero at or near the L/C resonant point, effectively
canceling one of the system’s poles. The system still contains
two poles, one of which must be canceled with a zero before
unity gain crossover to achieve stability. Compensation
components are added to introduce the necessary zero.
wide range of output filter choices. The result is a stable system
with no need for compensation components or complex
equations to properly tune the stability.
R2
VOUT
VCOMP
R1
VDAC
FIGURE 14. NON-INTEGRATED R4 ERROR-AMPLIFIER
CONFIGURATION
Figure 14 shows the R4 error-amplifier that does not require an
integrator for high DC gain to achieve accurate regulation. The
result to the open loop response can be seen in Figure 15.
R4 LOOP GAIN (dB)
COMPENSATION TO COUNTER
INTEGRATOR POLE
INTEGRATOR
FOR HIGH DC GAIN
L/C DOUBLE-POLE
p1
VOUT
VDAC
R3 LOOP GAIN (dB)
INTEGRATOR POLE
p1
ec
/d
B
0d dec
-2
/
B
c
0d
/ de
dB
-40
CURRENT-MODE
ZERO
z1
NO COMPENSATOR IS
NEEDED
-2
FIGURE 12. INTEGRATOR ERROR-AMPLIFIER CONFIGURATION
SYSTEM HAS 2 POLES
AND 1 ZERO
p2
VCOMP
f (Hz)
FIGURE 15. UNCOMPENSATED R4 OPEN-LOOP RESPONSE
L/C DOUBLE-POLE
Transient Response
p2
-20dB CROSSOVER
REQUIRED FOR STABILITY
p3
COMPENSATOR TO
ADD z2 IS NEEDED
CURRENT-MODE
ZERO
z1
-2
dB
-40
/d
B
0d
ec
c
ec
/de
-60dB/d
In addition to requiring a compensation zero, the integrator in
traditional architectures also slows system response to transient
conditions. The change in COMP voltage is slow in response to a
rapid change in output voltage. If the integrating capacitor is
removed, COMP moves as quickly as VOUT, and the modulator
immediately increases or decreases switching frequency to
recover the output voltage.
IOUT
f (Hz)
Figure 12 illustrates the classic integrator configuration for a
voltage loop error-amplifier. While the integrator provides the
high DC gain required for accurate regulation in traditional
technologies, it also introduces a low-frequency pole into the
control loop. Figure 13 shows the open-loop response that results
from the addition of an integrating capacitor in the voltage loop.
The compensation components found in Figure 12 are necessary
to achieve stability.
Because R4 does not require a high-gain voltage loop, the
integrator can be removed, reducing the number of inherent
poles in the loop to two. The current-mode zero continues to
cancel one of the poles, ensuring a single-pole crossover for a
19
t
R4
FIGURE 13. UNCOMPENSATED INTEGRATOR OPEN-LOOP RESPONSE
R3
VCOMP
t
VOUT
t
FIGURE 16. R3 vs R4 IDEALIZED TRANSIENT RESPONSE
FN6899.1
December 2, 2013
ISL95870, ISL95870A, ISL95870B
The dotted red and blue lines in Figure 16 represent the time
delayed behavior of VOUT and VCOMP in response to a load
transient when an integrator is used. The solid red and blue lines
illustrate the increased response of R4 in the absence of the
integrator capacitor.
Diode Emulation
The polarity of the output inductor current is defined as positive
when conducting away from the phase node, and defined as
negative when conducting towards the phase node. The DC
component of the inductor current is positive, but the AC
component known as the ripple current, can be either positive or
negative. Should the sum of the AC and DC components of the
inductor current remain positive for the entire switching period,
the converter is in continuous-conduction-mode (CCM). However,
if the inductor current becomes negative or zero, the converter is
in discontinuous-conduction-mode (DCM).
Unlike the standard DC/DC buck regulator, the synchronous
rectifier can sink current from the output filter inductor during
DCM, reducing the light-load efficiency with unnecessary
conduction loss as the low-side MOSFET sinks the inductor
current. The ISL95870, ISL95870A, ISL95870B controllers avoid
the DCM conduction loss by making the low-side MOSFET
emulate the current-blocking behavior of a diode. This
smart-diode operation called diode-emulation-mode (DEM) is
triggered when the negative inductor current produces a positive
voltage drop across the rDS(ON) of the low-side MOSFET for eight
consecutive PWM cycles while the LGATE pin is high. The
converter will exit DEM on the next PWM pulse after detecting a
negative voltage across the rDS(ON) of the low-side MOSFET.
It is characteristic of the R4 architecture for the PWM switching
frequency to decrease while in DCM, increasing efficiency by
reducing unnecessary gate-driver switching losses. The extent of
the frequency reduction is proportional to the reduction of load
current. Upon entering DEM, the PWM frequency is forced to fall
approximately 30% by forcing a similar increase of the window
voltage V W. This measure is taken to prevent oscillating between
modes at the boundary between CCM and DCM. The 30%
increase of VW is removed upon exit of DEM, forcing the PWM
switching frequency to jump back to the nominal CCM value.
Overcurrent
The overcurrent protection (OCP) setpoint is programmed with
resistor ROCSET, which is connected across the OCSET and
PHASE pins. Resistor RO is connected between the VO pin and
the actual output voltage of the converter. During normal
operation, the VO pin is a high impedance path, therefore there is
no voltage drop across RO. The value of resistor RO should always
match the value of resistor ROCSET.
L
DCR
IL
PHASE
+
ROCSET
8.5µA
OCSET
+ VROCSET
VDCR
CSEN
VO
_
CO
_
RO
VO
FIGURE 17. OVERCURRENT PROGRAMMING CIRCUIT
Figure 17 shows the overcurrent set circuit. The inductor consists
of inductance L and the DC resistance DCR. The inductor DC
current IL creates a voltage drop across DCR, which is given by
Equation 31:
V DCR = I L ⋅ DCR
(EQ. 31)
The IOCSET current source sinks 8.5µA into the OCSET pin,
creating a DC voltage drop across the resistor ROCSET, which is
given by Equation 32:
V ROCSET = 8.5μA ⋅ R OCSET
(EQ. 32)
The DC voltage difference between the OCSET pin and the VO pin,
which is given by Equation 33:
V OCSET – V VO = V DCR – V ROCSET = I L ⋅ DCR – I OCSET ⋅ R OCSET
(EQ. 33)
The IC monitors the voltage of the OCSET pin and the VO pin.
When the voltage of the OCSET pin is higher than the voltage of
the VO pin for more than 10µs, an OCP fault latches the
converter off.
The value of ROCSET is calculated with Equation 34, which is
written as:
I OC ⋅ DCR
R OCSET = ---------------------------I OCSET
(EQ. 34)
Where:
- ROCSET (Ω) is the resistor used to program the overcurrent
setpoint
- IOC is the output DC load current that will activate the OCP
fault detection circuit
- DCR is the inductor DC resistance
For example, if IOC is 20A and DCR is 4.5mΩ, the choice of
ROCSET is equal to 20A x 4.5mΩ/8.5µA = 10.5kΩ.
Resistor ROCSET and capacitor CSEN form an R-C network to
sense the inductor current. To sense the inductor current
correctly not only in DC operation, but also during dynamic
operation, the R-C network time constant ROCSET CSEN needs to
match the inductor time constant L/DCR. The value of CSEN is
then written as Equation 35:
L
C SEN = -----------------------------------------R OCSET ⋅ DCR
(EQ. 35)
For example, if L is 1.5µH, DCR is 4.5mΩ, and ROCSET is 9kΩ, the
choice of CSEN = 1.5µH/(9kΩ x 4.5mΩ) = 0.037µF.
20
FN6899.1
December 2, 2013
ISL95870, ISL95870A, ISL95870B
When an OCP fault is declared, the converter will be latched off
and the PGOOD pin will be asserted low. The fault will remain
latched until the EN pin has been pulled below the falling EN
threshold voltage VENTHF or if VCC has decayed below the falling
POR threshold voltage VVCC_THF.
Overvoltage
The OVP fault detection circuit triggers after the FB pin voltage is
above the rising overvoltage threshold VOVRTH for more than 2µs.
For example, if the converter is programmed to regulate 1.0V at
the FB pin, that voltage would have to rise above the typical
VOVRTH threshold of 116% for more than 2µs in order to trip the
OVP fault latch. In numerical terms, that would be
116% x 1.0V = 1.16V. When an OVP fault is declared, the
converter will be latched off and the PGOOD pin will be asserted
low. The fault will remain latched until the EN pin has been pulled
below the falling EN threshold voltage VENTHF or if VCC has
decayed below the falling POR threshold voltage VVCC_THF.
Although the converter has latched-off in response to an OVP
fault, the LGATE gate-driver output will retain the ability to toggle
the low-side MOSFET on and off, in response to the output
voltage transversing the VOVRTH and VOVFTH thresholds. The
LGATE gate-driver will turn-on the low-side MOSFET to discharge
the output voltage, protecting the load. The LGATE gate-driver will
turn-off the low-side MOSFET once the FB pin voltage is lower
than the falling overvoltage threshold VOVRTH for more than 2µs.
The falling overvoltage threshold VOVFTH is typically 102%. That
means if the FB pin voltage falls below 102% x 1.0V = 1.02V for
more than 2µs, the LGATE gate-driver will turn off the low-side
MOSFET. If the output voltage rises again, the LGATE driver will
again turn on the low-side MOSFET when the FB pin voltage is
above the rising overvoltage threshold VOVRTH for more than 2µs.
By doing so, the IC protects the load when there is a consistent
overvoltage condition.
Undervoltage
The UVP fault detection circuit triggers after the FB pin voltage is
below the undervoltage threshold VUVTH for more than 2µs. For
example if the converter is programmed to regulate 1.0V at the FB
pin, that voltage would have to fall below the typical VUVTH
threshold of 84% for more than 2µs in order to trip the UVP fault
latch. In numerical terms, that would be 84% x 1.0V = 0.84V.
When a UVP fault is declared, the converter will be latched off and
the PGOOD pin will be asserted low. The fault will remain latched
until the EN pin has been pulled below the falling EN threshold
voltage VENTHF or if VCC has decayed below the falling POR
threshold voltage VVCC_THF.
It is likely that the IC will detect an UVP fault because in the absence
of PWM, the output voltage decays below the undervoltage
threshold VUVTH.
PGOOD Monitor
The PGOOD pin indicates when the converter is capable of
supplying regulated voltage. The PGOOD pin is an undefined
impedance if the VCC pin has not reached the rising POR threshold
VVCC_THR, or if the VCC pin is below the falling POR threshold
VVCC_THF. If there is a fault condition of output overcurrent,
overvoltage or undervoltage, PGOOD is asserted low. The PGOOD
pull-down impedance is 50Ω.
Integrated MOSFET Gate-Drivers
The LGATE pin and UGATE pins are MOSFET driver outputs. The
LGATE pin drives the low-side MOSFET of the converter while the
UGATE pin drives the high-side MOSFET of the converter.
The LGATE driver is optimized for low duty-cycle applications
where the low-side MOSFET experiences long conduction times.
In this environment, the low-side MOSFETs require exceptionally
low rDS(ON) and tend to have large parasitic charges that conduct
transient currents within the devices in response to high dv/dt
switching present at the phase node. The drain-gate charge in
particular can conduct sufficient current through the driver
pull-down resistance that the VGS(th) of the device can be
exceeded and turned on. For this reason, the LGATE driver has
been designed with low pull-down resistance and high sink
current capability to ensure clamping the MOSFETs gate voltage
below VGS(th).
Adaptive Shoot-Through Protection
Adaptive shoot-through protection prevents a gate-driver output
from turning on until the opposite gate-driver output has fallen
below approximately 1V. The dead-time shown in Figure 18 is
extended by the additional period that the falling gate voltage
remains above the 1V threshold. The high-side gate-driver output
voltage is measured across the UGATE and PHASE pins while the
low-side gate-driver output voltage is measured across the LGATE
and PGND pins. The power for the LGATE gate-driver is sourced
directly from the PVCC pin. The-power for the UGATE gate-driver is
supplied by a boot-strap capacitor connected across the BOOT
and PHASE pins. The capacitor is charged each time the phase
node voltage falls a diode drop below PVCC such as when the
low-side MOSFET is turned on.
Over-Temperature
When the temperature of the IC increases above the rising threshold
temperature TOTRTH, it will enter the OTP state that suspends the
PWM, forcing the LGATE and UGATE gate-driver outputs low. The
status of the PGOOD pin does not change nor does the converter
latch-off. The PWM remains suspended until the IC temperature
falls below the hysteresis temperature TOTHYS at which time normal
PWM operation resumes. The OTP state can be reset if the EN pin is
pulled below the falling EN threshold voltage VENTHF or if VCC has
decayed below the falling POR threshold voltage VVCC_THF. All other
protection circuits remain functional while the IC is in the OTP state.
21
FN6899.1
December 2, 2013
ISL95870, ISL95870A, ISL95870B
A DC/DC buck regulator must have output capacitance CO into
which ripple current IP-P can flow. Current IP-P develops a
corresponding ripple voltage VP-P across CO, which is the sum of
the voltage drop across the capacitor ESR and of the voltage
change stemming from charge moved in and out of the
capacitor. These two voltages are expressed in Equations 39
and 40:
UGATE
ΔV ESR = I P-P ⋅ E SR
1V
1V
I P-P
ΔV C = --------------------------------8 ⋅ CO ⋅ F
(EQ. 39)
(EQ. 40)
SW
1V
1V
LGATE
FIGURE 18. GATE DRIVE ADAPTIVE SHOOT-THROUGH PROTECTION
General Application Design
Guide
This design guide is intended to provide a high-level explanation of
the steps necessary to design a single-phase buck converter. It is
assumed that the reader is familiar with many of the basic skills
and techniques referenced in the following. In addition to this
guide, Intersil provides complete reference designs that include
schematics, bills of materials, and example board layouts.
Selecting the LC Output Filter
The duty cycle of an ideal buck converter is a function of the
input and the output voltage. This relationship is expressed in
Equation 36:
VO
D = --------V IN
(EQ. 36)
The output inductor peak-to-peak ripple current is expressed in
Equation 37:
VO ⋅ ( 1 – D )
I P-P = ------------------------------F SW ⋅ L
(EQ. 37)
A typical step-down DC/DC converter will have an IPP of 20% to
40% of the maximum DC output load current. The value of IP-P is
selected based upon several criteria such as MOSFET switching
loss, inductor core loss, and the resistive loss of the inductor
winding. The DC copper loss of the inductor can be estimated
using Equation 38:
(EQ. 38)
2
P COPPER = I LOAD ⋅ DCR
Where, ILOAD is the converter output DC current.
The copper loss can be significant so attention has to be given to
the DCR of the inductor. Another factor to consider when
choosing the inductor is its saturation characteristics at elevated
temperature. A saturated inductor could cause destruction of
circuit components, as well as nuisance OCP faults.
22
If the output of the converter has to support a load with high
pulsating current, several capacitors will need to be paralleled to
reduce the total ESR until the required VP-P is achieved. The
inductance of the capacitor can significantly impact the output
voltage ripple and cause a brief voltage spike if the load transient
has an extremely high slew rate. Low inductance capacitors should
be considered. A capacitor dissipates heat as a function of RMS
current and frequency. Be sure that IP-P is shared by a sufficient
quantity of paralleled capacitors so that they operate below the
maximum rated RMS current at FSW. Take into account that the
rated value of a capacitor can fade as much as 50% as the DC
voltage across it increases.
Selecting the Input Capacitor
The important parameters for the bulk input capacitors are the
voltage rating and the RMS current rating. For reliable operation,
select bulk capacitors with voltage and current ratings above the
maximum input voltage and capable of supplying the RMS
current required by the switching circuit. Their voltage rating
should be at least 1.25x greater than the maximum input
voltage, while a voltage rating of 1.5x is a preferred rating. Figure
19 is a graph of the input RMS ripple current, normalized relative
to output load current, as a function of duty cycle that is adjusted
for converter efficiency. The ripple current calculation is written as
Equation 41:
2
2 D
2
2
( I MAX ⋅ ( D – D ) ) + ⎛ x ⋅ I MAX ⋅ ------ ⎞
⎝
12 ⎠
I IN_RMS = -------------------------------------------------------------------------------------------------------I MAX
(EQ. 41)
Where:
- IMAX is the maximum continuous ILOAD of the converter
- x is a multiplier (0 to 1) corresponding to the inductor
peak-to-peak ripple amplitude expressed as a percentage of
IMAX (0% to 100%)
- D is the duty cycle that is adjusted to take into account the
efficiency of the converter
Duty cycle is written as Equation 42:
VO
D = -------------------------V IN ⋅ EFF
(EQ. 42)
FN6899.1
December 2, 2013
ISL95870, ISL95870A, ISL95870B
In addition to the bulk capacitors, some low ESL ceramic
capacitors are recommended to decouple between the drain of
the high-side MOSFET and the source of the low-side MOSFET.
0.6
NORMALIZED INPUT
RMS RIPPLE CURRENT
0.5
x=0
0.4
x = 0.5
0.3
0.2
Where:
Fsw is the switching frequency of the PWM signal
VU is the upper gate driver bias supply voltage
VL is the lower gate driver bias supply voltage
QU is the charge to be delivered by the upper driver into the
gate of the MOSFET and discrete capacitors
- QL is the charge to be delivered by the lower driver into the
gate of the MOSFET and discrete capacitors
- PL is the quiescent power consumption of the lower driver
- PU is the quiescent power consumption of the upper driver
-
x=1
0.1
0
0
1000
QU =100nC
QL =200nC
900
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Selecting the Bootstrap Capacitor
The integrated driver features an internal bootstrap schottky
diode. Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit. The bootstrap
capacitor voltage rating is selected to be at least 10V. Although the
theoretical maximum voltage of the capacitor is PVCC-VDIODE
(voltage drop across the boot diode), large excursions below
ground by the phase node requires at least a 10V rating for the
bootstrap capacitor. The bootstrap capacitor can be chosen from
Equation 43:
(EQ. 43)
Where:
- QGATE is the amount of gate charge required to fully charge
the gate of the upper MOSFET
- ΔVBOOT is the maximum decay across the BOOT capacitor
As an example, suppose the high-side MOSFET has a total gate
charge Qg, of 25nC at VGS = 5V, and a ΔVBOOT of 200mV. The
calculated bootstrap capacitance is 0.125µF; for a comfortable
margin, select a capacitor that is double the calculated
capacitance. In this example, 0.22µF will suffice. Use a low
temperature-coefficient ceramic capacitor.
Driver Power Dissipation
Switching power dissipation in the driver is mainly a function of
the switching frequency and total gate charge of the selected
MOSFETs. Calculating the power dissipation in the driver for a
desired application is critical to ensuring safe operation.
Exceeding the maximum allowable power dissipation level will
push the IC beyond the maximum recommended operating
junction temperature of +125°C. When designing the
application, it is recommended that the following calculation be
performed to ensure safe operation at the desired frequency for
the selected MOSFETs. The power dissipated by the drivers is
approximated as Equation 44:
23
POWER (mW)
700
FIGURE 19. NORMALIZED INPUT RMS CURRENT FOR EFF = 1
P = F sw ( 1.5V U Q + V L Q ) + P L + P U
U
L
QU =50nC
QL=50nC
800
DUTY CYCLE
Q GATE
C BOOT ≥ -----------------------ΔV BOOT
QU =50nC
QL =100nC
600
QU =20nC
QL=50nC
500
400
300
200
100
0
0
200
400
600
800
1k
1.2k 1.4k 1.6k 1.8k 2k
FREQUENCY (Hz)
FIGURE 20. POWER DISSIPATION vs FREQUENCY
MOSFET Selection and Considerations
The choice of MOSFETs depends on the current each MOSFET will
be required to conduct, the switching frequency, the capability of
the MOSFETs to dissipate heat, and the availability and nature of
heat sinking and air flow.
Typically, a MOSFET cannot tolerate even brief excursions beyond
their maximum drain to source voltage rating. The MOSFETs used
in the power stage of the converter should have a maximum VDS
rating that exceeds the sum of the upper voltage tolerance of the
input power source and the voltage spike that occurs when the
MOSFETs switch.
There are several power MOSFETs readily available that are
optimized for DC/DC converter applications. The preferred highside MOSFET emphasizes low gate charge so that the device
spends the least amount of time dissipating power in the linear
region. The preferred low-side MOSFET emphasizes low r DS(on)
when fully saturated to minimize conduction loss.
For the low-side MOSFET, (LS), the power loss can be assumed to
be conductive only and is written as Equation 45:
2
P CON_LS ≈ I LOAD ⋅ r DS ( ON )_LS ⋅ ( 1 – D )
(EQ. 45)
For the high-side MOSFET, (HS), its conduction loss is written as
Equation 46:
2
P CON_HS = I LOAD ⋅ r DS ( ON )_HS ⋅ D
(EQ. 46)
(EQ. 44)
FN6899.1
December 2, 2013
ISL95870, ISL95870A, ISL95870B
For the high-side MOSFET, its switching loss is written as
Equation 47:
V IN ⋅ I VALLEY ⋅ t ON ⋅ F
V IN ⋅ I PEAK ⋅ t OFF ⋅ F
SW
SW
P SW_HS = ---------------------------------------------------------------------- + -----------------------------------------------------------------2
2
(EQ. 47)
Where:
- IVALLEY is the difference of the DC component of the
inductor current minus 1/2 of the inductor ripple current
- IPEAK is the sum of the DC component of the inductor
current plus 1/2 of the inductor ripple current
- tON is the time required to drive the device into saturation
- tOFF is the time required to drive the device into cut-off
Layout Considerations
As a general rule, power layers should be close together, either
on the top or bottom of the board, with the weak analog or logic
signal layers on the opposite side of the board. The ground-plane
layer should be adjacent to the signal layer to provide shielding.
The ground plane layer should have an island located under the
IC, the components connected to analog or logic signals. The
island should be connected to the rest of the ground plane layer
at one quiet point.
There are two sets of components in a DC/DC converter, the
power components and the small signal components. The power
components are the most critical because they switch large
amount of energy. The small signal components connect to
sensitive nodes or supply critical bypassing current and signal
coupling.
The power components should be placed first and these include
MOSFETs, input and output capacitors, and the inductor. Keeping
the distance between the power train and the control IC short
helps keep the gate drive traces short. These drive signals
include the LGATE, UGATE, PGND, PHASE and BOOT.
VIAS TO
GROUND
PLANE
GND
VOUT
INDUCTOR
HIGH-SIDE
MOSFETS
PHASE
NODE
VIN
VCC AND PVCC PINS
Place the decoupling capacitors as close as practical to the IC. In
particular, the PVCC decoupling capacitor should have a very
short and wide connection to the PGND pin. The VCC decoupling
capacitor should be referenced to GND pin.
EN, PGOOD, VID0, VID1, AND FSEL PINS
These are logic signals that are referenced to the GND pin. Treat
as a typical logic signal.
OCSET AND VO PINS
The current-sensing network consisting of ROCSET, RO, and CSEN
needs to be connected to the inductor pads for accurate
measurement of the DCR voltage drop. These components
however, should be located physically close to the OCSET and VO
pins with traces leading back to the inductor. It is critical that the
traces are shielded by the ground plane layer all the way to the
inductor pads. The procedure is the same for resistive current
sense.
FB, SREF, SET0, SET1, SET2, AND RTN PINS
The input impedance of these pins is high, making it critical to
place the components connected to these pins as close as
possible to the IC.
LGATE, PGND, UGATE, BOOT, AND PHASE PINS
The signals going through these traces are high dv/dt and high
di/dt, with high peak charging and discharging current. The
PGND pin can only flow current from the gate-source charge of
the low-side MOSFETs when LGATE goes low. Ideally, route the
trace from the LGATE pin in parallel with the trace from the PGND
pin, route the trace from the UGATE pin in parallel with the trace
from the PHASE pin. In order to have more accurate zero-crossing
detection of inductor current, it is recommended to connect
Phase pin to the drain of the low-side MOSFETs with Kelvin
connection. These pairs of traces should be short, wide, and
away from other traces with high input impedance; weak signal
traces should not be in proximity with these traces on any layer.
OUTPUT
CAPACITORS
SCHOTTKY
DIODE
LOW-SIDE
MOSFETS
INPUT
CAPACITORS
FIGURE 21. TYPICAL POWER COMPONENT PLACEMENT
When placing MOSFETs, try to keep the source of the upper
MOSFETs and the drain of the lower MOSFETs as close as
thermally possible. See Figure 21. Input high frequency
capacitors should be placed close to the drain of the upper
MOSFETs and the source of the lower MOSFETs. Place the output
inductor and output capacitors between the MOSFETs and the
load. High frequency output decoupling capacitors (ceramic)
should be placed as close as possible to the decoupling target,
making use of the shortest connection paths to any internal
planes. Place the components in such a way that the area under
the IC has less noise traces with high dV/dt and di/dt, such as
gate signals and phase node signals.
24
FN6899.1
December 2, 2013
ISL95870, ISL95870A, ISL95870B
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
CHANGE
December 2, 2013
FN6899.1
Updated to new datasheet template.
Updated “Package Outline Drawing” on page 28 (L20.3x4). Added Note 6 callout to top and bottom views
in Pin 1 index area. Corrected Note 4 from "Dimension b applies to..." to "Dimension applies to..."
December 22, 2009
FN6899.0
Initial Release
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal
computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting
www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at
http://www.intersil.com/en/support/qualandreliability.html#reliability
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
25
FN6899.1
December 2, 2013
ISL95870, ISL95870A, ISL95870B
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
D
6
INDEX AREA
2X
A
L16.2.6x1.8A
B
N
16 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC
PACKAGE
MILLIMETERS
E
SYMBOL
0.10 C
1 2
2X
0.10 C
TOP VIEW
C
A
SEATING PLANE
SIDE VIEW
e
PIN #1 ID
K
1 2
NX L
L1
NX b 5
16X
0.10 M C A B
0.05 M C
(DATUM B)
(DATUM A)
BOTTOM VIEW
MAX
NOTES
A
0.45
0.50
0.55
-
-
-
0.05
-
0.127 REF
-
b
0.15
0.20
0.25
5
D
2.55
2.60
2.65
-
E
1.75
1.80
1.85
-
e
A1
NOMINAL
A1
A3
0.10 C
0.05 C
MIN
0.40 BSC
-
K
0.15
-
-
-
L
0.35
0.40
0.45
-
L1
0.45
0.50
0.55
-
N
16
2
Nd
4
3
Ne
4
3
θ
0
-
12
4
Rev. 5 2/09
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
4. All dimensions are in millimeters. Angles are in degrees.
CL
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
(A1)
NX (b)
L
5
e
SECTION "C-C"
TERMINAL TIP
C C
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
8. Maximum allowable burrs is 0.076mm in all directions.
9. JEDEC Reference MO-255.
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
3.00
1.80
1.40
1.40
2.20
0.90
0.40
0.20
0.50
0.20
0.40
10 LAND PATTERN
26
FN6899.1
December 2, 2013
ISL95870, ISL95870A, ISL95870B
Package Outline Drawing
L20.3.2x1.8
20 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE (UTQFN)
Rev 0, 5/08
1.80
A
6
PIN #1 ID
16X 0.40
B
20
6
PIN 1 ID#
1
19
2
3.20
0.50±0.10
(4X)
0.10
9
12
11
10
VIEW “A-A”
TOP VIEW
0.10 M C A B
0.05 M C
4 20X 0.20
19X 0.40 ± 0.10
BOTTOM VIEW
( 1.0 )
(1 x 0.70)
SEE DETAIL "X"
0.10 C
MAX 0.55
C
BASE PLANE
( 2. 30 )
SEATING PLANE
0.05 C
SIDE VIEW
( 16 X 0 . 40 )
C
0 . 2 REF
5
( 20X 0 . 20 )
0 . 00 MIN.
0 . 05 MAX.
( 19X 0 . 60 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
27
FN6899.1
December 2, 2013
ISL95870, ISL95870A, ISL95870B
Package Outline Drawing
L20.3x4
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 3/10
3.00
0.10 M C A B
0.05 M C
A
B
4
20X 0.25
16X 0.50
+0.05
-0.07
17
A
16
6
PIN 1
INDEX AREA
6
PIN 1 INDEX AREA
(C 0.40)
20
1
4.00
2.65
11
+0.10
-0.15
6
0.15 (4X)
A
10
7
VIEW "A-A"
1.65
TOP VIEW
+0.10
-0.15
20x 0.40±0.10
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
C
0.9± 0.10
SEATING PLANE
0.08 C
SIDE VIEW
(16 x 0.50)
(2.65)
(3.80)
(20 x 0.25)
C
(20 x 0.60)
0.2 REF
5
0.00 MIN.
0.05 MAX.
(1.65)
(2.80)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
28
FN6899.1
December 2, 2013