N ESIG D W R NE D FO EL7536 E D ME N 1 OR COM EL753Technical E R Brief NOT SE E Using the EL7551 Demo Board S ® September 19, 2001 TB422 This demo board is operated at about 500kHz switching frequency. The input voltage is from 4.5V to 5.5V. This document outlines the design consideration and lists the bill of materials and the layout. Please also refer to the advanced data sheet of EL7551 for detailed applications of the features. The EL7551 is a Buck (Step Down) DC:DC controller with integrated synchronous MOSFETs in a 16-pin QSOP package. With very few external components, a 1A step-down DC:DC converter can be very easily built, resulting in saved board space (<0.5in2), minimal design effort, and improved design time. EL7551 Demo Board Circuit Schematic C3 C4 R3 1 SGND PGND 16 2 COSC VREF 15 C5 R2 FB 14 3 VDD 4 PGND VDRV 13 5 PGND LX 12 6 VIN LX 11 7 VIN VHI 10 8 EN PGND 9 R1 L1 C1 C2 VIN VO C7 C6 EL7551 EL7551 Demo Board Bill of Material VIN = 5V, VOUT = 3.3V REFERENCE DESIGNATION VALUE MANUFACTURER MANUFACTURER’S PHONE NUMBER PART NUMBER C1 10µF Panasonic 408-945-5660 ECJ-3YBOJ106K C2, C3, C5, C6 0.1µF, 0603 Any C4 270pF, 5%, 0603 Any C7 47µF Sprague 207-324-4140 293D476X00100D2W L1 10µH Coilcraft 847-639-6400 D01813P-103HC R1 1kΩ, 0603 Any R2 2370Ω, 0603 Any R3 39.2Ω, 0603 Any 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2004. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners. Technical Brief 422 Design Considerations Choosing the Component Values The following requirements are specified for a DC:DC converter: • Input voltage range: VIN = 4.5V-5.5V • Output voltage: VO = 3.3V 4. Output capacitor C7. ∆VO and ∆IL normally decide C7 value. ∆VO requires ESR of C7 be less than: ∆V O ESR = --------------------- = 136mΩ ∆I LMAX Double-check the RMS current requirement of the output capacitor: • Max output voltage ripple: ∆VO = 50mV • Output max current: IO = 1A ∆I LMAX ∆I C7 = -------------------12 The following steps briefly outline the steps to choose components. For a detailed design discussion, please refer to Elantec Application #18 “Designing a High Efficiency DC:DC Converter with the EL75XX.” 1. Choose the feedback resister divider. The output voltage is decided by: R V O = 0.975 × 1 + ------2- R 1 2. Choose the converter switching frequency FS. FS, inductor L1, output capacitor C7, and EL7551’s switching loss are closely related. many iterations (or thermal measurements) may be required before a final value can be decided. Please refer to the EL7551 data sheet for the FS vs COSC curve. 3. Inductor L1. The EL7551 is internally ramp-compensated. For optimal operation, the inductor current ripple should be less than 0.5A. If ∆IL = 0.5A, then: ( 1 – D ) × VO L = --------------------------------∆I L × F S which is 0.11A. For a capacitor or combination of capacitors with 136mΩ parallel ESR, it is more than enough to handle this current. 5. Input capacitor C1. If all the AC current is handled by the input capacitor C1, its RMS current is calculated as: I IN,rms = [ D × ( 1 – D ) ] × IO This gives almost 0.5A when D = DMAX. Therefore a cap with 0.5A current handling capability should be chosen. However, in case some other capacitor is sharing current with it, C1’s current requirement can be reduced. Layout Considerations The layout is very important for the converter to function properly. Power Ground ( ) and Signal Ground ( ) should be separated to ensure that the high pulse current in the Power Ground never interferes with the sensitive signals connected to Signal Ground. They should only be connected at one point (normally at the negative side of either the input or output capacitor.) The trace connected to pin 14 (FB) is the most sensitive trace. It needs to be as short as possible and in a “quiet” place, preferably between the PGND and SGND traces. In addition, the bypass capacitor C3 should be as close to pins 1 and 3 as possible. where: VO D = --------V IN Choosing L1 = 10µH yields ∆ILMAX = 0.26A and ∆ILMIN = 0.18A. L1 should also be able to handle DC current of 1A and peak current of 1.2A at temperature range. 2 The heat of the chip is mainly dissipated through the PGND pins. Maximizing the copper area around these pins is preferable. In addition, a solid ground plane is always helpful for the EMI performance. Technical Brief 422 Demo Board Layout 0.5 inch 1 inch FIGURE 1. TOP LAYER 0.5 inch 1 inch FIGURE 2. TOP SILKSCREEN 3 Technical Brief 422 Demo Board Layout (Continued) 0.5 inch 1 inch FIGURE 3. BOTTOM LAYER 0.5 inch 1 inch FIGURE 4. BOTTOM SILKSCREEN Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 4