D N EW ® ESIG Using the EL7563 Demo Board NS F OR DED 554 N E M EL7 COM SEE Technical Brief E R NOT May 5, 2003 Introduction voltages is set to 1.8V. This document outlines the design consideration and lists the bill of materials and the layout (Gerber files are available upon request). Please also refer to the advanced data sheet of EL7563 for detailed applications of the features. The EL7563 is a full featured Buck (Step Down) DC:DC controller with integrated synchronous MOSFETs. With very few external components, a 4A step-down DC:DC converter can be very easily built, resulting in saved board space, minimal design effort, and improved design time. If a low current 5V is available, the voltage doubler circuitry (D2, D3, D4, C9) can be eliminated, resulting in Figures 3 and 4. The 5V VDRV current is typically 2.5mA, 5mA worst case. This demo board is operated at about 350kHz switching frequency. The input voltages are 3V-3.6V and output C5 0.1µF C4 390pF R4 PSHR C2 C3 22Ω 0.22µF C1a 330µF 2.2nF 1 VREF EN 20 2 SGND FB 19 3 COSC PG 18 4 VDD 5 VTJ VHI 16 6 PGND LX 15 7 PGND LX 14 8 VIN VIN (3.3V) EN PG D2 D4 VDRV 17 C1b 0.1µF TB408 PGND 13 STP 9 STP PGND 12 STN 10 STN PGND 11 C8 D3 C6 D1 0.22µF 0.22µF C9 0.1µF L1 4.7µH VOUT C7 330µF R2 820Ω C10 (NOTE) 2.2nF R1 1kΩ EL7563CM NOTE: Recommended for VOUT ≥ 2.5V FIGURE 1. EL7563CM DEMO BOARD CIRCUIT SCHEMATIC (VIN = 3.3V) 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners. Technical Brief 408 \ C5 1 VREF EN 28 2 SGND FB 27 3 COSC PG 26 0.1µF C4 22Ω C3 0.22µF C2 C1b 0.1µF D3 VHI 24 5 VTJ C1a 330µF D4 VDRV 25 4 VS 2.2nF VIN 3.3V D2 390pF R4 6 PGND LX 23 C6 0.22µF 7 PGND LX 22 L1 8 PGND LX 21 4.7µH 9 PGND LX 20 10 VIN LX 19 11 VIN LX 18 12 NC NC 17 13 STP PGND 16 14 STN PGND 15 D1 C8 0.22µF C9 0.1µF C10 2.2nF C7 330µF VOUT 1.8V 4A R2 820Ω R1 1kΩ EL7563CRE FIGURE 2. EL7563CRE DEMO BOARD CIRCUIT SCHEMATIC C5 0.1µF C4 390pF R4 PSHR C2 C3 22Ω 0.22µF 2.2nF C1a C1b 330µF 0.1µF 1 VREF EN 20 2 SGND FB 19 3 COSC PG 18 4 VDD VDRV 17 5 VTJ VHI 16 6 PGND LX 15 7 PGND LX 14 8 VIN PGND 13 STP 9 STP PGND 12 STN 10 STN PGND 11 VIN (3.3V) EN PG C8 0.22µF C6 D1 0.22µF L1 4.7µH VOUT C7 330µF EL7563CM NOTE: Recommended for VOUT ≥ 2.5V FIGURE 3. EL7563CM CIRCUIT SCHEMATIC WITH A SEPARATE VDRV 2 VDRV (4.5V - 6.5V) R2 820Ω R1 1kΩ C10 (NOTE) 2.2nF Technical Brief 408 C5 1 VREF EN 28 2 SGND FB 27 3 COSC PG 26 0.1µF C4 390pF R4 22Ω 4 VS C3 0.22µF VDRV 25 C2 5 VTJ VHI 24 2.2nF VIN 3.3V C1a 330µF C1b 0.1µF C8 0.22µF D1 6 PGND LX 23 C6 0.22µF 7 PGND LX 22 L1 8 PGND LX 21 4.7µH 9 PGND LX 20 10 VIN LX 19 11 VIN LX 18 12 NC NC 17 13 STP PGND 16 14 STN PGND 15 C10 2.2nF C7 330µF VDRV (4.5V - 6.5V) VOUT 1.8V 4A R2 820Ω R1 1kΩ EL7563CRE FIGURE 4. EL7563CRE CIRCUIT SCHEMATIC WITH A SEPARATE VDRV EL7563 Demo Board Bill of Material VIN = 3.3V, VOUT = 1.8V COMPONENT LABEL VALUE MANUFACTURER MANUFACTURER’S PHONE NUMBER PART NUMBER Capacitor C1a 330µF Sprague 207-324-4140 293D337X96R3 Capacitor C1b 0.1µF Any Capacitor C2, C10 (Note) 2.2nF Any Capacitor C3, C6, C8 0.22µF Any Capacitor C4 390pF Any Capacitor C5 0.1µF Any Capacitor C7 330µF Sprague 207-324-4140 293D337X96R3 Capacitor C9 0.1µF Any Diode D1 Telefunken 1-800-554-5565 BAT42W Diode D2, D3, D4 Telefunken 1-800-554-5565 BAT54S Inductor L1 Coilcraft 847-639-6400 DO3316P-472 Dale 605-665-9301 IDC-5020 4.7µF 4.7µH Resistor R1 1kΩ, 1% Any Resistor R2 820Ω, 1% Any Resistor R4 22.1Ω Any NOTE: Recommended for VOUT ≥ 2.5V. 3 Technical Brief 408 Design Considerations Choosing the Component Values The following requirements are specified for a DC:DC converter: Input voltage range: VIN = 3V-3.6V 4. Output capacitor C7. ∆VO and ∆IL normally decide C7 value. ∆VO requires ESR of C7 be less than: ∆V O ESR = --------------------- = 94mΩ ∆I LMAX Double-check the RMS current requirement of the output capacitor: Output voltage: VO = 1.8V Max output voltage ripple: ∆VO = 50mV Output max current: IO = 4A The following steps briefly outline the steps to choose components. For a detailed design discussion, please refer to Elantec Application #18 “Designing a High Efficiency DC:DC Converter with the EL75XX.” 1. Choose the feedback resistor divider. The output voltage is decided by: ∆I LMAX ∆I C7 = -------------------12 which is 0.15A. For a capacitor or combination of capacitors with 94mΩ parallel ESR, it is more than enough to handle this current. 5. Input capacitor C1a. If all the AC current is handled by the input capacitor C1a, its RMS current is calculated as: I INRMS = R V O = 0.992 × 1 + ------2- R 1 ( D × ( 1 – D ) ) × IO This gives 2A when D = DMIN. Therefore a cap with 2A current handling capability should be chosen. However, in case some other capacitor is sharing current with it, C1a’s current requirement can be reduced. Layout Considerations If R1 is chosen to be 1kΩ, then: R 2 = 814Ω Choose R2 = 820Ω 2. Choose the converter switching frequency FS. The layout is very important for the converter to function properly. Power Ground ( ) and Signal Ground ( ) should be separated to ensure that the high pulse current in the Power Ground never interferes with the sensitive signals connected to Signal Ground. They should only be connected at one point (normally at the negative side of either the input or output capacitor.) FS, inductor L1, output capacitor C7, and EL7563’s switching loss are closely related. Many iterations (or thermal measurements) may be required before a final value can be decided. The trace connected to FB pin is the most sensitive trace. It needs to be as short as possible and in a “quiet” place, preferably between PGND or SGND traces. Please refer the FS vs COSC curve to find C4. For 350kHz FS, a 390pF should be chosen. In addition, the bypass capacitor C3 should be as close to pins 2 and 4 as possible. 3. Inductor L1. The EL7563 is internally ramp-compensated. For optimal operation, the inductor current ripple should be less than 0.8A. If ∆IL = 0.8A, then: The heat of the chip is mainly dissipated through the PGND pins. Maximizing the copper area around these pins is preferable. In addition, a solid ground plane is always helpful for the EMI performance. Performance ( I – D ) × VO L = ------------------------------- = 3.2µH ∆I L × F S The performance curves and waveforms of this demo board are shown on the following pages, when the junction temperature of EL7563 is determined by: where: 1.2 – VTJ T J = 75 + ------------------------0.00384 VO D = --------V IN Choosing L1 = 4.7µH yields ∆ILMAX = 0.53 and ∆ILMIN = 0.43A. L1 should also be able to handle DC current of 4A and peak current of 4.4A at temperature range. 4 Technical Brief 408 Typical Performance Curves VIN=3.3V 100 96 94 VO=1.8V EFFICIENCY (%) EFFICIENCY (%) VIN=3V VO=2.5V 95 90 85 VO=1.2V 80 75 70 0.5 1 1.5 2 2.5 VIN=3.3V 92 90 VIN=3.6V 88 86 VO=1V 0 VO=2.5V 3 3.5 84 4 0 0.5 FIGURE 5. EL7563CM EFFICIENCY vs IO VIN=3.3V 2.505 VO=1.8V VO=1.2V 1.2 1 0.8 VO=1V 0.6 0.4 VO=2.5V 3.5 4 VIN=3.6V 2.495 VIN=3.3V 2.49 2.485 VIN=3V 2.48 2.475 0 0.5 1 1.5 2 2.5 3 3.5 2.465 0.5 4 OUTPUT CURRENT IO (A) 1.5 2 2.5 3 3.5 4 FIGURE 8. EL7563CM LOAD REGULATION 1.27 1000 900 1.268 800 1.266 FS (kHz) 700 1.264 1.262 600 500 400 1.26 300 1.258 1.256 -50 1 LOAD CURRENT IO (A) FIGURE 7. EL7563CM CONVERTER POWER LOSS vs IO VREF (V) 3 2.47 0.2 0 2.5 VO=2.5V 2.5 OUTPUT VOLTAGE (V) POWER LOSS (W) 1.4 2 1.5 FIGURE 6. EL7563CM EFFICIENCY vs IO 1.8 1.6 1 LOAD CURRENT IO (A) LOAD CURRENT IO (A) 200 -10 30 70 110 150 JUNCTION TEMPERATURE (°C) FIGURE 9. VREF vs JUNCTION TEMPERATURE 5 100 100 200 300 400 500 600 700 800 900 1000 COSC (pF) FIGURE 10. SWITCHING FREQUENCY vs COSC Technical Brief 408 Typical Performance Curves (Continued) 50 THERMAL RESISTANCE (°C/W) 1.5 VPSHR 1.3 1.1 0.9 0 50 25 75 100 125 46 WITH NO AIRFLOW 42 38 WITH 100 LFPM AIRFLOW 34 30 150 TEST CONDITION: CHIP IN THE CENTER OF COPPER AREA 1 OZ. COPPER PCB USED 1 2 1.5 3 2.5 3.5 4 PCB COPPER HEAT-SINKING AREA (in2) JUNCTION TEMPERATURE (°C) FIGURE 12. EL7563CM θJA vs COPPER AREA FIGURE 11. VTJ vs JUNCTION TEMPERATURE 95 50 NO AIRFLOW 40 100 LFM 30 20 200 LFM 10 0 EFFICIENCY (%) JUNCTION TEMPERATURE RISE (°C) VIN=3.3V 100 60 500 LPF 0 1 2 3 VO=2.5V 90 85 VO=1.8V 80 VO=1.2V 75 70 65 60 0.1 4 0.6 1.1 1.6 IO (A) FIGURE 13. EL7563CM JUNCTION TEMPERATURE RISE ON DEMO BOARD 0.6 1.4 3.1 3.6 4 VO=2.5V 0.4 VO=2.5V 1.2 1 0.8 VO=1.2V 0.6 VIN=3.3V 0.2 VO (V) (%) PLOSS (W) 2.6 FIGURE 14. EL7563CRE EFFICIENCY 1.6 VIN=3.6V 0 -0.2 -0.4 0.4 VIN=3V -0.6 0.2 0 2.1 IO (A) 0 1 2 3 4 IO (A) FIGURE 15. EL7563CRE TOTAL CONVERTER POWER LOSS 6 -0.8 0 0.5 1 1.5 2 2.5 3 3.5 IO (A) FIGURE 16. EL7563CRE LOAD REGULATION 4 Technical Brief 408 Typical Performance Curves (Continued) 50 CONDITION: EL7563CRE THERMAL PAD SOLDERED TO 2-LAYER PCB WITH 0.039” THICKNESS AND 1 OZ. COPPER ON BOTH SIDES 45 40 35 30 40 TJ RISE θJA (°C/W) 45 35 25 20 15 10 30 5 25 0 1.5 2 2.5 3 3.5 4 0 1 PCB AREA (in2) FIGURE 17. EL7563CRE THERMAL RESISTANCE vs PCB AREA - NO AIR FLOW 1.5 2 2.5 3 3.5 FIGURE 18. EL7563CRE JUNCTION TEMPERATURE RISE ON DEMO BOARD - NO AIR FLOW Demo Board Waveforms VIN=3.3V, VO=1.8V, IO=0.2A-4A VIN=3.3V, VO=1.8V, IO=4A ∆VIN VLX IO iL ∆VO ∆VO FIGURE 19. SWITCHING WAVEFORMS FIGURE 20. TRANSIENT RESPONSE VIN=3.3V, VO=1.8V, IO=2A VIN=3.3V, VO=1.8V, IO=4A VIN VIN VO VO FIGURE 21. POWER-UP 7 4 IO (A) FIGURE 22. POWER-DOWN Technical Brief 408 Demo Board Waveforms (Continued) VIN=3.3V, VO=1.8V AT 4A VIN=3.3V, VO=1.8V AT 4A EN EN VO VO FIGURE 23. ENABLE FIGURE 24. DISABLE VIN=3.3V, VO=1.8V, IO=4A TO SHORT IO VO FIGURE 25. SHORT-CIRCUIT PROTECTION Demo Board Layout (EL7563CM) 1000 mil 2000 mil FIGURE 26. TOP LAYER 8 Technical Brief 408 Demo Board Layout (EL7563CM) (Continued) 1000 mil 2000 mil FIGURE 27. TOP SILKSCREEN 1000 mil 2000 mil FIGURE 28. BOTTOM LAYER 1000 mil 2000 mil FIGURE 29. BOTTOM SILKSCREEN 9 Technical Brief 408 Demo Board Layout (EL7563CRE) 2 in 2 in 2 in 2 in FIGURE 30. TOP LAYER FIGURE 31. TOP SILKSCREEN 2 in 2 in FIGURE 32. BOTTOM LAYER 2 in 2 in FIGURE 33. BOTTOM SILKSCREEN All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10