INTERSIL TB423

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Using the EL7562 Demo Board
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COM SEETechnical
Brief
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NOT
June 20, 2002
TB423
There are 2 demo boards, one for nominal 5V input and
another for 3.3V input. This document outlines the design
consideration and lists the bill of materials and the layout.
Please also refer to the advanced data sheet of EL7562 for
detailed applications of the features.
The EL7562 is a Buck (Step Down)
DC:DC controller with integrated
synchronous MOSFETs in a 16-pin
QSOP package. With very few external components, a 2A
step-down DC:DC converter can be very easily built,
resulting in saved board space (0.5in2), minimal design
effort, and improved design time.
EL7562 Demo Board Circuit Schematic for VIN = 5V Application
R 

V O = 0.985 ×  1 + ------2-
R 1

C3
C4
1 SGND
PGND 16
2 COSC
VREF 15
C5
R3
R2
FB 14
3 VDD
C1
C2
VIN
4 PGND
VDRV 13
5 PGND
LX 12
6 VIN
LX 11
7 VIN
VHI 10
8 EN
PGND 9
R1
L1
VO
C7
C6
EL7562
EL7562 Demo Board Bill of Material
VIN = 5V, VOUT = 3.3V
REFERENCE
DESIGNATION
VALUE
MANUFACTURER
MANUFACTURER’S
PHONE NUMBER
PART NUMBER
C1
100µF
Sprague
207-324-4140
293D107X0010D2
C2, C3, C5, C6
0.1µF, 0603
Any
C4
270pF, 5%, 0603
Any
C7
100µF
Sprague
207-324-4140
293D107X0010D2
L1
4.7µH
Coilcraft
847-639-6400
D01813472HC
R1
1kΩ, 0603
Any
R2
2370Ω, 0603
Any
R3
39Ω, 0603
Any
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Technical Brief 423
EL7562 Demo Board Circuit Schematic for VIN = 3.3V Application
R 

V O = 0.975 ×  1 + ------2-
R 1

C3
C4
0.1µF
270pF
1 SGND
PGND 16
2 COSC
VREF 15
C5
0.1µF
R3
FB 14
3 VDD
39Ω
C1
C2
100µF
0.1µF
VIN
(3V-3.6V)
4 PGND
VDRV 13
5 PGND
LX 12
D2
D3
D4
C8
0.1µF
C9
0.1µF
VO
(2.5V, 2A)
L1
LX 11
6 VIN
7 VIN
VHI 10
8 EN
PGND 9
EL7562 Demo Board Bill of Material
C6
C7
4.7µF
0.1µF
100µF
R2
1.54kΩ
R1
1kΩ
VIN = 3.3V, VOUT = 2.5V
REFERENCE
DESIGNATION
VALUE
MANUFACTURER
MANUFACTURER’S
PHONE NUMBER
PART NUMBER
C1
100µF
Sprague
207-324-4140
293D107X0010D2
C2, C3, C5, C6, C8, C9
0.1µF, 0603
Any
C4
270pF, 5%, 0603
Any
C7
100µF
Sprague
207-324-4140
293D107X0010D2
L1
4.7µH
Coilcraft
847-639-6400
D01813472HC
R1
1kΩ, 0603
Any
R2
1.54kΩ, 0603
Any
R3
39Ω, 0603
Any
D2, D3/4
Bat54S
Vishay Telefunken
402-563-6863
Bat54S
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Technical Brief 423
Design Considerations
Choosing the Component Values
The following requirements are specified for a DC:DC
converter:
• Input voltage range: VIN = 4.5V-5.5V
• Output voltage: VO = 3.3V
4. Output capacitor C7.
∆VO and ∆IL normally decide C7 value. ∆VO requires
ESR of C7 be less than:
∆V O
ESR = --------------------- = 89mΩ
∆I LMAX
Double-check the RMS current requirement of the output
capacitor:
• Max output voltage ripple: ∆VO = 50mV
• Output max current: IO = 2A
∆I LMAX
∆I C7 = -------------------12
The following steps briefly outline the steps to choose
components.
1. Choose the feedback resister divider.
The output voltage is decided by:
R 

V OUT = 0.985 ×  1 + ------2-
R 1

which is 0.16A. For a capacitor or combination of
capacitors with 89mΩ parallel ESR, it is more than
enough to handle this current.
For VIN = 5V
5. Input capacitors C1 and C2.
R 

V OUT = 0.975 ×  1 + ------2-
R 1

If all the AC current is handled by the input capacitors its
RMS current is calculated as:
For VIN = 3.3V
2. Choose the converter switching frequency FS.
FS, inductor L1, output capacitor C7, and EL7562’s
switching loss are closely related. many iterations (or
thermal measurements) may be required before a final
value can be decided.
Please refer to the EL7562 data sheet for the FS vs
COSC curve.
3. Inductor L1.
The EL7562 is internally ramp-compensated. For
optimal operation, the inductor current ripple should be
less than 0.6A.
If ∆IL = 0.5A, then:
( 1 – D ) × VO
L = --------------------------------∆I L × F S
I IN,rms =
[ D × ( 1 – D ) ] × IO
This gives almost 0.99A when D = DMAX. Therefore a
cap with 0.99A current handling capability should be
chosen. However, in case some other capacitor is
sharing current with it, this current requirement can be
reduced.
Layout Considerations
The layout is very important for the converter to function
properly. Power Ground ( ) and Signal Ground ( ) should
be separated to ensure that the high pulse current in the
Power Ground never interferes with the sensitive signals
connected to Signal Ground. They should only be connected
at one point (normally at the negative side of either the input
or output capacitor.)
The trace connected to pin 14 (FB) is the most sensitive
trace. It needs to be as short as possible and in a “quiet”
place, preferably between the PGND and SGND traces.
where:
VO
D = --------V IN
Choosing L1 = 4.7µH yields ∆ILMAX = 0.56A. L1 should
also be able to handle DC current of 2A and peak
current of 2.3A at temperature range.
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In addition, the bypass capacitor C3 should be as close to
pins 1 and 3 as possible.
The heat of the chip is mainly dissipated through the PGND
pins. Maximizing the copper area around these pins is
preferable. In addition, a solid ground plane is always helpful
for the EMI performance.
Technical Brief 423
Demo Board Layout for VIN = 5V
0.5”
1”
FIGURE 1. TOP LAYER
0.5”
1”
FIGURE 2. TOP SILKSCREEN
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Technical Brief 423
Demo Board Layout for VIN = 5V
(Continued)
0.5”
1”
FIGURE 3. BOTTOM LAYER
0.5”
1”
FIGURE 4. BOTTOM SILKSCREEN
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Technical Brief 423
Demo Board Layout for VIN = 3.3V
0.6”
1.2”
FIGURE 5. TOP LAYER
0.6”
1.2”
FIGURE 6. TOP SILKSCREEN
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Technical Brief 423
Demo Board Layout for VIN = 3.3V
(Continued)
0.6”
1.2”
FIGURE 7. BOTTOM LAYER
0.6”
1.2”
FIGURE 8. BOTTOM SILKSCREEN
Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to
verify that the Application Note or Technical Brief is current before proceeding.
For information regarding Intersil Corporation and its products, see www.intersil.com
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