INTERSIL ISL8540

ISL8540
®
Data Sheet
September 9, 2008
DC/DC Power Switching Regulator
Features
The ISL8540 is a step down DC/DC power switching
regulator which accepts 9.0V to 40V input and provides a 2A
output current. The output voltage can be set in the range
between 1.21V and 35V by means of an external divider.
The device uses an internal power DMOS transistor with a
typical rDS(ON) of 0.19Ω to obtain very high efficiency and
high switching speed. A switching frequency in the range of
100kHz to 600kHz can be realized (the maximum power
dissipation of the various packages must be observed).
Notable features of this next generation of DC/DC converter
include pulse-by-pulse current limit for FET protection,
hiccup mode for short circuit protection, voltage feedforward
regulation, Frequency SYNC, soft-start, low standby current
of 60µA typical in the disabled state, and thermal shut-down.
The device is available in a 20 Ld HTSSOP package.
• Voltage feedforward mode
Ordering Information
• Load dump to 100V for 400ms
PART
NUMBER
(Note)
ISL8540IVEZ
PART
MARKING
TEMP.
RANGE
(°C)
FN6495.5
• Step down DC/DC supporting up to 2A
• Input voltage range of 9.0V to 40V
• Internal reference of 1.21V ±1%
• Adjustable output voltage range of 1.21V to 35V
• Adjustable switching frequency 100kHz to 600kHz
• Frequency SYNC pin
• Zero load current operation
• Pulse-by-pulse mode current limit and Hiccup mode
• Low standby current of 60µA typical
• Thermal shut-down
• Pb-free (RoHS compliant)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL85 40IVEZ -40 to +85 20 Ld HTSSOP MDP0048
Applications
• Non-isolated telecom power supply
ISL8540IVEZ-T* ISL85 40IVEZ -40 to +85 20 Ld HTSSOP MDP0048
• Industrial and automotive power supplies
*Please refer to TB347 for details on reel specifications.
• Portable computers
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach materials,
and 100% matte tin plate plus anneal (e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at Pb-free
peak reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020.
• Battery chargers
• Distributed power systems
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Pinout
ISL8540
(20 LD HTSSOP)
TOP VIEW
VIN 1
19 VIN
LX 3
18 LX
LX 4
17 LX
BOOT 5
16 SS
EN 6
15 PGND
VCC5 7
14 PGOOD
SYNC 8
13 REF
RTCT 9
12 COMP
SGND 10
1
20 VIN
VIN 2
11 FB
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL8540
Absolute Maximum Ratings
Thermal Information
Input Voltage VIN . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to 42V
Voltage at BOOT pin . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to 49V
LX, RTCT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to 42V
REF, FB, SS, EN, SYNC, PGOOD pins. . . . . . . . . . . . . . . . . . . . .8V
VCC5* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to 5.5V
Thermal Resistance (Typical, Notes 1, 2) θJA (°C/W) θJC (°C/W)
HTSSOP Package . . . . . . . . . . . . . . . .
40
2.5
Maximum Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3W
Maximum Junction Temperature (Hermetic Package or Die) . . +150°C
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Junction Temperature Range. . . . . . . . . . . . . . . . . .-40°C to +125°C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . 9.0V to 40V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
*An accidental short between VCC5 and GND may cause excessive heating and permanent damage to the device.
NOTES:
1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
3. Additional heatsinking may be required to insure that junction temperature do not exceed above +125°C.
Electrical Specifications
Unless otherwise specified the specifications listed in the table are tested at TA = +25°C and guard band for the
full Temperature Range, VIN = 24V, VOUT = 5.0V, IOUT = 0A. Typical values are at TA = +25°C. Parameters
with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits
established by characterization and are not production tested.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
9.0
24
40
V
VIN = 9V, EN = HIGH
35
60
µA
VIN = 40V, EN = HIGH
60
110
µA
VIN = 9V, VFB = 1.5V
3.6
4
mA
VIN = 40V, VFB = 1.5V
6.0
8.0
mA
5.0
5.1
V
5
mA
8.9
V
0.55
V
VIN - 5
V
VIN SUPPLY
Input Voltage Range
VIN SUPPLY CURRENT
Shut-down Current
IDD
Operating Current
IDD
VCC5 SUPPLY (A 1µF capacitor is needed from VCC5 to GND)
VCC5 Output Voltage
VIN = 9.0V to 40V, IL = 0mA to 5mA
Maximum Output Current
VIN = 24V
4.9
INPUT UV
Rising UV Threshold
7.8
UV Threshold Hysteresis
0.18
0.3
BUCK CONVERTER
Output Voltage (Note 3)
IOUT = 2A
1.2
Maximum Duty Cycle
F = 300kHz
90
Minimum Controllable ON Time
96
%
F = 300kHz
150
ns
Over the VIN range with frequency set by
external resistor and capacitor at RTCT
±10
%
OSCILLATOR
Total Variation on Set Frequency
Frequency Range (Set by RTCT)
fOSC
100
600
kHz
SYNC Range
fOSC
100
600
kHz
2
FN6495.5
September 9, 2008
ISL8540
Electrical Specifications
Unless otherwise specified the specifications listed in the table are tested at TA = +25°C and guard band for the
full Temperature Range, VIN = 24V, VOUT = 5.0V, IOUT = 0A. Typical values are at TA = +25°C. Parameters
with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits
established by characterization and are not production tested. (Continued)
PARAMETER
SYMBOL
Oscillation Frequency
fOSC
ΔVOSC
Max Ramp Amplitude
Modulator Gain
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VIN = 9V to 40V, RT = 100kΩ, CT = 1200pF
60
kHz
VIN = 9V to 40V, RT = 27.4kΩ, CT = 220pF
725
kHz
1
VP
9
-
VIN = 9V
VVIN/ΔVOSC
Min OFF Time
150
300
ns
REFERENCE AND SOFT-START
Internal Reference Voltage
VREF
Soft-Start Current
Soft-Start Threshold
1.21
ISS
8
VSOFT
1.0
gm
3.9
10
V
12
µA
V
ERROR AMPLIFIER
Transconductance
Gain-Bandwidth Product
Slew Rate
COMP Pin Drive
5.7
7.2
ms
GBW
15
MHz
SR
6
V/µs
ICOMP
±200
µA
Internal Feedback Voltage
VFB
TA = -40°C to +85°C, VIN = 9.0V to 40V
Internal Feedback Bias Current
IFB
TA = -40°C to +85°C, VFB = 1.20V
1.194
1.210
1.222
V
±50
±100
nA
OVERCURRENT PROTECTION
Dynamic Current Limit ON Time
tOCON
16
Clock
pulses
Dynamic Current Limit OFF Time
tOCOFF
4
SS cycle
Switch Current Limit
ILIMIT
TA = +25°C
3.2
VPG-
Fraction of the VOUT set point; ~3µs noise filter
VPG+
Fraction of the VOUT set point; ~3µs noise filter
4.0
4.8
A
85
89
%
111
115
%
VPULLUP = 5.5V
1
µA
IPGOOD = 4mA
0.5
V
0.355
Ω
POWER-GOOD (OPEN DRAIN)
Power-Good Lower Threshold
PGOOD Leakage Current
IPGLKG
PGOOD Voltage Low
MOSFET
Switch ON-Resistance
rDS(ON)
IOUT = 2A, VBOOT = VIN + 5.0V, Tested at wafer
level
0.19
EN
Input HIGH Level (Asserted)
VINHIGH
Input LOW Level (Unasserted)
VINLOW
Input Current HIGH
IENHIGH
Input Current LOW
IENLOW
2.6
V
1.2
V
VIN = 24V
25
µA
VIN = 24V
25
µA
SYNC
Input HIGH Level (Asserted)
VINHIGH
Input LOW Level (Unasserted)
VINLOW
1.2
V
Input Current HIGH
ISYNCHIGH
0.2
µA
Input Current LOW
ISYNCLOW
0.2
µA
3
2.6
V
FN6495.5
September 9, 2008
ISL8540
Electrical Specifications
Unless otherwise specified the specifications listed in the table are tested at TA = +25°C and guard band for the
full Temperature Range, VIN = 24V, VOUT = 5.0V, IOUT = 0A. Typical values are at TA = +25°C. Parameters
with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits
established by characterization and are not production tested. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
THERMAL SHUT-DOWN
Thermal Shut-down Temperature
Rising Threshold
Thermal Shut-down Hysteresis
Pin Descriptions
150
°C
15
°C
RTCT (Pin 9)
VIN (Pins 1, 2, 19, 20)
The input supply for the PWM regulator power stage.
Connected to DRAIN of the high side MOSFET.
LX (Pins 3, 4, 17, 18)
There are four output pins that must be connected together
externally in normal operation.
BOOT (Pin 5)
A capacitor is connected from this pin to the output pin. An
internal 10V supply and an internal Schottky diode provide
the high side voltage to drive the gate of the internal DMOS
device.
EN (Pin 6)
The EN input will disable the part and shut-down all function
when it is held high or left OPEN. The EN current will be
10µA typical. An internal pull-up resistor will hold the pin
high. When EN = Low, the part is enabled. Connect to GND
for auto start-up.
A resistor to VIN and a capacitor to GND determine the
frequency of the saw-tooth oscillator. Resistor range is
R = 20k to 100k. Capacitor range is C = 470pF to 1.2nF. The
oscillator amplitude will vary from approximately 0.9V to 10V
as VIN changes from 8.5V to 40V to maintain constant
frequency and provide feed forward. The oscillator will have
a fixed off time, which will establish the maximum on time for
the regulator. This off time will be <200ns. The maximum
duty cycle for a 500kHz system will therefore be
approximately 90%, as the frequency of the maximum duty
cycle will increase (95% for 250kHz system). The minimum
duty cycle is zero.
SGND (Pin 10)
The SGND terminal of the ISL8540 provides the return path
for the control and monitor portions of the IC.
FB (Pin 11)
This is the feedback pin. The feedback ratio is set by an
external resistor divider connected to the load.
COMP (Pin 12)
VCC5 (Pin 7)
VCC5 is the +5.0V output pin which provides an output of an
internal supply for supply filtering purposes. A 1µF capacitor
should be connected from this pin to GND. Internal VDD
supply is set at 5.0V (not planned that the user would use
this supply).
This pin is connected to the output of the Error Amplifier and
is used to compensate the loop. The Error Amplifier is a GM
amplifier.
REF (Pin 13)
1.20V reference output. Bypass to GND with 1µF capacitor.
SYNC (Pin 8)
PGOOD (Pin 14)
This pin provides a digital input pin to synchronize the
internal oscillator to an external signal. When the sync
function is not used, this pin can be left open or tied to GND.
If the sync function is used, the RTCT timing must be set to a
frequency lower than the sync input frequency. The
termination of the ramp is synchronized with the rising edge
of the sync input signal. There are no duty cycle restrictions
on the input sync signal. Input thresholds are TTL
compatible.
This pin is an open drain output that is turned on when the
feedback voltage is more than ±10% from the reference
voltage, indicating that the output is not within 10% of set
point.
PGND (Pin 15)
This pins are used as the ground connection of the power
train.
SS (Pin 16)
A capacitor is connected from this pin to GND to determine
the soft-start timing. The soft-start pin internal charging
current is 10µA.
4
FN6495.5
September 9, 2008
ISL8540
REF
SS
CO M P
RTCT
SYNC
VCC5
BO O T
SO FTSTART
RAM P
G EN
O SC
LDO
+
BANDG AP
1.21V
FB
+
EN
EAM P
+
PW M
CO M P
3pF
OVFLT
1.6k
VIN
PW M
LOG IC
CONTRO LLER
PRO TECTIO N
DRIVER
LX
PG ND
+14%
+
UVFLT
O CFLT
+
+
CSA
-14%
PG O O D
3µs
DELAY
SG ND
FIGURE 1. BLOCK DIAGRAM OF THE ISL8540
5
FN6495.5
September 9, 2008
ISL8540
VIN 9V TO 40V
C9 + C4
150µF
0.1µF
PGND
VIN
VIN
VIN
VIN
LX
LX
LX
BOOT
C3
1µF
R1
20k
C1
470pF
L1
15µH
LX
D1
B260
ISL8540
EN
VIN
C1
0.1µF
OUTPUT
5V
C8
470µF
PGND
VCC5
PGOOD
SYNC
REF
RTCT
COMP
SGND
FB
C7
100pF
+
R2
51.1k
R6
5.62k
C10
100pF
C11
1µF
R5
100k
VCC5
SS
R4
301k
C5
0.1µF
C6
390pF
R3
16.2k
FIGURE 2. TYPICAL SCHEMATIC FOR ISL8540 (5V VOUT)
VIN
VIN
VIN
VIN
LX
LX
VIN 18V TO 40V
C9
150µF
+
C4
0.1µF
PGND
LX
BOOT
C3
1µF
R1
20k
C1
470pF
L1
22µH
LX
D1
B260
ISL8540
EN
VIN
C1
0.1µF
C8
470µF
PGND
VCC5
PGOOD
SYNC
REF
RTCT
COMP
SGND
FB
OUTPUT
12V
+
R2
51.1k
C7
330pF
R6
5.62k
C10
100pF
C11
1µF
R5
100k
VCC5
SS
R4
390k
C6
820pF
C5
0.1µF
R3
5.62k
FIGURE 3. TYPICAL SCHEMATIC FOR ISL8540 (12V VOUT)
6
FN6495.5
September 9, 2008
ISL8540
Typical Performance Curves
Circuit of Figure 2, VIN = 24V, EN = 0V, FS = 500KHz, VOUT = 5V, unless otherwise noted.
Typical values are at TA = +25°C.
100
2.5V VOUT
90
100
5V VOUT
3.3V VOUT
90
5V VOUT
80
EFFICIENCY (%)
EFFICIENCY (%)
80
12V VOUT
70
60
50
1.8V VOUT
1.2V VOUT
40
70
60
50
2.5V VOUT
40
30
30
20
0.0
0.5
1.0
1.5
20
0.0
2.0
0.5
90
EFFICIENCY (%)
70
60
2.5V VOUT
50
1.8V VOUT
3.3V VOUT
5V VOUT
3.29
36V VIN
3.26
0.5
1.0
1.5
3.20
0.0
2.0
0.5
OUTPUT LOAD (A)
5.05
12.2
OUTPUT VOLTAGE (V)
12.3
5.00
24V VIN
4.95
4.90
1.5
2.0
2.5
FIGURE 7. VOUT REGULATION vs LOAD
(VOUT = 3.3V - 500kHz)
5.10
12V VIN
1.0
OUTPUT LOAD (A)
FIGURE 6. EFFICIENCY vs LOAD (36V INPUT - 500kHz)
OUTPUT VOLTAGE (V)
12V VIN
24V VIN
3.32
3.23
30
36V VIN
4.85
4.80
0.0
2.0
3.35
12V VOUT
80
20
0.0
1.5
3.38
24V VOUT
40
1.0
OUTPUT LOAD (A)
FIGURE 5. EFFICIENCY vs LOAD (24V INPUT - 500kHz)
OUTPUT VOLTAGE (V)
100
1.2V VOUT
3.3V VOUT
OUTPUT LOAD (A)
FIGURE 4. EFFICIENCY vs LOAD (12V INPUT - 500kHz)
1.8V VOUT
12.1
24V VIN
12.0
36V VIN
11.9
11.8
0.5
1.0
1.5
OUTPUT LOAD (A)
FIGURE 8. VOUT REGULATION vs LOAD
(VOUT = 5V - 500kHz)
7
2.0
2.5
11.7
0.0
0.5
1.0
1.5
2.0
2.5
OUTPUT LOAD (A)
FIGURE 9. VOUT REGULATION vs LOAD
(VOUT = 12V - 500kHz)
FN6495.5
September 9, 2008
ISL8540
Typical Performance Curves
Circuit of Figure 2, VIN = 24V, EN = 0V, FS = 500KHz, VOUT = 5V, unless otherwise noted.
Typical values are at TA = +25°C. (Continued)
24.4
3.4
3.4
36V VIN
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
24.3
24.2
24.1
24.0
23.9
3.3
3.3
1A LOAD
3.3
3.2
23.8
0.0
0.5
1.0
1.5
3.2
2.0
5
10
15
5.10
12.3
5.05
12.2
5.00
IOUT = 1A
4.95
IOUT = 2A
4.90
12.1
IOUT = 0A
35
40
IOUT = 1A
12.0
IOUT = 2A
11.9
5
10
15
20
25
30
35
11.7
40
5
10
15
20
25
30
35
40
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
FIGURE 12. OUTPUT VOLTAGE REGULATION vs VIN
(VOUT = 5V - 500kHz)
FIGURE 13. OUTPUT VOLTAGE REGULATION vs VIN
(VOUT = 5V - 500kHz)
24.75
POWER DISSIPATION (W)
3.0
24.50
OUTPUT VOLTAGE (V)
30
11.8
4.85
IOUT = 1A
IOUT = 0A
24.25
24.00
23.75
23.50
2.5
36V VIN
2.0
1.5
1.0
24V VIN
0.5
IOUT = 2A
23.25
25
FIGURE 11. OUTPUT VOLTAGE REGULATION vs VIN PWM
MODE
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
FIGURE 10. VOUT REGULATION vs LOAD
(VOUT = 24V - 500kHz)
IOUT = 0A
20
INPUT VOLTAGE (V)
OUTPUT LOAD (A)
4.80
NO LOAD
2A LOAD
5
10
15
20
25
30
35
INPUT VOLTAGE (V)
FIGURE 14. OUTPUT VOLTAGE REGULATION vs VIN
(VOUT = 5V - 500kHz)
8
40
0.0
0.0
12V VIN
0.5
1.0
OUTPUT LOAD (A)
1.5
2.0
FIGURE 15. POWER DISSIPATION vs LOAD
(VOUT = 3.3V - 500kHz)
FN6495.5
September 9, 2008
ISL8540
Typical Performance Curves
Circuit of Figure 2, VIN = 24V, EN = 0V, FS = 500KHz, VOUT = 5V, unless otherwise noted.
Typical values are at TA = +25°C. (Continued)
3.0
POWER DISSIPATION (W)
POWER DISSIPATION (W)
3.0
2.5
36V VIN
2.0
1.5
1.0
24V VIN
0.5
0.0
0.0
2.5
36V VIN
2.0
1.5
1.0
24V VIN
0.5
12V VIN
0.5
1.0
1.5
2.0
0.0
0.0
0.5
OUTPUT LOAD (A)
1.0
1.5
2.0
OUTPUT LOAD (A)
FIGURE 16. POWER DISSIPATION vs LOAD
(VOUT = 5V - 500kHz)
FIGURE 17. POWER DISSIPATION vs LOAD
(VOUT = 12V - 500kHz)
LX = 10V/DIV
POWER DISSIPATION (W)
3.0
2.5
36V VIN
2.0
VOUT RIPPLE = 50mV/DIV
IL = 0.2A/DIV
1.5
RTCT = 2V/DIV
1.0
0.5
0.0
0.0
0.5
1.0
1.5
2.0
OUTPUT LOAD (A)
FIGURE 18. POWER DISSIPATION vs LOAD
(VOUT = 24V - 500kHz)
FIGURE 19. STEADY STATE OPERATION AT NO LOAD
LX = 10V/DIV
VOUT RIPPLE = 50mV/DIV
LX = 10V/DIV
IL = 1A/DIV
VOUT RIPPLE = 50mV/DIV
RTCT = 2V/DIV
IL = 1A/DIV
FIGURE 20. STEADY STATE OPERATION WITH FULL LOAD
9
FIGURE 21. LOAD TRANSIENT
FN6495.5
September 9, 2008
ISL8540
Typical Performance Curves
Circuit of Figure 2, VIN = 24V, EN = 0V, FS = 500KHz, VOUT = 5V, unless otherwise noted.
Typical values are at TA = +25°C. (Continued)
EN = 5V/DIV
VOUT = 2V/DIV
EN = 5V/DIV
PRE-BIASED WITH 4V
VOUT = 1V/DIV
SS = 2V/DIV
SS = 2V/DIV
IL = 0.5A/DIV
IL = 0.5A/DIV
FIGURE 22. SOFT-START AT NO LOAD
FIGURE 23. SOFT-START WITH PRE-BIASED
EN = 5V/DIV
VOUT = 2V/DIV
LX = 10V/DIV
IL = 1A/DIV
IL = 2A/DIV
SS = 2V/DIV
VOUT = 2V/DIV
PGOOD = 5V/DIV
FIGURE 24. SOFT-START AT FULL LOAD
FIGURE 25. OUTPUT SHORT CIRCUIT
LX = 10V/DIV
VOUT = 2V/DIV
IL = 2A/DIV
PGOOD = 5V/DIV
FIGURE 26. OUTPUT SHORT CIRCUIT
10
FN6495.5
September 9, 2008
ISL8540
Applications Information
and a capacitor from RTCT to GND are used to program the
switching frequency through Equation 2.
Product Description
The ISL8540 is a non-synchronous, integrated FET 2A step
down regulator which operates from an unregulated input of
9V to 40V. The output voltage is user-adjustable with a pair
of external resistors. Frequency of operation is adjustable
from 100kHz to 600kHz set by RTCT. An external signal with
higher frequency can be injected to SYNCH to synchronize
the controller.
The buck controller drives an internal N-Channel MOSFET
and requires an external diode to deliver load current up to
2A. A Schottky diode is recommended for improved
efficiency and performance over a standard diode. The
converter output is regulated down to 1.21V from an input
source. These features make the ISL8540 ideally suited for
telecommunication power applications.
The PWM control loop uses a single output voltage loop with
input voltage feed forward which simplifies feedback loop
compensation and rejects input voltage variation. External
feedback loop compensation allows flexibility in output filter
component selection.
6.25
1000
C 1 [ nF ] = ----------------- ⎛ ------------------------------ – 0.3⎞
⎠
R [ kΩ ] ⎝ f OSC [ kHz ]
(EQ. 2)
Caution: When the ISL8540 is in disabled state, the voltage
across RTCT pin will reach VIN voltage. Make sure that the
voltage rating of the RTCT capacitor is rated as high as the
input voltage.
Output Voltage Selection
The output voltage of the regulator can be programmed via
an external resistor divider that is used to scale the output
voltage relative to the internal reference voltage and feed it
back to the inverting input of the error amplifier. Refer to
Figure 28.
The output voltage programming resistor, R3, will depend on
the value chosen for the feedback resistor and the desired
output voltage of the regulator. The value for the feedback
resistor is typically between 1kΩ and 10kΩ.
R 2 × 1.21V
R 3 = ------------------------------------V OUT – 1.21V
(EQ. 3)
The buck regulator is equipped with a lossless current limit
scheme. The current limit in the buck regulator is achieved
by monitoring the drain-to-source current of the internal
switching power MOSFET. The current limit threshold is
internally set at 4.5A peak. Additional features include
programmable soft-start to support proper start-up of wide
output capacitance range.
If the output voltage desired is 1.21V, then R3 is left
unpopulated.
Start-Up and Shut-Down
Overcurrent Protection
When the EN pin is connected to a logic high, the ISL8540 is
in the shut-down mode. All the control circuitry and both
MOSFETs are off, and VOUT falls to zero. In this mode, the
total input current is less than 110µA.
The overcurrent function protects the switching converter from
a shorted output by monitoring the current flowing through the
upper MOSFETs.
When the EN pin is tied to GND, and VIN reaches
approximately 9V, the regulator begins to switch. The output
voltage is gradually increased to ensure proper soft-start
operation.
When the EN reaches logic LOW, the regulator repeats the
start-up procedure, including the soft-start function. Connect
a capacitor from SS pin to ground. This capacitor, along with
an internal 10µA current source sets the soft-start interval of
the converter, tSS.
C SS [ μF ] ≈ 8.3 ⋅ t SS [ s ]
(EQ. 1)
Operating Frequency
The ISL8540 can operate at switching frequencies from
100kHz to 600kHz. A resistor tied from the RTCT pin to VIN
Fault Protection
The ISL8540 monitors the output of the regulator for
overcurrent and undervoltage events. The ISL8540 also
provides protection from excessive junction temperatures.
Upon detection of overcurrent condition, the upper MOSFET
will be immediately turned off and will not be turned on again
until the next switching cycle. Upon detection of the initial
overcurrent condition, the overcurrent fault counter is set to
1 and the overcurrent condition flag is set from LOW to
HIGH. If, on the subsequent cycle, another overcurrent
condition is detected, the OC fault counter will be
incremented. If there are 16 sequential OC fault detections,
the regulator will be shut down under an overcurrent fault
condition. An overcurrent fault condition will result with the
regulator attempting to restart in a hiccup mode with the
delay between restarts being 4 soft-start periods. At the end
of the fourth soft-start wait period, the fault counters are
reset and soft-start is attempted again. If the overcurrent
condition goes away prior to the OC fault counter reaching a
count of four, the overcurrent condition flag will set back to
LOW.
If the overcurrent condition flag is HIGH and the overcurrent
fault counter is less than four and an undervoltage event is
detected, the regulator will be shut down immediately.
11
FN6495.5
September 9, 2008
ISL8540
Undervoltage Protection
If the voltage detected on the FB pin falls 14% below the
internal reference voltage and the overcurrent condition flag
is LOW, then the regulator will be shut down immediately
under an undervoltage fault condition. An undervoltage fault
condition will result with the regulator attempting to restart in
a hiccup mode with the delay between restarts being 4
soft-start periods. At the end of the fourth soft-start wait
period, the fault counters are reset and soft-start is
attempted again.
During the removal of the same output load, the energy
stored in the inductor is dumped into the output capacitors.
This energy dumping creates a temporary hump in the
output voltage. This hump, as with the sag, can be attributed
to the total amount of capacitance on the output. Figure 27
shows a typical response to a load transient.
ΔVHUMP
VOUT
Thermal Protection
If the ISL8540 IC junction temperature reaches a nominal
temperature of +150°C, the regulator will be disabled. The
ISL8540 will not re-enable the regulator until the junction
temperature drops below +135°C.
ΔVESR
ΔVSAG
ΔVESL
Output Capacitor Selection
An output capacitor is required to filter the inductor current
and supply the load transient current. The filtering
requirements are a function of the switching frequency and
the ripple current. The load transient requirements are a
function of the slew rate (di/dt) and the magnitude of the
transient load current. These requirements are generally met
with a mix of capacitors and careful layout.
High frequency capacitors initially supply the transient and
slow the current load rate seen by the bulk capacitors. The
bulk filter capacitor values are generally determined by the
ESR (Effective Series Resistance) and voltage rating
requirements rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
The shape of the output voltage waveform during a load
transient that represents the worst case loading conditions
will ultimately determine the number of output capacitors and
their type. When this load transient is applied to the
converter, most of the energy required by the load is initially
delivered from the output capacitors. This is due to the finite
amount of time required for the inductor current to slew up to
the level of the output current required by the load. This
phenomenon results in a temporary dip in the output voltage.
At the very edge of the transient, the Equivalent Series
Inductance (ESL) of each capacitor induces a spike that
adds on top of the existing voltage drop due to the
Equivalent Series Resistance (ESR).
After the initial spike, attributable to the ESR and ESL of the
capacitors, the output voltage experiences sag. This sag is a
direct consequence of the amount of capacitance on the
output.
12
IOUT
Itran
FIGURE 27. TYPICAL TRANSIENT RESPONSE
The amplitudes of the different types of voltage excursions
can be approximated by using the formulas in Equation 4:
dI tran
ΔV ESL = ESL • --------------dt
ΔV ESR = ESR • I tran
2
L out • I tran
ΔV SAG = -------------------------------------------------C out • ( V in – V out )
2
L out • I tran
ΔV HUMP = -------------------------------C out • V out
(EQ. 4)
where
Itran = Output Load Current Transient
Cout = Total Output Capacitance
In a typical converter design, the ESR of the output capacitor
bank dominates the transient response. The ESR and the
ESL are typically the major contributing factors in
determining the output capacitance. The number of output
capacitors can be determined by using Equation 5, which
relates the ESR and ESL of the capacitors to the transient
load step and the voltage limit (ΔVO):
ESL • dI tran
--------------------------------+ ESR • I tran
dt
Number of Caps = ----------------------------------------------------------------------ΔV o
(EQ. 5)
If ΔVSAG and/or ΔVHUMP are found to be too large for the
output voltage limits, then the amount of capacitance may need
to be increased. In this situation, a trade-off between output
inductance and output capacitance may be necessary.
FN6495.5
September 9, 2008
ISL8540
The ESL of the capacitors, which is an important parameter
in Equations 4 and 5, is not usually listed in databooks.
Practically, it can be approximated if an impedance vs
frequency curve is given for a specific capacitor (C):
1
ESL = ---------------------------------------2
C ( 2 • π • f res )
(EQ. 6)
where fres is the frequency where the lowest impedance
is achieved (resonant frequency).
The ESL of the capacitors becomes a concern when
designing circuits that supply power to loads with high rates
of change in the current.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by Equation 7:
ΔI =
VIN - VOUT
Fs x L
x
VOUT
VIN
ΔVOUT = ΔI x ESR
(EQ. 7)
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient. Use ΔI of
approximately 30% of IOUT is a good compromise.
One of the parameters limiting the converter’s response to
a load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL8540 will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
The response time to a transient is different for the
application of load and the removal of load. Equation 8 gives
the approximate response time interval for application and
removal of a transient load:
tRISE =
L x ITRAN
VIN - VOUT
tFALL =
L x ITRAN
(EQ. 8)
VOUT
where: ITRAN is the transient load current step, tRISE is the
response time to the application of load, and tFALL is the
response time to the removal of load. The worst case
response time can be either at the application or removal of
load. Be sure to check both of these equations at the
minimum and maximum output levels for the worst case
response time.
13
Rectifier Selection
Current circulates from ground to the junction of the
MOSFET and the inductor when the high-side switch is off.
As a consequence, the polarity of the switching node is
negative with respect to ground. This voltage is
approximately -0.5V (a Schottky diode drop) during the off
time. The rectifier's rated reverse breakdown voltage must
be at least equal to the maximum input voltage, preferably
with a 20% derating factor. The power dissipation is:
V OUT⎞
⎛
P D [ W ] = I OUT ⋅ V D ⋅ ⎜ 1 – ----------------⎟
V IN ⎠
⎝
(EQ. 9)
where VD is the voltage of the Schottky diode = 0.5V to 0.7V
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the VIN’s pin. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time the upper MOSFET
turns on. Place the small ceramic capacitors physically close
to the VIN and PGND pins.
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. Their voltage rating should be
at least 1.25 times greater than the maximum input voltage,
while a voltage rating of 1.5 times is a conservative
guideline. For most cases, the RMS current rating
requirement for the input capacitor of a buck regulator is
approximately 1/2 the DC load current.
The maximum RMS current through the input capacitors
may be closely approximated through Equation 10:
2
V OUT ⎛
V OUT
2 ⎛
1 ⎛ V IN – V OUT V OUT⎞ ⎞
-------------- × ⎜ I OUT
× 1 – --------------⎞ + ------ × ⎜ ----------------------------- × --------------⎟ ⎟
⎝
V IN
V IN ⎠ 12 ⎝ L × f OSC
V IN ⎠ ⎠
MAX
⎝
(EQ. 10)
For a through hole design, several electrolytic capacitors
may be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised with
regard to the capacitor surge current rating. These
capacitors must be capable of handling the surge-current at
power-up. Some capacitor series available from reputable
manufacturers are surge current tested.
Feedback Compensation
Figure 28 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(VOUT) is regulated to the Reference voltage level. The error
amplifier output (VE/A) is compared with the oscillator (OSC)
triangular wave to provide a pulse-width modulated (PWM)
wave with an amplitude of VIN at the LX node. The PWM
wave is smoothed by the output filter (LO and CO).
FN6495.5
September 9, 2008
ISL8540
PWM
COMPARATOR
-
ΔVOSC
1. Pick Gain (R3gm/(R2+R3) for desired converter
bandwidth.
VIN
DRIVER
OSC
LO
LX
DRIVER
+
VOUT
3. Place 2ND Zero at Filter’s Double Pole.
CO
D
4. Place 1ST Pole at the ESR Zero.
ESR
(PARASITIC)
ZFB
5. Place 2ND Pole at Half the Switching Frequency.
6. Check Gain against Error transconductance’s OpenLoop Gain.
VE/A
ZIN
-
+
7. Estimate Phase Margin - Repeat if Necessary.
REFERENCE
ERROR
AMP
Compensation Break Frequency
Equations
DETAILED COMPENSATION COMPONENTS
ZFB
C10
VOUT
ZIN
C6
C7
R4
R6
R2
COMP
R3
ISL8540
REFERENCE
R ⎞
⎛
V OUT = 1.20 × ⎜ 1 + ------2-⎟
R 3⎠
⎝
FIGURE 28. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
The modulator transfer function is the small-signal transfer
function of VOUT/VE/A . This function is dominated by a DC
Gain and the output filter (LO and CO), with a double pole
break frequency at fLC and a zero at fESR . The DC Gain of
the modulator is simply the input voltage (VIN) divided by the
peak-to-peak oscillator voltage ΔVOSC . The ISL8540
incorporates a feed forward loop that accounts for changes in
the input voltage. This maintains a constant modulator gain.
Modulator Break Frequency Equations
1
f LC = ------------------------------------------2π x L O x C O
1
f Z1 = ---------------------------------------------------------( R4 ⋅ gm + 1 )
2π ⋅ ---------------------------------- ⋅ C 6
gm
1
f P1 = --------------------------2πR 6 ⋅ C 7
1
f Z2 = --------------------------2πR 2 ⋅ C 7
1
f P2 = ----------------------------2πR 4 ⋅ C 10
(EQ. 12)
Assumption: R6<<R2, R6<<R3, and C10<<C6.
FB
gm
+
2. Place 1ST Zero Below Filter’s Double Pole (~75% fLC).
Figure 29 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 29. Using the guidelines in “Modulator Break
Frequency Equations” on page 14 should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at FP2 with the capabilities of
the error amplifier. The Closed Loop Gain is constructed on
the graph of Figure 29 by adding the Modulator Gain (in dB) to
the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
The compensation gain uses external impedance networks
ZFB and ZIN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin.
100
1
f ESR = -------------------------------------------2π x ESR x C O
FZ1 FZ2
FP1
FP2
80
(EQ. 11)
OPEN LOOP
ERROR AMP GAIN
60
GAIN (dB)
The compensation network consists of the transconductance
amplifier (internal to the ISL8540) and the impedance
networks ZIN and ZFB. The goal of the compensation
network is to provide a closed loop transfer function with the
highest 0dB crossing frequency (f0dB) and adequate phase
margin. Phase margin is the difference between the closed
loop phase at f0dB and 180°. The equations in the following
section relate the compensation network’s poles, zeros and
gain to the components (R2, R3 , R4 , R6, C10 , C6, and C7) in
Figure 28. Use these guidelines for locating the poles and
zeros of the compensation network:
40
20
20LOG
(R4/R2)
20LOG
(VIN/ΔVOSC)
0
COMPENSATION
GAIN
MODULATOR
GAIN
-20
CLOSED LOOP
GAIN
-40
FLC
-60
10
100
1k
FESR
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 29. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
14
FN6495.5
September 9, 2008
ISL8540
A more detailed explanation of voltage mode control of a
buck regulator can be found in Tech Brief TB417, titled
“Designing Stable Compensation Networks for Single Phase
Voltage Mode Buck Regulators.”
Layout Considerations
Layout is very important in high frequency switching
converter design. With power devices switching efficiently
between 100kHz and 600kHz, the resulting current
transitions from one device to another cause voltage spikes
across the interconnecting impedances and parasitic circuit
elements. These voltage spikes can degrade efficiency,
radiate noise into the circuit, and lead to device overvoltage
stress. Careful component layout and printed circuit board
design minimizes these voltage spikes.
As an example, consider the turn-off transition of the control
MOSFET. Prior to turn-off, the MOSFET is carrying the full
load current. During turn-off, current stops flowing in the
MOSFET and is picked up by the freewheeling Schottky
diode. Any parasitic inductance in the switched current path
generates a large voltage spike during the switching interval.
Careful component selection, tight layout of the critical
components, and short, wide traces minimizes the
magnitude of voltage spikes.
There are two sets of critical components in the ISL8540
switching converter. The switching components are the most
critical because they switch large amounts of energy, and
therefore tend to generate large amounts of noise. Next are
the small signal components which connect to sensitive
nodes or supply critical bypass current and signal coupling.
A multi-layer printed circuit board is recommended.
Figure 30 shows the connections of the critical components
in the converter. Note that capacitors CIN and COUT could
each represent numerous physical capacitors. Dedicate one
solid layer, usually a middle layer of the PC board, for a
ground plane and make all critical component ground
connections with vias to this layer. Dedicate another solid
layer as a power plane and break this plane into smaller
islands of common voltage levels. Keep the metal runs from
the LX terminals to the output inductor short. The power
plane should support the input power and output power
nodes. Use copper filled polygons on the top and bottom
circuit layers for the LX nodes. Use the remaining printed
circuit layers for small signal wiring.
In order to dissipate heat generated by the internal LDO and
other power components, the ground pad at the bottom of
the device should be connected to the ground plane through
at least nine vias. This allows the heat to move away from
the IC and also ties the pad to the ground plane through a
low impedance path.
The switching components should be placed close to the
ISL8540 first. Minimize the length of the connections
between the input capacitors, CIN. Make the PGND and the
output capacitors as short as possible.
NOTE: It is recommended that any applications with input
voltage greater than 30VDC should be polymer coated to
meet Intersil’s IPC-2221 creepage and clearance
specification.
VIN
VIN
CIN
ISL8540
L
D
LOAD
CBP2
VOUT1
LX
VCC5
COUT1
COMP
C6
C10
R4
PGND
R2
FB
R3
C7
R6
GND PAD
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 30. PRINTED CIRCUIT BOARD POWER PLANES AND
ISLANDS
15
FN6495.5
September 9, 2008
ISL8540
HTSSOP (Heat-Sink TSSOP) Family
0.25 M C A B
D
MDP0048
A
HTSSOP (HEAT-SINK TSSOP) FAMILY
(N/2)+1
N
MILLIMETERS
SYMBOL 14 LD 20 LD 24 LD 28 LD 38 LD TOLERANCE
PIN #1 I.D.
E
E1
1
0.20 C B A
2X
N/2 LEAD TIPS
(N/2)
TOP VIEW
B
D1
EXPOSED
THERMAL PAD
E2
A
1.20
1.20
1.20
1.20
1.20
Max
A1
0.075
0.075
0.075
0.075
0.075
±0.075
A2
0.90
0.90
0.90
0.90
0.90
+0.15/-0.10
b
0.25
0.25
0.25
0.25
0.22
+0.05/-0.06
c
0.15
0.15
0.15
0.15
0.15
+0.05/-0.06
D
5.00
6.50
7.80
9.70
9.70
±0.10
D1
3.2
4.2
4.3
5.0
7.25
Reference
E
6.40
6.40
6.40
6.40
6.40
Basic
E1
4.40
4.40
4.40
4.40
4.40
±0.10
E2
3.0
3.0
3.0
3.0
3.0
Reference
e
0.65
0.65
0.65
0.65
0.50
Basic
L
0.60
0.60
0.60
0.60
0.60
±0.15
L1
1.00
1.00
1.00
1.00
1.00
Reference
N
14
20
24
28
38
Reference
BOTTOM VIEW
Rev. 3 2/07
NOTES:
0.05
e
C
H
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
SEATING
PLANE
0.10 M C A B
b
0.10 C
N LEADS
3. Dimensions “D” and “E1” are measured at Datum Plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
SIDE VIEW
SEE DETAIL “X”
c
END VIEW
L1
A A2
GAUGE
PLANE
0.25
L
A1
0° - 8°
DETAIL X
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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16
FN6495.5
September 9, 2008