HM-6516/883 TM 2K x 8 CMOS RAM March 1997 Features Description • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. The HM-6516/883 is a CMOS 2048 x 8 Static Random Access Memory. Extremely low power operation is achieved by the use of complementary MOS design techniques. This low power is further enhanced by the use of synchronous circuit techniques that keep the active (operating) power low, which also gives fast access times. The pinout of the HM6516/883 is the popular 24 pin, 8-bit wide JEDEC Standard which allows easy memory board layouts, flexible enough to accommodate a variety of PROMs, RAMS, EPROMs, and ROMs. • Low Power Standby. . . . . . . . . . . . . . . . . . . 275µW Max • Low Power Operation . . . . . . . . . . . . . .55mW/MHz Max • Fast Access Time . . . . . . . . . . . . . . . . . 120/200ns Max • Industry Standard Pinout • Single Supply . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0V VCC The HM-6516/883 is ideally suited for use in microprocessor based systems. The byte wide organization simplifies the memory array design, and keeps operating power down to a minimum because only one device is enabled at a time. The address latches allow very simple interfacing to recent generation microprocessors which employ a multiplexed address/data bus. The convenient output enable control also simplifies multiplexed bus interfacing by allowing the data outputs to be controlled independent of the chip enable. • TTL Compatible • Static Memory Cells • High Output Drive • On-Chip Address Latches • Easy Microprocessor Interfacing Ordering Information 120ns HM1-6516B/883 200ns TEMPERATURE RANGE PACKAGE -55oC to 125oC HM1-6516/883 HM4-6516B/883 -55oC to +125oC - PKG. NO. CERDIP F24.6 CLCC J32.A Pinouts DQ2 11 GND 12 14 DQ4 13 DQ3 NC NC NC DESCRIPTION No Connect 29 A8 A5 6 28 A9 A4 7 27 NC A3 8 26 W VSS/GND A2 9 25 G DQ0 - DQ7 Data In/Data Out A1 10 24 A10 A0 11 23 E NC 12 22 DQ7 DQ0 13 21 DQ6 A0 - A10 E Address Inputs Chip Enable/Power Down Ground VCC Power (+5V) W Write Enable G Output Enable 14 15 16 17 18 19 20 DQ5 16 DQ6 15 DQ5 VCC DQ0 9 DQ1 10 32 31 30 DQ4 18 E 17 DQ7 1 DQ3 A1 7 A0 8 NC 20 G 19 A10 NC A3 5 A2 6 2 NC 22 A9 21 W 3 DQ2 A5 3 A4 4 4 PIN A6 5 GND 24 VCC 23 A8 DQ1 A7 1 A6 2 NC HM-6516/883 (CLCC) TOP VIEW A7 HM-6516/883 (CERDIP) TOP VIEW CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved 173 FN2999.1 HM-6516/883 Functional Diagram A10 A9 A8 A7 A6 A5 A4 A 7 LATCHED ADDRESS REGISTER A GATED ROW DECODER 128 128 x 128 MATRIX 7 L 1 OF 8 G 16 16 16 16 16 16 16 16 G G GATED COLUMN DECODER 8 A 4 W E A 8 L 4 A A LATCHED ADDRESS REGISTER A3 A2 174 A1 A0 DQ0 THRU DQ7 HM-6516/883 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input or Output Voltage Applied for all Grades. . . . . . . GND -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance θJA θJC CERDIP Package . . . . . . . . . . . . . . . . 48oC/W 8oC/W CLCC Package . . . . . . . . . . . . . . . . . . 66oC/W 12oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25953 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.4V to VCC Data Retention Supply Voltage . . . . . . . . . . . . . . . . . . . 2.0V to 4.5V Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns Max TABLE 1. HM-6516/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested LIMITS PARAMETER SYMBOL (NOTE 1) CONDITIONS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 2.4 - V High Level Output Voltage VOH VCC = 4.5V IO = -1.0mA 1, 2, 3 -55oC ≤ TA ≤ +125oC Low Level Output Voltage VOL VCC = 4.5V IO = 3.2mA 1, 2, 3 -55oC ≤ TA ≤ +125oC - 0.4 V High Impedance Output Leakage Current IIOZ VCC = G = 5.5 V, VIO = GND or VCC 1, 2, 3 -55oC ≤ TA ≤ +125oC -1.0 1.0 µA VCC = 5.5V, VI = GND or VCC 1, 2, 3 -55oC ≤ TA ≤ +125oC -1.0 1.0 µA Input Leakage Current II Operating Supply Current ICCOP VCC = G = 5.5V, (Note 2) f = 1MHz, VI = GND or VCC 1, 2, 3 -55oC ≤ TA ≤ +125oC - 10 mA Standby Supply Current ICCSB1 VCC = 5.5V, HM-6516/883 E = VCC-0.3V, IO = 0mA, VI = GND or VCC 1, 2, 3 -55oC ≤ TA ≤ +125oC - 100 µA VCC = 5.5V, HM-6516B/883 E = VCC -0.3V, IO = 0mA, VI = GND or VCC 1, 2, 3 -55oC ≤ TA ≤ +125oC - 50 µA VCC = 2.0V, HM-6516/883 E = VCC-0.3V, IO = 0mA, VI = GND or VCC 1, 2, 3 -55oC ≤ TA ≤ +125oC - 50 µA VCC = 2.0V, HM-6516B/883 E = VCC-0.3V, IO = 0mA, VI = GND or VCC 1, 2, 3 -55oC ≤ TA ≤ +125oC - 25 µA 7, 8A, 8B -55oC ≤ TA ≤ +125oC - - - Data Retention Supply Current Functional Test ICCDR FT VCC = 4.5V (Note 3) NOTES: 1. All voltages referenced to device GND. 2. Typical derating 1.5mA/MHz increase in ICCOP. 3. Tested as follows: f = 2MHz, VIH = 2.4V, VIL = 0.4V, IOH = -4.0mA, IOL = 4.0mA, VOH ≥ 1.5V, and VOL ≤ 1.5V. 175 HM-6516/883 TABLE 2. HM-6514/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested LIMITS (NOTES 1, 2) PARAMETER SYMBOL CONDITIONS GROUP A SUBGROUPS TEMPERATURE MIN MAX MIN MAX UNITS - 120 - 200 ns HM-6516B/883 HM-6516/883 Chip Enable Access Time (1) TELQV VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ T A ≤ +125oC Address Access Time (2) TAVQV VCC = 4.5 and 5.5V, (Note 3) 9, 10, 11 -55oC ≤ T A ≤ +125oC - 120 - 200 ns Chip Enable Pulse Negative Width (9) TELEH VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ T A ≤ +125oC 120 - 200 - ns Chip Enable Pulse Positive Width (10) TEHEL VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ T A ≤ +125oC 50 - 80 - ns Address Set-up Time (11) TAVEL VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ T A ≤ +125oC 0 - 0 - ns Address Hold Time (12) TELAX VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ T A ≤ +125oC 30 - 50 - ns Write Enable Pulse Width (13) TWLWH VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ T A ≤ +125oC 120 - 200 - ns Write Enable Pulse Set-up Time (14) TWLEH VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ T A ≤ +125oC 120 - 200 - ns Chip Selection to End of Write (15) TELWH VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ T A ≤ +125oC 120 - 200 - ns Data Set-up Time (16) TDVWH VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ T A ≤ +125oC 50 - 80 - ns Data Hold Time (17) TWHDX VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ T A ≤ +125oC 10 - 10 - ns Read or Write Cycle Time (18) TELEL VCC = 4.5 and 5.5V 9, 10, 11 -55oC ≤ T A ≤ +125oC 170 - 280 - ns NOTES: 1. All voltages referenced to device GND. 2. Input pulse levels: 0.8V to VCC -2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF. 3. TAVQV = TELQV + TAVEL. 176 HM-6516/883 TABLE 3. HM-6516/883 ELECTRICAL PERFORMANCE SPECIFICATIONS LIMITS PARAMETER SYMBOL Input Capacitance CI Input/Output Capacitance CIO CONDITIONS NOTES TEMPERATURE MIN MAX UNITS = +25oC - 8 pF VCC = Open, f = 1MHz, All Measurements Referenced to Device Ground 1, 2 TA VCC = Open, f = 1MHz, All Measurements Referenced to Device Ground 1, 3 TA = +25oC - 12 pF VCC = Open, f = 1MHz, All Measurements Referenced to Device Ground 1, 2 TA = +25oC - 10 pF VCC = Open, f = 1MHz, All Measurements Referenced to Device Ground 1, 3 TA = +25oC - 14 pF Chip Enable to Output Valid Time (3) TELQX VCC = 4.5 and 5.5V 1 -55oC ≤ TA ≤ +125 oC 10 - ns Write Enable Output Disable Time (4) TWLQZ VCC = 4.5 and 5.5V HM-6516/883 1 -55oC ≤ TA ≤ +125 oC - 80 ns VCC = 4.5 and 5.5V HM-6516B/883 1 -55oC ≤ TA ≤ +125 oC - 50 ns VCC = 4.5 and 5.5V HM-6516/883 1 -55oC ≤ TA ≤ +125 oC - 80 ns VCC = 4.5 and 5.5V HM-6516B/883 1 -55oC ≤ TA ≤ +125 oC - 50 ns Chip Enable Output Disable Time (5) TEHQZ Output Enable Access Time (6) TGLQV VCC = 4.5 and 5.5V 1 -55oC ≤ TA ≤ +125 oC - 80 ns Output Enable to Output Valid Time (7) TGLQX VCC = 4.5 and 5.5V 1 -55oC ≤ TA ≤ +125 oC 10 - ns Output Disable Time (8) TGHQZ VCC = 4.5 and 5.5V HM-6516/883 1 -55oC ≤ TA ≤ +125 oC - 80 ns VCC = 4.5 and 5.5V HM-6516B/883 1 -55oC ≤ TA ≤ +125 oC - 50 ns NOTES: 1. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design release and upon design changes which would affect these characteristics. 2. Applies to LCC device types only. 3. Applies to DIP device types only. TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS METHOD SUBGROUPS Initial Test 100%/5004 - Interim Test 100%/5004 1, 7, 9 PDA 100%/5004 1 Final Test 100%/5004 2, 3, 8A, 8B, 10, 11 Group A Samples/5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Groups C & D Samples/5005 1, 7, 9 177 HM-6516/883 Timing Waveforms (2) TAVQV (12) TELAX (11) (11) TAVEL TAVEL A NEXT VALID ADD ADD (18) TELEL (10) TEHEL (9) TELEH (10) TEHEL E HIGH W (5) TEHQZ (5) TEHQZ (1) TELQV (5) TELQX DQ VALID DATA OUT TGHQZ (6) TGLQV (8) G (7) TGLQX TIME REFERENCE -1 0 1 2 3 4 5 FIGURE 1. READ CYCLE The address information is latched in the on-chip registers on the falling edge of E (T = 0), minimum address setup and hold time requirements must be met. After the required hold time, the addresses may change state without affecting device operation. During time (T = 1), the outputs become enabled but data is not valid until time (T = 2), W must remain high throughout (12) TELAX (11) TAVEL A the read cycle. After the data has been read, E may return high (T = 3). This will force the output buffers into a high impedance mode at time (T = 4). G is used to disable the output buffers when in a logical “1” state (T = -1, 0, 3, 4, 5). After (T = 4) time, the memory is ready for the next cycle. (11) TAVEL NEXT ADD VALID ADD (18) TELEL (10) TEHEL (9) TELEH (10) TEHEL E (14) TWLEH (13) TWLWH W (15) TELWH DQ G (17) TWHDX (16) TDVWH VALID DATA IN HIGH TIME REFERENCE -1 0 1 2 3 4 5 FIGURE 2. WRITE CYCLE The write cycle is initiated on the falling edge of E (T = 0), which latches the address information in the on-chip registers. If a write cycle is to be performed where the output is not to become active, G can be held high (inactive). TDVWH and TWHDX must be met for proper device operation regardless of G. If E and G fall before W falls (read mode), a possible bus conflict may exist. If E rises before W rises, reference data setup and hold times to the E rising edge. The write operation is terminated by the first rising edge of W (T = 2) or E (T = 3). After the minimum E high time (TEHEL), the next cycle may begin. If a series of consecutive write cycles are to be performed, the W line may be held low until all desired locations have been written. In this case, data setup and hold times must be referenced to the rising of E. 178 HM-6516/883 Test Circuit DUT (NOTE 1) CL + - IOH 1.5V IOL EQUIVALENT CIRCUIT NOTE: 1. Test head capacitance includes stray and jig capacitance. Burn-In Circuits HM-6516/883 CERDIP TOP VIEW HM-6516/883 CLCC TOP VIEW F10 VCC C VCC F2 DQ1 DQ2 4 21 5 20 6 19 7 18 8 17 W G A10 E DQ7 DQ6 9 16 10 15 DQ5 11 14 DQ4 12 13 DQ3 F9 F12 F8 F1 F7 F0 F6 F13 F5 F0 F4 F2 F3 F2 F2 F2 1 32 31 30 F2 NOTES: All resistors 47kΩ ±5%. F0 = 100kHz ±10%. VCC = 5.5V ±0.5V. VIH = 4.5V ±10%. VIL = -0.2V to +0.4V. C1 = 0.01µF Min. 179 A8 A6 5 A5 6 28 7 27 NC W 26 G 25 A10 24 E 23 DQ7 22 DQ6 21 A4 A3 A2 A1 A0 29 8 9 10 11 NC 12 DQ0 13 14 15 16 17 18 F2 NC 2 NC 3 VCC NC 4 NC F11 NC A9 F2 GND 22 19 20 DQ5 F2 DQ0 3 F2 F2 A0 A8 F2 F3 A1 23 DQ4 F4 A2 2 F2 F5 A3 VCC NC DQ3 F6 A4 24 GND F7 A5 1 F2 F8 A6 DQ2 F9 A7 DQ1 F10 A7 C A9 F11 F12 F1 F0 F13 F0 F2 F2 HM-6516/883 Die Characteristics DIE DIMENSIONS: 186.6 x 199.6 x 19 ±1mils GLASSIVATION: Type: SiO2 Thickness: 7kÅ ±9kÅ METALLIZATION: Type: Si - Al Thickness: 9kÅ - 13kÅ WORST CASE CURRENT DENSITY: 0.5 x 105 A/cm 2 Metallization Mask Layout HM-6516/883 A3 A4 A5 A6 A7 VCC A8 A9 W G A10 A2 A1 E A0 DQ0 DQ1 DQ2 GND DQ3 DQ4 DQ5 DQ6 DQ7 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 180