HM-6617/883 2K x 8 CMOS PROM June 2004 Features Description • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. The HM-6617/883 is a 16,384-bit fuse link CMOS PROM in a 2K word by 8-bit/word format with “Three-State” outputs. • Low Power Standby and Operating Power - ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100µA - ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA at 1MHz The HM-6617/883 utilizes a synchronous design technique. This includes on-chip address latches and a separate output enable control which makes this device ideal for applications utilizing recent generation microprocessors. This design technique, combined with the Intersil advanced self-aligned silicon gate CMOS process technology offers ultra-low standby current. Low ICCSB is ideal for battery applications or other systems with low power requirements. • Fast Access Time. . . . . . . . . . . . . . . . . . . . . . . . . . 120ns • Industry Standard Pinout • Single 5.0V Supply • CMOS/TTL Compatible Inputs • Separate Output Enable The Intersil NiCr fuse link technology is utilized on this and other Intersil CMOS PROMs. This gives the user a PROM with permanent, stable storage characteristics over the full industrial and military temperature voltage ranges. NiCr fuse technology combined with the low power characteristics of CMOS provides an excellent alternative to standard bipolar PROMs or NMOS EPROMs. • Operating Temperature Range . . . . . . -55oC to +125oC All bits are manufactured storing a logical “0” and can be • High Output Drive . . . . . . . . . . . . . . . . 12 LSTTL Loads • Synchronous Operation • On-Chip Address Latches Ordering Information PACKAGE TEMPERATURE RANGE 120ns -55oC to +125oC SBDIP PACKAGE NO. HM1-6617/883 D24.6 Pinout HM-6617/883 (SBDIP) TOP VIEW PIN DESCRIPTION PIN A7 1 A6 DESCRIPTION 2 24 VCC 23 A8 NC No Connect A5 3 22 A9 A0-A10 Address Inputs A4 4 21 P E Chip Enable A3 5 20 G A2 6 19 A10 Q Data Output A1 7 18 E VCC Power (+5V) A0 8 17 Q7 G Output Enable Q0 9 16 Q6 Q1 10 15 Q5 P (Note) Program Enable Q2 11 14 Q4 GND 12 13 Q3 NOTE: P should be hardwired to VCC except during programming. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 2001 1 FN3016.3 HM-6617/883 Functional Diagram MSB A10 A9 A8 A7 A6 A5 A4 A LATCHED ADDRESS REGISTER 7 GATED ROW DECODER Q0 128 x 128 MATRIX 128 A Q1 7 LSB Q2 L G Q3 16 16 16 16 16 16 16 16 GATED COLUMN DECODER AND DATA OUTPUT CONTROL G E 8 Q5 A A 4 Q4 4 Q6 G L ALL LINES POSITIVE LOGIC: LATCHED ADDRESS REGISTER ACTIVE HIGH THREE-STATE BUFFERS: A HIGH OUTPUT ACTIVE ADDRESS LATCHES AND GATED DECODERS: Q7 MSB LSB A3 LATCH ON FALLING EDGE OF E GATE ON FALLING EDGE OF G 2 A2 A1 A0 HM-6617/883 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V Typical Derating Factor . . . . . . . . . . . . 5mA/MHz Increase in ICCOP ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance θJA θJC SBDIP Package . . . . . . . . . . . . . . . . . . 48oC/W 9oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +175oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC Operating Conditions Die Characteristics Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.8V Input High Voltage . . . . . . . . . . . . . . . . . . . . . . +2.4V to VCC +0.3V Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5473 Gates CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TABLE 1. HM-6617/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested LIMITS PARAMETER SYMBOL (NOTES 1, 4) CONDITIONS High Level Output Voltage VOH1 VCC = 4.5V, IO = -2.0mA 1, 2, 3 -55oC ≤ TA ≤ +125oC 2.4 - V Low Level Output Voltage VOL VCC = 4.5V, IO = +4.8mA 1, 2, 3 -55oC ≤ TA ≤ +125oC - 0.4 V High Impedance Output Leakage Current IIOZ VCC = 5.5V, G = 5.5V, VI/O = GND or VCC 1, 2, 3 -55oC ≤ TA ≤ +125oC -1.0 1.0 µA VCC = 5.5V, VI = GND or VCC, P Not Tested 1, 2, 3 -55oC ≤ TA ≤ +125oC -1.0 1.0 µA Input Leakage Current II GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS Standby Supply Current ICCSB VI = VCC or GND, VCC = 5.5V, IO = 0mA 1, 2, 3 -55oC ≤ TA ≤ +125oC - 100 µA Operating Supply Current ICCOP VCC = 5.5V, G = GND, (Note 3), f = 1MHz, IO = 0mA, VI = VCC or GND 1, 2, 3 -55oC ≤ TA ≤ +125oC - 20 mA 7, 8A, 8B -55oC ≤ TA ≤ +125oC - - Functional Test FT VCC = 4.5V (Note 6) TABLE 2. HM-6617/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested LIMITS HM-6617/883 PARAMETER SYMBOL (NOTES 1, 2, 4) CONDITIONS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS Address Access Time TAVQV VCC = 4.5V and 5.5V (Note 5) 9, 10, 11 -55oC ≤ TA ≤ +125oC - 140 ns Output Enable Access Time TGLQV VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC - 50 ns Chip Enable Access Time TELQV VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC - 120 ns Address Setup Time TAVEL VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 20 - ns Address Hold Time TELAX VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 25 - ns Chip Enable Low Width TELEH VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 120 - ns Chip Enable High Width TEHEL VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤ TA ≤ +125oC 40 - ns 3 HM-6617/883 TABLE 2. HM-6617/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued) Device Guaranteed and 100% Tested LIMITS HM-6617/883 PARAMETER (NOTES 1, 2, 4) CONDITIONS SYMBOL Read Cycle Time TELEL GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 9, 10, 11 -55oC ≤ TA ≤ +125oC 160 - ns VCC = 4.5V and 5.5V NOTES: 1. All voltages referenced to Device GND. 2. AC measurements assume transition time ≤ 5ns; input levels = 0.0V to 3.0V; timing reference levels = 1.5V; output load = 1TTL equivalent load and CL ≅ 50pF. 3. Typical derating = 5mA/MHz increase in ICCOP. 4. All tests performed with P hardwired to VCC. 5. TAVQV = TELQV + TAVEL. 6. Tested as follows: f = 1MHz, VIH = 2.4V, VIL = 0.8V, IOH = -1mA, IOL = +1mA, VOH ≥ 1.5V, VOL ≤ 1.5V. TABLE 3. HM-6617/883 AC AND DC ELECTRICAL PERFORMANCE SPECIFICATIONS LIMITS HM-6617/883 PARAMETER (NOTES 1, 2) CONDITIONS SYMBOL NOTES TEMPERATURE MIN MAX UNITS Input Capacitance CIN VCC = Open, f = 1MHz, All Measurements Referenced to Device GND 2 +25oC - 10 pF I/O Capacitance CI/O VCC = Open, f = 1MHz, All Measurements Referenced to Device GND 2 +25oC - 12 pF VCC = 4.5V and 5.5V 2 -55oC ≤ TA ≤ +125oC 5 - ns 5 - ns Chip Enable Time TELQX Output Enable Time TGLQX VCC = 4.5V and 5.5V 2 -55oC ≤ TA ≤ +125oC Chip Disable Time TEHQZ VCC = 4.5V and 5.5V 2 -55oC ≤ TA ≤ +125oC - 50 ns Output Disable Time TGHQZ VCC = 4.5V and 5.5V 2 -55oC ≤ TA ≤ +125oC - 50 ns 2 -55oC ≤ TA ≤ +125oC VCC1V - V Output High Voltage VOH2 VCC = 4.5V, IO = 100µA NOTES: 1. All tests performed with P hardwired to VCC. 2. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design changes which would affect these characteristics. TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS METHOD SUBGROUPS Initial Test 100%/5004 - Interim Test 100%/5004 1, 7, 9 PDA 100%/5004 1 Final Test 100%/5004 2, 3, 8A, 8B, 10, 11 Group A Samples/5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Groups C & D Samples/5005 1, 7, 9 4 HM-6617/883 Switching Waveforms TAVQV ADDRESSES VALID ADDRESS 1.5V VALID ADDRESSES 1.5V 0V TELEL TAVEL 3.0V TELAX TELEH E 1.5V 3.0V 1.5V 1.5V 1.5V 0V TEHEL TEHQZ TELQV TGLQV G 3.0V 1.5V 1.5V 0V TGLQX TGHQZ DATA OUTPUT Q0-Q7 TELQX VALID DATA TS FIGURE 1. READ CYCLE Test Circuit DUT CL (NOTE) IOH NOTE: TEST HEAD CAPACITANCE ± 1.5V EQUIVALENT CIRCUIT FIGURE 2. TEST CIRCUIT 5 IOL HM-6617/883 Burn-In Circuit NOTES:HM-6617/883 (.600 INCH) SBDIP VCC C f8 1 A7 VCC 24 f7 2 A6 A6 23 f11 f6 3 A5 A5 22 f12 f5 4 A4 P 21 VCC f4 5 A3 G 20 f1 f3 6 A2 A10 19 f2 7 A1 E 18 f1 8 A0 Q7 17 9 Q0 Q6 16 10 Q1 Q5 15 11 Q2 Q4 14 12 GND Q3 13 VCC/2 f13 f0 VCC/2 GND f0 = 100KHz ± 10%. All resistors = 47kΩ Unless Otherwise Noted. VCC = 5.5V ± 0.05V. C = 0.01 µF min. 6 HM-6617/883 Die Characteristics DIE DIMENSIONS: 140 x 232 x 19 ± 1mils GLASSIVATION: Type: SiO2 Thickness: 7kÅ ± 9kÅ METALLIZATION: Type: Si - Al Thickness: 11kÅ ± 15kÅ WORST CASE CURRENT DENSITY: 1.7 x 105 A/cm2 Metallization Mask Layout HM-6617/883 A4 A5 A6 A7 VCC A8 A9 P A3 G A2 A10 A1 E A0 Q7 Q0 Q1 Q2 GND Q3 Q4 Q5 Q6 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 7