REVISIONS LTR DESCRIPTION A Under Table I, Switching specifications, ADC output section, Output clock to data propagation delay (tDC), both LVDS and CMOS mode tests, delete condition “SDR rising edge” and replace with “SDR falling edge”. - ro DATE APPROVED 13-11-04 C. SAFFLE CURRENT DESIGN ACTIVITY CAGE CODE 16236 HAS CHANGED NAMES TO: DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 Prepared in accordance with ASME Y14.24 Vendor item drawing REV PAGE REV A A A A A A PAGE 18 19 20 21 22 23 REV STATUS OF PAGES REV A A A A A A A A A A A A A A A A A PAGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PMIC N/A PREPARED BY RICK OFFICER Original date of drawing YY-MM-DD CHECKED BY JOSEPH RODENBECK 10-07-22 APPROVED BY CHARLES F. SAFFLE SIZE A REV AMSC N/A DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 CODE IDENT. NO. TITLE MICROCIRCUIT, DIGITAL-LINEAR, 12 BIT, 250 MSPS, ANALOG TO DIGITAL CONVERTER, MONOLITHIC SILICON DWG NO. V62/10609 16236 A PAGE 1 OF 23 5962-V013-14 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 12 bit 250 MSPS analog to digital converter microcircuit, with an operating temperature range of -55°C to +125°C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/10609 - Drawing number 01 X E Device type (See 1.2.1) Case outline (See 1.2.2) Lead finish (See 1.2.3) 1.2.1 Device type(s). Device type Generic 01 Circuit function ISLA112P25MREP 12 bit, 250 MSPS analog to digital converter 1.2.2 Case outline(s). The case outline(s) are as specified herein. Outline letter Number of pins X 72 JEDEC PUB 95 Package style See figure 1 Quad flat leadless plastic package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacture: Finish designator A B C D E Z DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/10609 PAGE 2 1.3 Absolute maximum ratings. 1/ 1.8 V analog supply (AVDD) to analog ground (AVSS) .............................................. 1.8 V output supply (OVDD) to output ground (OVSS) .............................................. AVSS to OVSS ........................................................................................................... Analog inputs to AVSS ............................................................................................... Clock inputs to AVSS ................................................................................................. Logic inputs to AVSS ................................................................................................. Logic inputs to OVSS ................................................................................................. Junction temperature range (TJ) ................................................................................ -0.4 V to 2.1 V -0.4 V to 2.1 V -0.3 V to 0.3 V -0.4 V to AVDD + 0.3 V -0.4 V to AVDD + 0.3 V -0.4 V to OVDD + 0.3 V -0.4 V to OVDD + 0.3 V +150°C Storage temperature range (TSTG) ............................................................................ -65°C to +150°C Thermal resistance, junction to ambient (θJA) ............................................................ 24°C/W 2/ 1.4 Recommended operating conditions. 3/ Operating free-air temperature range (TA) ................................................................. -55°C to +125°C 1/ 2/ 3/ Stresses beyond those listed under “absolute maximum rating” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. Use of this product beyond the manufacturers design rules or stated parameters is done at the user’s risk. The manufacturer and/or distributor maintain no responsibility or liability for product used beyond the stated limits. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/10609 PAGE 3 2. APPLICABLE DOCUMENTS JEDEC PUB 95 - Registered and Standard Outlines for Semiconductor Devices IPC/JEDEC J STD-020 - Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices (Applications for copies should be addressed to the JEDEC Office, 3103 North 10th Street, Suite 240-S, Arlington, VA 22201-2107 or online at http://www.jedec.org) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as follows: A. B. C. Manufacturer’s name, CAGE code, or logo Pin 1 identifier ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Logic diagram. The logic diagram shall be as shown in figure 3. 3.5.4 Timing waveforms. The timing waveforms shall be as shown in figures 4, 5, 6, 7, 8, 9, 10, and 11. 3.5.5 Application information. Detailed application information may be found in the manufacturer’s datasheet. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/10609 PAGE 4 TABLE I. Electrical performance characteristics. 1/ Test Symbol Conditions 2/ Temperature, TA Device type Limits 3/ Min Max 1.36 1.59 Unit DC specifications. Analog input section. Full scale analog input range VFS Differential -55°C to +125°C 01 Input resistance RIN Differential +25°C 01 1000 typical Ω Input capacitance CIN Differential +25°C 01 1.9 typical pF Full scale range temperature drift AVTC +125°C 01 90 typical ppm / °C Input offset voltage VOS -55°C to +125°C 01 Gain error EG +25°C 01 Common mode output voltage VCM +25°C 01 Inputs common mode voltage +25°C 01 0.9 typical V CLKP, CLKN input swing +25°C 01 1.8 typical V -10 VPP 10 mV 2 typical 0.435 % 0.635 V Clock input section. Power requirements section. 1.8 V analog supply voltage AVDD -55°C to +125°C 01 1.7 1.9 V 1.8 V digital supply voltage OVDD -55°C to +125°C 01 1.7 1.9 V 1.8 V analog supply current IAVDD -55°C to +125°C 01 96 mA 1.8 V digital supply 4/ current (SDR) IOVDD 3 mA low voltage differential signaling (LVDS) -55°C to +125°C 01 76 mA 1.8 V digital supply 4/ current (DDR) IOVDD 3 mA LVDS +25°C 01 39 typical mA Power supply rejection ratio PSRR 30 MHz, 200 VPP signal on AVDD +25°C 01 -36 typical dB See footnotes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/10609 PAGE 5 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ Temperature, TA Device type Limits 2/ Min Unit Max DC specifications - continued. Total power dissipation section. Normal mode (SDR) PD 3 mA LVDS -55°C to +125°C 01 Normal mode (DDR) PD 3 mA LVDS +25°C 01 Nap mode PD -55°C to +125°C 01 92 mW Sleep mode PD -55°C to +125°C 01 18 mW CSB at logic high 310 mW 234 typical mW Nap mode wakeup time 5/ Sample clock running +25°C 01 1 typical µs Sleep mode wakeup time 5/ Sample clock running +25°C 01 1 typical ms AC specifications. 6/ Differential nonlinearity DNL -55°C to +125°C 01 -0.9 +0.9 LSB Integral nonlinearity INL -55°C to +125°C 01 -2.0 +2.0 LSB Minimum 7/ conversion rate fS MIN -55°C to +125°C 01 40 MSPS Maximum conversion rate fS MAX -55°C to +125°C 01 Signal to noise ratio SNR fIN = 10 MHz +25°C 01 fIN = 105 MHz -55°C to +125°C fIN = 190 MHz +25°C 65.9 typical fIN = 364 MHz +25°C 65.4 typical fIN = 695 MHz +25°C 63.8 typical fIN = 995 MHz +25°C 62.6 typical 250 MSPS 66.1 typical dBFS 62.7 See footnotes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/10609 PAGE 6 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ Temperature, TA Device type Limits 3/ Min Max AC specifications - continued. 6/ Signal to noise and distortion fIN = 10 MHz +25°C fIN = 105 MHz -55°C to +125°C fIN = 190 MHz +25°C 64.6 typical fIN = 364 MHz +25°C 63.9 typical fIN = 695 MHz +25°C 56.9 typical fIN = 995 MHz +25°C 49.6 typical fIN = 10 MHz +25°C fIN = 105 MHz -55°C to +125°C fIN = 190 MHz +25°C 10.4 typical fIN = 364 MHz +25°C 10.3 typical fIN = 695 MHz +25°C 9.2 typical fIN = 995 MHz +25°C 7.9 typical fIN = 10 MHz +25°C fIN = 105 MHz -55°C to +125°C fIN = 190 MHz +25°C 79 typical fIN = 364 MHz +25°C 76 typical fIN = 695 MHz +25°C 61 typical fIN = 995 MHz +25°C 51 typical Effective number of bits Spurious free dynamic range SINAD ENOB SFDR 01 Unit 65.3 typical dBFS 62.2 01 10.6 typical Bits 10.1 01 83.0 typical dBc 67 See footnotes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/10609 PAGE 7 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ Temperature, TA Device type Limits 3/ Min AC specifications - continued. 6/ Intermodulation distortion fIN = 70 MHz +25°C fIN = 170 MHz +25°C IMD 01 Unit Max -86 typical dBFS -97 typical Word error rate WER +25°C 01 Full power dissipation FPBW +25°C 01 10 -12 typical 1300 typical MHz Digital specifications. Inputs section. Input current high (SDIO, RESETN) IIH VIN = 1.8 V -55°C to +125°C 01 -1 1 µA Input current low (SDIO, RESETN) IIL VIN = 0 V -55°C to +125°C 01 -25 -5 µA Input voltage high (SDIO, RESETN) VIH -55°C to +125°C 01 1.17 Input voltage low (SDIO, RESETN) VIL -55°C to +125°C 01 Input current high 8/ (OUTMODE, NAPSLP, CLKDIV, OUTFMT) IIH -55°C to +125°C 01 Input current low (OUTMODE, NAPSLP, CLKDIV, OUTFMT) IIL -55°C to +125°C 01 Input capacitance CDI +25°C 01 V 0.63 V 15 40 µA -40 -15 µA 3 typical pF See footnotes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/10609 PAGE 8 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ Temperature, TA Device type Limits 3/ Min Unit Max Digital specifications - continued. Low voltage differential signaling (LVDS) outputs section. Differential output voltage VT 3 mA mode +25°C 01 620 typical Output offset voltage VOS 3 mA mode -55°C to +125°C 01 Output rise time tR +25°C 01 500 typical ps Output fall time tF +25°C 01 500 typical ps 950 mVPP 980 mV CMOS output section. Voltage output high VOH IOH = -500 µA -55°C to +125°C 01 Voltage output low VOL IOL = 1 mA -55°C to +125°C 01 Output rise time tR +25°C 01 1.8 typical ns Output fall time tF +25°C 01 1.3 typical ns Switching specifications. OVDD - 0.3 V 0.3 V See figures 4 and 5. ADC output section Aperture delay tA +25°C 01 375 typical ps RMS aperture jitter jA +25°C 01 60 typical fs Output clock to 9/ 10/ data propagation delay, LVDS mode tDC -55°C to +125°C 01 DDR rising edge -260 120 DDR falling edge -160 230 SDR falling edge -260 230 ps See footnotes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/10609 PAGE 9 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ Temperature, TA Device type Limits 3/ Min Max -220 200 DDR falling edge -310 110 SDR falling edge -310 200 Unit Switching specifications. ADC output section - continued. See figures 4 and 5. Output clock to 9/ data propagation delay, CMOS mode DDR rising edge tDC 01 -55°C to +125°C ps Latency (pipeline delay) L +25°C 01 7.5 typical cycles Overvoltage recovery tOVR +25°C 01 1 typical cycles SPI interface section. 10/ 11/ 12/ See figures 8 and 9. SCLK period tCLK Write operation -55°C to +125°C 01 Read operation 16 cycles 8/ 66 cycles SCLK duty cycle tHI / tCLK or tLO / tCLK Read or write -55°C to +125°C 01 25 75 % CSB↓ to SCLK↑ setup time tS Read or write -55°C to +125°C 01 1 cycles CSB↑ after SCLK↑ hold time tH Read or write -55°C to +125°C 01 3 cycles Data valid to SCK↑ setup time tDSW Write -55°C to +125°C 01 1 cycles Data valid after SCK↑ hold time tDHW Write -55°C to +125°C 01 3 cycles See footnotes at end of table. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/10609 PAGE 10 TABLE I. Electrical performance characteristics – Continued. 1/ Test Symbol Conditions 2/ Temperature, TA Device type Limits 3/ Min Unit Max Switching specifications. SPI interface section - continued. 10/ 11/ 12/ See figures 8 and 9. Data valid after SCK↓ time tDVR Read -55°C to +125°C 01 16.5 cycles Data invalid after SCK↑ time tDHR Read -55°C to +125°C 01 3 cycles Sleep mode 13/ CSB↓ to SCLK↑ setup time tS Read or write in sleep mode -55°C to +125°C 01 150 µs 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ Unless otherwise specified, AVDD = 1.8 V, OVDD = 1.8 V, AIN = -1 dBFS, fSAMPLE = maximum conversion rate (per speed grade). 3/ Parameters with min and/or max limits are 100% production tested at their worst case temperature extreme (+125°C). 4/ Digital supply current is dependent upon the capacitive loading of the loading of the digital outputs. IOVDD specifications apply for 10 pF load on each digital output. 5/ See nap / sleep mode description in the datasheet for more details 6/ AC specifications apply after internal calibration of the analog digital converter is invoked at the given sample rate and temperature. Refer to “power on calibration” and “user initiated reset” in the device datasheet for more details. 7/ The DLL range setting must be changed for low speed operation. 8/ The tri-level inputs internal switching thresholds are approximately 0.43 V and 1.34 V. It is advised to float the inputs, tie to ground or AVDD depending on desired function. 9/ The input clock to output clock delay is a function of sample rate, using the output clock to latch the data simplifies data capture for most application. 10/ Parameter guaranteed by characterization and not 100% tested. 11/ Serial peripheral interface (SPI) interface timing is directly proportional to the ADC sample period (tS). 4 ns at 250 MSPS. Minimum and maximum limits guaranteed by characterization, and not 100% tested. 12/ The SPI may operate asynchronously with respect to the ADC sample clock. 13/ The SPI chip select (CSB) setup time increases in sleep mode due to the reduced power state, CSB setup time in nap mode is equal to normal mode CSB setup time ( 4 ns minimum). DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/10609 PAGE 11 Case X FIGURE 1. Case outline. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/10609 PAGE 12 Case X - continued. Dimensions Inches Symbol Millimeters Min Max Min Max A --- 0.035 --- 0.90 A1 --- 0.007 --- 0.2 b 0.009 --- 0.24 --- D/E 0.393 BSC 10.00 BSC D1/E1 0.334 BSC 8.50 BSC D2/E2 0.236 BSC 6.00 BSC e 0.019 BSC 0.50 BSC L 0.015 N --- 0.40 72 --72 NOTES: 1. Controlling dimensions are millimeter, inch dimensions are given for reference only. 2. Dimension b applies to the metalized terminal and is measured between 0.15 mm (inch) and 0.30 mm (inch) from the terminal tip. 3. The configuration of the pin 1 identifier is optional, but must be located within the zone indicated. The pin 1 identifier may be either a mold or mark feature. FIGURE 1. Case outline - continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/10609 PAGE 13 Device type 01 Case outline X Terminal number Terminal symbol Terminal number Terminal symbol Terminal number Terminal symbol 1 AVDD 25 RESETN 49 D6N 2 DNC 26 OVSS 50 D6P 3 DNC 27 OVDD 51 D7N 4 DNC 28 DNC 52 D7P 5 DNC 29 DNC 53 D8N 6 AVDD 30 DNC 54 D8P 7 AVSS 31 DNC 55 OVSS 8 AVSS 32 D0N 56 OVDD 9 VINN 33 D0P 57 D9N 10 VINP 34 D1N 58 D9P 11 AVSS 35 D1P 59 D10N 12 AVDD 36 OVDD 60 D10P 13 DNC 37 D2N 61 D11N 14 DNC 38 D2P 62 D11P 15 VCM 39 D3N 63 ORN 16 CLKDIV 40 D3P 64 ORP 17 DNC 41 D4N 65 OVSS 18 DNC 42 D4P 66 SDO 19 AVDD 43 D5N 67 CSB 20 CLKP 44 D5P 68 SCLK 21 CLKN 45 OVSS 69 SDIO 22 OUTMODE 46 RLVDS 70 OUTFMT 23 NAPSLP 47 CLKOUTN 71 AVDD 24 AVDD 48 CLKOUTP 72 AVSS FIGURE 2. Terminal connections. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/10609 PAGE 14 Terminal symbol LVDS function SDR mode AVDD 1.8 V analog supply. DNC Do not connect. AVSS Analog ground. VINN, VINP VCM CLKDIV CLKP, CLKN OUTMODE DDR mode comments Analog input negative, positive. Common mode output. Clock divider control. Clock input true, complement. Output mode (LVDS). NAPSLP Power control, (nap, sleep modes). RESETN Power on reset (active low). OVSS Output ground. OVDD 1.8 V output supply. D0N LVDS bit 0 (LSB) output complement. DDR logical bits 1, 0 (LVDS) D0P LVDS bit 0 (LSB) output true. DDR logical bits 1, 0 (LVDS) D1N LVDS bit 1 output complement. NC in DDR D1P LVDS bit 1 output true. NC in DDR D2N LVDS bit 2 output complement. DDR logical bits 3, 2 (LVDS) D2P LVDS bit 2 output true. DDR logical bits 3, 2 (LVDS) D3N LVDS bit 3 output complement. NC in DDR D3P LVDS bit 3 output true. NC in DDR D4N LVDS bit 4 output complement. DDR logical bits 5, 4 (LVDS) D4P LVDS bit 4 output true. DDR logical bits 5, 4 (LVDS) D5N LVDS bit 5 output complement. NC in DDR D5P LVDS bit 5 output true. NC in DDR FIGURE 2. Terminal connections - continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/10609 PAGE 15 Terminal symbol LVDS function SDR mode RLVDS LVDS bias resistor (connect to OVSS with a 10 kΩ 1% resistor). CLKOUTN LVDS clock output complement. CLKOUTP LVDS clock output true. DDR mode comments D6N LVDS bit 6 output complement. DDR logical bits 7, 6 (LVDS) D6P LVDS bit 6 output true. DDR logical bits 7, 6 (LVDS) D7N LVDS bit 7 output complement. NC in DDR D7P LVDS bit 7 output true. NC in DDR D8N LVDS bit 8 output complement. DDR logical bits 9, 8 (LVDS) D8P LVDS bit 8 output true. DDR logical bits 9, 8 (LVDS) D9N LVDS bit 9 output complement. NC in DDR D9P LVDS bit 9 output true. NC in DDR D10N LVDS bit 10 output complement. DDR logical bits 11, 10 (LVDS) D10P LVDS bit 10 output true. DDR logical bits 11, 10 (LVDS) D11N LVDS bit 11 output complement. NC in DDR D11P LVDS bit 11 output true. NC in DDR ORN LVDS over range complement. ORP LVDS over range true. SDO Serial peripheral interface (SPI) serial data output (4.7 kΩ pull-up to OVDD is required). CSB SPI chip select (active low). SCLK SPI clock. SDIO SPI serial data input/output. OUTFMT AVSS Output data format (two’s complement, gray code, offset binary). Analog ground. NOTE: SDR is the default state at power up the package. FIGURE 2. Terminal connections - continued. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/10609 PAGE 16 FIGURE 3. Block diagram. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/10609 PAGE 17 FIGURE 4. LVDS timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/10609 PAGE 18 FIGURE 5. CMOS timing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/10609 PAGE 19 Input voltage Offset binary Two’s complement Gray code -Full scale 000 00 000 00 00 100 00 000 00 00 000 00 000 00 00 -Full scale + 1 LSB 000 00 000 00 01 100 00 000 00 01 000 00 000 00 01 Mid-scale 100 00 000 00 00 000 00 000 00 00 110 00 000 00 00 +Full scale - 1 LSB 111 11 111 11 10 011 11 111 11 10 100 00 00 00 01 +Full scale 111 11 111 11 11 011 11 111 111 1 100 00 000 00 00 Input voltage to output code mapping FIGURE 6. MSB first addressing waveforms. FIGURE 7. LSB first addressing waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/10609 PAGE 20 FIGURE 8. SPI write waveforms. FIGURE 9. SPI read waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/10609 PAGE 21 FIGURE 10. 2 byte transfer waveforms. FIGURE 11. N byte transfer waveforms. DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/10609 PAGE 22 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Part marking 2/ Vendor part number V62/10609-01XE 34371 ISLA112P25MREP ISLA112P25MREP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. 2/ This lead (Pb) free plastic package employ special Pb free material sets; molding compounds/die attach materials and nickel (Ni), Pb, and gold (Au) plate - precious metals (e4) termination finish, which Restriction of Hazardous Substances Directive (RoHS) compliant and compatible with both tin lead (SnPb) and Pb free soldering operations. This Pb free device is moisture sensitivity level (MSL) classified at Pb free peak reflow temperatures that meet or exceed the Pb free requirements of IPC/JEDEC J STD-020. CAGE code 34371 DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO Source of supply Intersil Corporation 1001 Murphy Ranch Road Milpitas, CA 95035-6803 SIZE A CODE IDENT NO. 16236 REV A DWG NO. V62/10609 PAGE 23