DATASHEET

ISLA112P25M
Features
The ISLA112P25MREP is a low-power 12-bit, 250MSPS
analog-to-digital converter. Designed with Intersil’s
proprietary FemtoCharge™ technology on a standard
CMOS process.
• Programmable Gain, Offset and Skew Control
• 1.3GHz Analog Input Bandwidth
• 60fs Clock Jitter
• Over-Range Indicator
A serial peripheral interface (SPI) port allows for
extensive configurability, as well as fine control of various
parameters such as gain and offset.
• Selectable Clock Divider: ÷1, ÷2 or ÷4
• Clock Phase Selection
• Nap and Sleep Modes
Digital output data is presented in selectable LVDS or
CMOS formats. The ISLA112P25MREP is available in a
72 Ld QFN package with an exposed paddle. Operating
from a 1.8V supply, performance is specified over the full
military temperature range (-55°C to +125°C).
• Two’s Complement, Gray Code or Binary Data Format
• SDR/DDR LVDS-Compatible or LVCMOS Outputs
• Programmable Built-in Test Patterns
• Single-Supply 1.8V Operation
Applications
• Pb-Free (RoHS Compliant)
• Power Amplifier Linearization
VID Features
• Radar and Satellite Antenna Array Processing
• Specifications per DSCC VID V62/10609
• Broadband Communications
• Full Military Temperature Electrical Performance from
-55°C to +125°C
• High-Performance Data Acquisition
• Communications Test Equipment
• Controlled Baseline with One Wafer Fabrication Site
and One Assembly/Test Site
Key Specifications
• Full Homogeneous Lot Processing in Wafer Fab
• SNR = 62.7dBFS for fIN = 105MHz (-1dBFS)
• No Combination of Wafer Fabrication Lots in Assembly
• SFDR = 67dBc for fIN = 105MHz (-1dBFS)
• Total Power Consumption
- 310mW @ 250MSPS (SDR Mode)
- 234mW @ 250MSPS (DDR Mode)
• Full Traceability Through Assembly and Test by
• Date/Trace Code Assignment
• Enhanced Process Change Notification
• Enhanced Obsolescence Management
• Eliminates Need for Up-Screening a COTS Component
CLKP
OVDD
AVDD
CLKDIV
Block Diagram
CLKOUTP
CLOCK
GENERATION
CLKN
CLKOUTN
D[11:0]P
12-BIT
250 MSPS
ADC
VINN
NAPSLP
1.25V
November 17, 2011
FN7646.1
1
+
–
AVSS
VCM
SPI
CONTROL
CSB
SCLK
SDIO
SDO
SHA
DIGITAL
ERROR
CORRECTION
D[11:0]N
LVDS/CMOS
DRIVERS
OUTFMT
ORP
ORN
OUTMODE
OVSS
VINP
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
FemtoCharge is a trademark of Kenet Inc. Copyright Intersil Americas Inc. 2011. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISLA112P25M
Low Power 12-Bit, 250MSPS ADC
ISLA112P25M
Pin Configuration
AVSS
AVDD
OUTFMT
SDIO
SCLK
CSB
SDO
OVSS
ORP
ORN
D11P
D11N
D10P
D10N
D9P
D9N
OVDD
OVSS
ISLA112P25MREP
(72 LD QFN)
TOP VIEW
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
AVDD
1
54 D8P
DNC
2
53 D8N
DNC
3
52 D7P
DNC
4
51 D7N
DNC
5
50 D6P
AVDD
6
49 D6N
AVSS
7
48 CLKOUTP
AVSS
8
47 CLKOUTN
VINN
9
46 RLVDS
VINP 10
45 OVSS
AVSS 11
44 D5P
AVDD 12
43 D5N
DNC 13
42 D4P
DNC 14
41 D4N
VCM 15
40 D3P
CLKDIV 16
39 D3N
DNC 17
38 D2P
Connect Thermal Pad to AVSS
DNC 18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
AVDD
CLKP
CLKN
OUTMODE
NAPSLP
AVDD
RESETN
OVSS
OVDD
DNC
DNC
DNC
DNC
D0N
D0P
D1N
D1P
OVDD
37 D2N
Pin Descriptions
PIN
NUMBER
LVDS [LVCMOS]
NAME
1, 6, 12, 19,
24, 71
AVDD
2, 3, 4, 5, 13,
14, 17, 18, 28,
29, 30, 31
DNC
Do Not Connect
7, 8, 11, 72
AVSS
Analog Ground
9, 10
VINN, VINP
15
VCM
16
CLKDIV
2
LVDS [LVCMOS] FUNCTION
SDR MODE
DDR MODE
COMMENTS
1.8V Analog Supply
Analog Input Negative, Positive
Common Mode Output
Tri-Level Clock Divider Control
FN7646.1
November 17, 2011
ISLA112P25M
Pin Descriptions (Continued)
PIN
NUMBER
LVDS [LVCMOS]
NAME
20, 21
CLKP, CLKN
22
OUTMODE
23
NAPSLP
Tri-Level Power Control (Nap, Sleep modes)
25
RESETN
Power On Reset (Active Low, see page 15)
26, 45, 55, 65
OVSS
Output Ground
27, 36, 56
OVDD
1.8V Output Supply
32
D0N
[NC]
LVDS Bit 0 (LSB) Output Complement
[NC in LVCMOS]
DDR Logical Bits 1, 0 (LVDS)
33
D0P
[D0]
LVDS Bit 0 (LSB) Output True
[LVCMOS Bit 0]
DDR Logical Bits 1, 0 (LVDS or CMOS)
34
D1N
[NC]
LVDS Bit 1 Output Complement
[NC in LVCMOS]
NC in DDR
35
D1P
[D1]
LVDS Bit 1 Output True
[LVCMOS Bit 1]
NC in DDR
37
D2N
[NC]
LVDS Bit 2 Output Complement
[NC in LVCMOS]
DDR Logical Bits 3,2 (LVDS)
38
D2P
[D2]
LVDS Bit 2 Output True
[LVCMOS Bit 2]
DDR Logical Bits 3,2 (LVDS or CMOS)
39
D3N
[NC]
LVDS Bit 3 Output Complement
[NC in LVCMOS]
NC in DDR
40
D3P
[D3]
LVDS Bit 3 Output True
[LVCMOS Bit 3]
NC in DDR
41
D4N
[NC]
LVDS Bit 4 Output Complement
[NC in LVCMOS]
DDR Logical Bits 5,4 (LVDS)
42
D4P
[D4]
LVDS Bit 4 Output True
[LVCMOS Bit 4]
DDR Logical Bits 5,4 (LVDS or CMOS)
43
D5N
[NC]
LVDS Bit 5 Output Complement
[NC in LVCMOS]
NC in DDR
44
D5P
[D5]
LVDS Bit 5 Output True
[LVCMOS Bit 5]
NC in DDR
46
RLVDS
47
CLKOUTN
[NC]
LVDS Clock Output Complement
[NC in LVCMOS]
48
CLKOUTP
[CLKOUT]
LVDS Clock Output True
[LVCMOS CLKOUT]
49
D6N
[NC]
LVDS Bit 6 Output Complement
[NC in LVCMOS]
DDR Logical Bits 7,6 (LVDS)
50
D6P
[D6]
LVDS Bit 6 Output True
[LVCMOS Bit 6]
DDR Logical Bits 7,6 (LVDS or CMOS)
51
D7N
[NC]
LVDS Bit 7 Output Complement
[NC in LVCMOS]
NC in DDR
52
D7P
[D7]
LVDS Bit 7 Output True
[LVCMOS Bit 7]
NC in DDR
53
D8N
[NC]
LVDS Bit 8 Output Complement
[NC in LVCMOS]
DDR Logical Bits 9,8 (LVDS)
3
LVDS [LVCMOS] FUNCTION
SDR MODE
DDR MODE
COMMENTS
Clock Input True, Complement
Tri-Level Output Mode Control (LVDS, LVCMOS)
LVDS Bias Resistor
(Connect to OVSS with a 10kΩ, 1% resistor)
FN7646.1
November 17, 2011
ISLA112P25M
Pin Descriptions (Continued)
PIN
NUMBER
LVDS [LVCMOS]
NAME
LVDS [LVCMOS] FUNCTION
SDR MODE
DDR MODE
COMMENTS
54
D8P
[D8]
LVDS Bit 8 Output True
[LVCMOS Bit 8]
DDR Logical Bits 9,8 (LVDS or CMOS)
57
D9N
[NC]
LVDS Bit 9 Output Complement
[NC in LVCMOS]
NC in DDR
58
D9P
[D9]
LVDS Bit 9 Output True
[LVCMOS Bit 9]
NC in DDR
59
D10N
[NC]
LVDS Bit 10 Output Complement
[NC in LVCMOS]
DDR Logical Bits 11,10 (LVDS)
60
D10P
[D10]
LVDS Bit 10 Output True
[LVCMOS Bit 10]
DDR Logical Bits 11,10 (LVDS or CMOS)
61
D11N
[NC]
LVDS Bit 11 Output Complement
[NC in LVCMOS]
NC in DDR
62
D11P
[D11]
LVDS Bit 11 Output True
[LVCMOS Bit 11]
NC in DDR
63
ORN
[NC]
LVDS Over Range Complement
[NC in LVCMOS]
64
ORP
[OR]
LVDS Over Range True
[LVCMOS Over Range]
66
SDO
SPI Serial Data Output
(4.7kΩ pull-up to OVDD is required)
67
CSB
SPI Chip Select (active low)
68
SCLK
SPI Clock
69
SDIO
SPI Serial Data Input/Output
70
OUTFMT
Exposed Paddle
AVSS
Tri-Level Output Data Format Control (Two’s
Comp., Gray Code, Offset Binary)
Analog Ground
NOTE: LVCMOS Output Mode Functionality is shown in brackets (NC = No Connection). SDR is the default state at power-up for
the 72 Ld package.
Ordering Information
PART NUMBER
PART MARKING
ISLA112P25MREP (Note 1)
ISLA112P25 MREP
SPEED
(MSPS)
TEMP. RANGE
(°C)
250
-55 to +125
PACKAGE
(Pb-Free)
72 Ld QFN
PKG.
DWG. #
L72.10x10D
NOTE:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach
materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
4
FN7646.1
November 17, 2011
ISLA112P25M
Table of Contents
Block Diagram ..................................................................................................................................... 1
Pin Configuration................................................................................................................................. 2
Pin Descriptions .................................................................................................................................. 2
Ordering Information .......................................................................................................................... 4
Absolute Maximum Ratings ................................................................................................................. 6
Thermal Information ........................................................................................................................... 6
Operating Conditions ........................................................................................................................... 6
Electrical Specifications ....................................................................................................................... 6
Digital Specifications ........................................................................................................................... 8
Timing Diagrams ................................................................................................................................. 9
Switching Specifications ...................................................................................................................... 9
Typical Performance Curves .............................................................................................................. 11
Theory of Operation........................................................................................................................... 14
Functional Description.......................................................................................................................
Power-On Calibration ........................................................................................................................
User-Initiated Reset .........................................................................................................................
Analog Input ...................................................................................................................................
Clock Input .....................................................................................................................................
Jitter ..............................................................................................................................................
Voltage Reference ............................................................................................................................
Digital Outputs ................................................................................................................................
Over Range Indicator........................................................................................................................
Power Dissipation.............................................................................................................................
Nap/Sleep .......................................................................................................................................
Data Format ....................................................................................................................................
14
14
15
15
16
17
17
17
17
17
17
18
Serial Peripheral Interface ................................................................................................................ 20
SPI Physical Interface .......................................................................................................................
SPI Configuration .............................................................................................................................
Device Information...........................................................................................................................
Indexed Device Configuration/Control .................................................................................................
Global Device Configuration/Control....................................................................................................
SPI Memory Map..............................................................................................................................
20
21
21
21
22
25
Equivalent Circuits............................................................................................................................. 26
ADC Evaluation Platform ................................................................................................................... 27
Layout Considerations ....................................................................................................................... 27
Split Ground and Power Planes...........................................................................................................
Clock Input Considerations ................................................................................................................
Exposed Paddle................................................................................................................................
Bypass and Filtering .........................................................................................................................
LVDS Outputs ..................................................................................................................................
LVCMOS Outputs..............................................................................................................................
Unused Inputs .................................................................................................................................
27
27
27
27
27
28
28
Definitions ......................................................................................................................................... 28
Revision History ................................................................................................................................ 28
Products ............................................................................................................................................ 28
Package Outline Drawing .................................................................................................................. 29
5
FN7646.1
November 17, 2011
ISLA112P25M
Absolute Maximum Ratings
AVDD to AVSS . . . . . .
OVDD to OVSS. . . . . .
AVSS to OVSS . . . . . .
Analog Inputs to AVSS
Clock Inputs to AVSS .
Logic Input to AVSS . .
Logic Inputs to OVSS .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Thermal Information
. . . . . . -0.4V to
. . . . . . -0.4V to
. . . . . . -0.3V to
-0.4V to AVDD +
-0.4V to AVDD +
-0.4V to OVDD +
-0.4V to OVDD +
Thermal Resistance (Typical)
2.1V
2.1V
0.3V
0.3V
0.3V
0.3V
0.3V
θJA (°C/W) θJC (°C/W)
72 Ld QFN Package (Note 2, 3) . . .
24
0.8
Storage Temperature . . . . . . . . . . . . . . . . -65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . -55°C to +125°C
Maximum Operating Junction Temperature. . . . . . . . +135°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
2. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
3. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V,
OVDD = 1.8V, TA = -55°C to +125°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = Maximum Conversion Rate (per
speed grade).
PARAMETER
SYMBOL
CONDITIONS
MIN
(Note 4)
TYP
MAX
(Note 4) UNITS
DC SPECIFICATIONS (Note 5)
Analog Input
Full-Scale Analog Input Range
VFS
Differential
1.47
VP-P
Input Resistance
RIN
Differential
1000
Ω
Input Capacitance
CIN
Differential
1.8
pF
Full Temp
90
ppm/°C
Full Scale Range Temp. Drift
AVTC
Input Offset Voltage
VOS
±2
mV
EG
±0.6
%
VCM
535
mV
Inputs Common Mode Voltage
0.9
V
CLKP, CLKN Input Swing
1.8
V
Gain Error
Common-Mode Output Voltage
Clock Inputs
Power Requirements
1.8V Analog Supply Voltage
AVDD
1.8
V
1.8V Digital Supply Voltage
OVDD
1.8
V
1.8V Analog Supply Current
90
mA
3mA LVDS
58
mA
1.8V Digital Supply Current (DDR) (Note 6)
IAVDD
I
OVDD
I
OVDD
3mA LVDS
39
mA
Power Supply Rejection Ratio
PSRR
30MHz, 200mVP-P signal on AVDD
-36
dB
1.8V Digital Supply Current (SDR) (Note 6)
Total Power Dissipation
Normal Mode (SDR)
PD
3mA LVDS
267
mW
Normal Mode (DDR)
PD
3mA LVDS
234
mW
Nap Mode
PD
84
mW
Sleep Mode
PD
CSB at logic high
2
mW
Nap Mode Wakeup Time (Note 7)
Sample Clock Running
1
µs
Sleep Mode Wakeup Time (Note 7)
Sample Clock Running
1
ms
6
FN7646.1
November 17, 2011
ISLA112P25M
Electrical Specifications
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V,
OVDD = 1.8V, TA = -55°C to +125°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = Maximum Conversion Rate (per
speed grade). (Continued)
PARAMETER
SYMBOL
CONDITIONS
MIN
(Note 4)
TYP
MAX
(Note 4) UNITS
AC SPECIFICATIONS (Note 9)
Differential Nonlinearity
DNL
±0.3
LSB
Integral Nonlinearity
INL
±0.8
LSB
Minimum Conversion Rate (Note 8)
fS MIN
40
MSPS
Maximum Conversion Rate
fS MAX
250
MSPS
fIN = 10MHz
66.1
dBFS
fIN = 105MHz
66.1
dBFS
fIN = 190MHz
65.9
dBFS
fIN = 364MHz
65.4
dBFS
fIN = 695MHz
63.8
dBFS
fIN = 995MHz
62.6
dBFS
fIN = 10MHz
65.3
dBFS
fIN = 105MHz
65.3
dBFS
fIN = 190MHz
64.6
dBFS
fIN = 364MHz
63.9
dBFS
fIN = 695MHz
56.9
dBFS
fIN = 995MHz
49.6
dBFS
fIN = 10MHz
10.6
Bits
fIN = 105MHz
10.6
Bits
fIN = 190MHz
10.4
Bits
fIN = 364MHz
10.3
Bits
fIN = 695MHz
9.2
Bits
fIN = 995MHz
7.9
Bits
83.0
dBc
fIN = 105MHz
87
dBc
fIN = 190MHz
79.4
dBc
fIN = 364MHz
76.1
dBc
fIN = 695MHz
60.6
dBc
fIN = 995MHz
50.7
dBc
fIN = 70MHz
-85.7
dBFS
fIN = 170MHz
-97.1
dBFS
Signal-to-Noise Ratio (Note 5)
Signal-to-Noise and Distortion
Effective Number of Bits
SNR
SINAD
ENOB
Spurious-Free Dynamic Range
Intermodulation Distortion
SFDR
IMD
7
fIN = 10MHz
FN7646.1
November 17, 2011
ISLA112P25M
Electrical Specifications
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V,
OVDD = 1.8V, TA = -55°C to +125°C (typical specifications at +25°C), AIN = -1dBFS, fSAMPLE = Maximum Conversion Rate (per
speed grade). (Continued)
PARAMETER
SYMBOL
CONDITIONS
MIN
(Note 4)
TYP
Word Error Rate
WER
10-12
Full Power Bandwidth
FPBW
1.3
MAX
(Note 4) UNITS
GHz
NOTES:
4. For min and max parameter limits, refer to DSCC drawing number V62/10609.
5. To ensure device accuracy the measurement temperature is to be within 60°C of the calibration temperature.
6. Digital Supply Current is dependent upon the capacitive loading of the digital outputs. IOVDD specifications apply for 10pF load
on each digital output.
7. See Nap /Sleep Mode description on page 17 for more details.
8. The DLL Range setting must be changed for low speed operation. See “Serial Peripheral Interface” on page 20 for more detail.
9. AC Specifications apply after internal calibration of the ADC is invoked at the given sample rate and temperature. Refer to
“Power-On Calibration” on page 14 and “User-Initiated Reset” on page 15 for more details.
Digital Specifications
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
INPUTS
Input Current High (SDIO, RESETN)
IIH
VIN = 1.8V
Input Current Low (SDIO, RESETN)
IIL
VIN = 0V
Input Voltage High (SDIO, RESETN)
1
µA
-12
µA
VIH
1.8
V
Input Voltage Low (SDIO, RESETN)
VIL
0
V
Input Current High (OUTMODE, NAPSLP, CLKDIV,
OUTFMT) (Note 10)
IIH
25
µA
Input Current Low (OUTMODE, NAPSLP, CLKDIV,
OUTFMT)
IIL
25
µA
Input Capacitance
CDI
3
pF
LVDS OUTPUTS
Differential Output Voltage
Output Offset Voltage
VT
3mA Mode
620
mVP-P
VOS
3mA Mode
965
mV
Output Rise Time
tR
500
ps
Output Fall Time
tF
500
ps
OVDD - 0.1
V
0.1
V
CMOS OUTPUTS
Voltage Output High
VOH
IOH = -500µA
Voltage Output Low
VOL
IOL = 1mA
Output Rise Time
tR
1.8
ns
Output Fall Time
tF
1.4
ns
8
FN7646.1
November 17, 2011
ISLA112P25M
Timing Diagrams
SAMPLE N
SAMPLE N
INP
INP
INN
INN
tA
tA
CLKN
CLKP
CLKN
CLKP
tCPD
LATENCY = L CYCLES
tCPD
CLKOUTN
CLKOUTP
CLKOUTN
CLKOUTP
tDC
tDC
tPD
D[10/8/6/4/2/0]P
ODD BITS EVEN BITS ODD BITS EVEN BITS ODD BITS EVEN BITS
N-L
N-L
N-L + 1
N-L + 1
N-L + 2
N-L + 2
D[10/8/6/4/2/0]N
LATENCY = L CYCLES
EVEN BITS
N
tPD
D[11/0]P
D[11/0]N
DATA
N-L
FIGURE 1A. DDR
DATA
N-L + 1
DATA
N
FIGURE 1B. SDR
FIGURE 1. LVDS TIMING DIAGRAMS (See “Digital Outputs” on page 17)
SAMPLE N
SAMPLE N
INP
INP
INN
INN
tA
tA
CLKN
CLKP
CLKN
CLKP
tCPD
LATENCY = L CYCLES
LATENCY = L CYCLES
tCPD
CLKOUT
CLKOUT
tDC
tDC
tPD
D[10/8/6/4/2/0]
ODD BITS
N-L
EVEN BITS ODD BITS
N-L
N-L + 1
EVEN BITS
N-L + 1
ODD BITS
N-L + 2
EVEN BITS
N-L + 2
tPD
EVEN BITS
N
DATA
N-L
D[11/0]
FIGURE 2A. DDRx
DATA
N-L + 1
DATA
N
FIGURE 2B. SDR
FIGURE 2. CMOS TIMING DIAGRAM (See “Digital Outputs” on page 17)
Switching Specifications
PARAMETER
CONDITION
SYMBOL
MIN
TYP
MAX
UNITS
ADC OUTPUT
Aperture Delay
tA
375
ps
RMS Aperture Jitter
jA
60
fs
DDR Rising Edge
tDC
-50
ps
DDR Falling Edge
tDC
10
ps
SDR Falling Edge
tDC
-40
ps
DDR Rising Edge
tDC
-10
ps
DDR Falling Edge
tDC
-90
ps
SDR Falling Edge
tDC
-50
ps
Output Clock to Data Propagation
Delay, LVDS Mode
(Note 11)
Output Clock to Data Propagation
Delay, CMOS Mode
(Note 11)
9
FN7646.1
November 17, 2011
ISLA112P25M
Switching Specifications (Continued)
PARAMETER
CONDITION
SYMBOL
Latency (Pipeline Delay)
Over Voltage Recovery
MIN
TYP
MAX
UNITS
L
7.5
cycles
tOVR
1
cycles
SPI INTERFACE (Notes 12, 13)
SCLK Period
Write Operation
t
CLK
Note 15
cycles
(Note 12)
Read Operation
tCLK
Note 15
cycles
SCLK Duty Cycle (tHI/tCLK or
tLO/tCLK)
Read or Write
CSB↓ to SCLK↑ Setup Time
Read or Write
tS
Note 15
cycles
CSB↑ after SCLK↑ Hold Time
Read or Write
tH
Note 15
cycles
Data Valid to SCLK↑ Setup Time
Write
tDSW
Note 15
cycles
Data Valid after SCLK↑ Hold Time
Write
tDHW
Note 15
cycles
Data Valid after SCLK↓ Time
Read
tDVR
Data Invalid after SCLK↑ Time
Read
tDHR
Note 15
cycles
Sleep Mode CSB↓ to SCLK↑ Setup
Time (Note 14)
Read or Write in Sleep Mode
tS
Note 15
µs
Note 15
50
Note 15
Note 15
%
cycles
NOTES:
10. The Tri-Level Inputs internal switching thresholds are approximately 0.43V and 1.34V. It is advised to float the inputs, tie to
ground or AVDD depending on desired function.
11. The input clock to output clock delay is a function of sample rate, using the output clock to latch the data simplifies data
capture for most applications. Contact factory for more info if needed..
12. SPI Interface timing is directly proportional to the ADC sample period (4ns at 250MSPS).
13. The SPI may operate asynchronously with respect to the ADC sample clock.
14. The CSB setup time increases in sleep mode due to the reduced power state, CSB setup time in Nap mode is equal to normal
mode CSB setup time (4ns min).
15. Refer to DSCC drawing number V62/10609 for min/max parameters.
10
FN7646.1
November 17, 2011
ISLA112P25M
Typical Performance Curves All
Typical Performance Characteristics apply under the following
conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = Maximum
Conversion Rate (per speed grade).
85
SFDR @ 125MSPS
80
75
SNR @ 125MSPS
70
65
60
SNR @ 250MSPS
55
50
SFDR @ 250MSPS
0
200M
400M
600M
-50
HD2 AND HD3 MAGNITUDE (dBc)
SNR (dBFS) AND SFDR (dBc)
90
800M
-55
-60
HD2 @ 125MSPS
-65
HD2 @ 250MSPS
-70
-75
-80
-85
HD3 @ 125MSPS
-90
-95
HD3 @ 250MSPS
-100
0
1G
200M
-20
90
-30
SNR AND SFDR
HD2 & HD3 MAGNITUDE
100
SFDRFS (dBFS)
60
SNRFS (dBFS)
50
40
30
SFDR (dBc)
20
SNR (dBc)
10
0
-60
-50
-40
-30
-20
-10
-50
-60
HD3 (dBc)
-70
HD2 (dBFS)
-80
-90
-100
-110
HD3 (dBFS)
-120
-60
-50
0
80
75
SNR
65
100
130
160
190
220
SAMPLE RATE (MSPS)
FIGURE 7. SNR AND SFDR vs fSAMPLE
11
250
HD2 AND HD3 MAGNITUDE (dBc)
SNR (dBFS) AND SFDR (dBc)
SFDR
85
70
-30
-20
-10
0
FIGURE 6. HD2 AND HD3 vs AIN
95
60
40
-40
INPUT AMPLITUDE (dBFS)
FIGURE 5. SNR AND SFDR vs AIN
70
1G
HD2 (dBc)
-40
INPUT AMPLITUDE (dBFS)
90
800M
FIGURE 4. HD2 AND HD3 vs fIN
FIGURE 3. SNR AND SFDR vs fIN
70
600M
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
80
400M
-60
-70
HD3
-80
-90
-100
HD2
-110
-120
40
70
100
130
160
190
220
250
SAMPLE RATE (MSPS)
FIGURE 8. HD2 AND HD3 vs fSAMPLE
FN7646.1
November 17, 2011
ISLA112P25M
Typical Performance Curves All
Typical Performance Characteristics apply under the following
conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = Maximum
Conversion Rate (per speed grade). (Continued)
300
1.5
250
1.0
200
0.5
DNL (LSBs)
TOTAL POWER (mW)
SDR
150
DDR
100
50
0
0
-0.5
-1.0
40
70
100
130
160
190
220
250
-1.5
0
512
1024 1536 2048 2560 3072 3584 4096
CODE
SAMPLE RATE (MSPS)
FIGURE 10. DIFFERENTIAL NONLINEARITY
FIGURE 9. POWER vs fSAMPLE IN 3mA LVDS MODE
1.5
SNR (dBFS) & SFDR (dBc)
90
INL (LSBs)
1.0
0.5
0
-0.5
-1.0
-1.5
0
512
85
SFDR
80
75
70
65
SNR
60
55
50
300
1024 1536 2048 2560 3072 3584 4096
400
CODE
FIGURE 11. INTEGRAL NONLINEARITY
600
0
240000
AMPLITUDE (dBFS)
180000
150000
120000
90000
60000
800
AIN = -1.0dBFS
SNR = 66.0dBFS
SFDR = 82.5dBc
SINAD = 65.9dBFS
-20
210000
700
FIGURE 12. SNR AND SFDR vs VCM
270000
NUMBER OF HITS
500
INPUT COMMON MODE (mV)
-40
-60
-80
-100
30000
0
2050 2051 2052 2053 2054 2055 2056 2057 2058
CODE
FIGURE 13. NOISE HISTOGRAM
12
-120
0
20
40
60
80
100
120
FREQUENCY (MHz)
FIGURE 14. SINGLE-TONE SPECTRUM @ 10MHz
FN7646.1
November 17, 2011
ISLA112P25M
Typical Performance Curves All
Typical Performance Characteristics apply under the following
conditions unless otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -1dBFS, fIN = 105MHz, fSAMPLE = Maximum
Conversion Rate (per speed grade). (Continued)
0
AIN = -1.0dBFS
SNR = 65.7dBFS
SFDR = 79.2dBc
SINAD = 65.4dBFS
-20
AMPLITUDE (dBFS)
-20
AMPLITUDE (dBFS)
0
AIN = -1.0dBFS
SNR = 66.0dBFS
SFDR = 86.5dBc
SINAD = 65.9dBFS
-40
-60
-80
-40
-60
-80
-100
-100
-120
0
20
40
60
80
100
-120
120
0
20
120
AIN = -1.0dBFS
SNR = 61.6dBFS
SFDR = 49.8dBc
SINAD = 49.8dBFS
-20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
100
0
AIN = -1.0dBFS
SNR = 64.4dBFS
SFDR = 68.8dBc
SINAD = 62.6dBFS
-20
-40
-60
-80
-40
-60
-80
-100
-100
0
20
40
60
80
100
-120
0
120
20
40
60
80
100
120
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 17. SINGLE-TONE SPECTRUM @ 495MHz
FIGURE 18. SINGLE-TONE SPECTRUM @ 995MHz
0
0
IMD = -85.7dBFS
IMD = -97.1dBFS
-20
AMPLITUDE (dBFS)
-20
AMPLITUDE (dBFS)
80
FIGURE 16. SINGLE-TONE SPECTRUM @ 190MHz
0
-40
-60
-80
-40
-60
-80
-100
-100
-120
60
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 15. SINGLE-TONE SPECTRUM @ 105MHz
-120
40
0
20
40
60
80
100
120
FREQUENCY (MHz)
FIGURE 19. TWO-TONE SPECTRUM @ 70MHz
13
-120
0
20
40
60
80
100
120
FREQUENCY (MHz)
FIGURE 20. TWO-TONE SPECTRUM @ 170MHz
FN7646.1
November 17, 2011
ISLA112P25M
Theory of Operation
A user-initiated reset can subsequently be invoked in the
event that the previously mentioned conditions cannot
be met at power-up.
Functional Description
The ISLA112P25MREP is based upon a 12-bit, 250MSPS
A/D converter core that utilizes a pipelined successive
approximation architecture (Figure 21). The input
voltage is captured by a Sample-Hold Amplifier (SHA)
and converted to a unit of charge. Proprietary
charge-domain techniques are used to successively
compare the input to a series of reference charges.
Decisions made during the successive approximation
operations determine the digital code for each input
value. The converter pipeline requires six samples to
produce a result. Digital error correction is also applied,
resulting in a total latency of seven and one half clock
cycles. This is evident to the user as a time lag between
the start of a conversion and the data being available on
the digital outputs.
Power-On Calibration
The ADC performs a self-calibration at start-up. An
internal power-on-reset (POR) circuit detects the supply
voltage ramps and initiates the calibration when the
analog and digital supply voltages are above a threshold.
The following conditions must be adhered to for the
power-on calibration to execute successfully:
• A frequency-stable conversion clock must be applied
to the CLKP/CLKN pins
• DNC pins (especially 3, 4 and 18) must not be pulled
up or down
The SDO pin requires an external 4.7kΩ pull-up to OVDD.
If the SDO pin is pulled low externally during power-up,
calibration will not be executed properly.
After the power supply has stabilized, the internal POR
releases RESETN and an internal pull-up pulls it high,
which starts the calibration sequence. If a subsequent
user-initiated reset is required, the RESETN pin should
be connected to an open-drain driver with a drive
strength of less than 0.5mA.
The calibration sequence is initiated on the rising edge
of RESETN, as shown in Figure 22. The over-range
output (OR) is set high once RESETN is pulled low, and
remains in that state until calibration is complete. The
OR output returns to normal operation at that time, so it
is important that the analog input be within the
converter’s full-scale range to observe the transition. If
the input is in an over-range condition, the OR pin will
stay high, and it will not be possible to detect the end of
the calibration cycle.
While RESETN is low, the output clock
(CLKOUTP/CLKOUTN) is set low. Normal operation of the
output clock resumes at the next input clock edge
(CLKP/CLKN) after RESETN is deasserted. At 250MSPS
the nominal calibration time is 200ms, while the
maximum calibration time is 550ms.
• SDO (pin 66) must be high
• RESETN (pin 25) must begin low
• SPI communications must not be attempted
CLOCK
GENERATION
INP
SHA
INN
1.25V
+
–
2.5-BIT
FLASH
6-STAGE
1.5-BIT/STAGE
3-STAGE
1-BIT/STAGE
3-BIT
FLASH
DIGITAL
ERROR
CORRECTION
LVDS/LVCMOS
OUTPUTS
FIGURE 21. ADC CORE BLOCK DIAGRAM
14
FN7646.1
November 17, 2011
ISLA112P25M
70
CLKN
69
CLKP
68
CALIBRATION TIME
1.7V
67
SNR (dB)
RESETN
CALIBRATION BEGINS
ORP
66
65
64
1.8V
63
1.9V
62
CALIBRATION COMPLETE
61
60
-55
CLKOUTP
-35
-15
5
25
45
65
85
105
125
TEMPERATURE (°C)
FIGURE 22. CALIBRATION TIMING
FIGURE 23. SNR PERFORMANCE vs TEMPERATURE
(CAL DONE AT +25°C)
User-Initiated Reset
The performance of the ISLA112P25MREP changes with
variations in temperature, supply voltage or sample rate.
The extent of these changes may necessitate
recalibration, depending on system performance
requirements. Best performance will be achieved by
recalibrating the ADC under the environmental conditions
at which it will operate. Note: To ensure device accuracy
the measurement temperature is to be within 60°C of
the calibration temperature.
A supply voltage variation of less than 100mV will
generally result in an SNR change of less than 0.5dBFS
and SFDR change of less than 3dBc.
In situations where the sample rate is not constant, best
results will be obtained if the device is calibrated at the
highest sample rate. Reducing the sample rate by less
than 75MSPS will typically result in an SNR change of
less than 0.5dBFS and an SFDR change of less than
3dBc.
Figures 23 and 24 show the effect of temperature on
SNR and SFDR performance without recalibration. In
each plot, the ADC is calibrated at +25°C and
temperature is varied over the operating range without
recalibrating. The average change in SNR/SFDR is
shown, relative to the +25°C value.
15
90
1.7V
1.8V
85
SFDR (dB)
Recalibration of the ADC can be initiated at any time by
driving the RESETN pin low for a minimum of one clock
cycle. An open-drain driver with a drive strength of less
than 0.5mA is recommended, RESETN has an internal
high impedance pull-up to OVDD. As is the case during
power-on reset, the SDO, RESETN and DNC pins must be
in the proper state for the calibration to successfully
execute.
80
75
1.9V
70
65
60
-55
-35
-15
5
25
45
65
85
105
125
TEMPERATURE (°C)
FIGURE 24. SFDR PERFORMANCE vs TEMPERATURE
(CAL DONE AT +25°C)
Analog Input
The ADC core contains a fully differential input
(VINP/VINN) to the sample and hold amplifier (SHA). The
ideal full-scale input voltage is 1.45V, centered at the
VCM voltage of 0.535V as shown in Figure 25.
Best performance is obtained when the analog inputs are
driven differentially. The common-mode output voltage,
VCM, should be used to properly bias the inputs as
shown in Figures 26 through 28. An RF transformer will
give the best noise and distortion performance for
wideband and/or high intermediate frequency (IF)
inputs. Two different transformer input schemes are
shown in Figures 26 and 27.
FN7646.1
November 17, 2011
ISLA112P25M
348Ω
1.8
69.8Ω
1.4
1.0
INN
INP
0.725V
CM
VCM
0.6
0.22µF
0.535V
25 Ω
0.1µF
FIGURE 28. DIFFERENTIAL AMPLIFIER INPUT
FIGURE 25. ANALOG INPUT RANGE
This dual transformer scheme is used to improve
common-mode rejection, which keeps the commonmode level of the input matched to VCM. The value of the
shunt resistor should be determined based on the
desired load impedance. The differential input resistance
of the ISLA112P25MREP is 1000Ω.
ADT1-1WT
KAD5512P
VCM
0.1µF
FIGURE 26. TRANSFORMER INPUT FOR GENERAL
PURPOSE APPLICATIONS
A differential amplifier, as shown in Figure 28, can be
used in applications that require DC-coupling. In this
configuration, the amplifier will typically dominate the
achievable SNR and distortion performance.
Clock Input
The clock input circuit is a differential pair (see
Figure 42). Driving these inputs with a high level (up to
1.8VPP on each input) sine or square wave will provide
the lowest jitter performance. A transformer with 4:1
impedance ratio will provide increased drive levels.
The recommended drive circuit is shown in Figure 29. A
duty range of 40% to 60% is acceptable. The clock can
be driven single-ended, but this will reduce the edge rate
and may impact SNR performance. The clock inputs are
internally self-biased to AVDD/2 to facilitate AC coupling.
200pF
TC4-1W
ADTL1-12
ADTL1-12
1000pF
KAD5512P
VCM
348Ω
1000pF
217 Ω
100 Ω
69.8Ω
49.9Ω
0.2
ADT1-1WT
25 Ω
100Ω
CLKP
1000pF
200pF
0.1µF
200O
Ω
KAD5512P
1000pF
CLKN
VCM
200pF
FIGURE 27. TRANSMISSION-LINE TRANSFORMER
INPUT FOR HIGH IF APPLICATIONS
The SHA design uses a switched capacitor input stage
(see Figure 41), which creates current spikes when the
sampling capacitance is reconnected to the input voltage.
This causes a disturbance at the input which must settle
before the next sampling point. Lower source impedance
will result in faster settling and improved performance.
Therefore a 1:1 transformer and low shunt resistance are
recommended for optimal performance.
FIGURE 29. RECOMMENDED CLOCK DRIVE
A selectable 2x frequency divider is provided in series
with the clock input. The divider can be used in the 2x
mode with a sample clock equal to twice the desired
sample rate. This allows the use of the Phase Slip
feature, which enables synchronization of multiple ADCs.
TABLE 1. CLKDIV PIN SETTINGS
CLKDIV PIN
DIVIDE RATIO
AVSS
2
Float
1
AVDD
4
The clock divider can also be controlled through the SPI
port, which overrides the CLKDIV pin setting. Details on
this are contained in “Serial Peripheral Interface” on
page 20.
16
FN7646.1
November 17, 2011
ISLA112P25M
A delay-locked loop (DLL) generates internal clock
signals for various stages within the charge pipeline. If
the frequency of the input clock changes, the DLL may
take up to 52µs to regain lock at 250MSPS. The lock time
is inversely proportional to the sample rate.
Jitter
In a sampled data system, clock jitter directly impacts
the achievable SNR performance. The theoretical
relationship between clock jitter (tJ) and SNR is shown in
Equation 1 and is illustrated in Figure 30.
1
SNR = 20 log 10 ⎛ --------------------⎞
⎝ 2πf t ⎠
(EQ. 1)
IN J
100
95
tj = 0.1ps
90
14 BITS
SNR (dB)
85
80
tj = 1ps
12 BITS
75
70
tj = 10ps
65
60
55
50
1
tj = 100ps
1000
FIGURE 30. SNR vs CLOCK JITTER
This relationship shows the SNR that would be achieved
if clock jitter were the only non-ideal factor. In reality,
achievable SNR is limited by internal factors such as
linearity, aperture jitter and thermal noise. Internal
aperture jitter is the uncertainty in the sampling instant
shown in Figure 1. The internal aperture jitter combines
with the input clock jitter in a root-sum-square fashion,
since they are not statistically correlated, and this
determines the total jitter in the system. The total jitter,
combined with other noise sources, then determines the
achievable SNR.
Voltage Reference
A temperature compensated voltage reference provides
the reference charges used in the successive
approximation operations. The full-scale range of each
A/D is proportional to the reference voltage. The voltage
reference is internally bypassed and is not accessible to
the user.
Digital Outputs
Output data is available as a parallel bus in
LVDS-compatible or CMOS modes. Additionally, the data
can be presented in either double data rate (DDR) or
single data rate (SDR) formats. The even numbered data
output pins are active in DDR mode. When CLKOUT is
low the MSB and all odd logical bits are output, while on
the high phase the LSB and all even logical bits are
presented. Figures 1 and 2 show the timing relationships
for LVDS/CMOS and DDR/SDR modes.
17
The output mode and LVDS drive current are selected via
the OUTMODE pin as shown in Table 2.
TABLE 2. OUTMODE PIN SETTINGS
OUTMODE PIN
MODE
AVSS
LVCMOS
Float
LVDS, 3mA
AVDD
LVDS, 2mA
The output mode can also be controlled through the SPI
port, which overrides the OUTMODE pin setting. Details
on this are contained in “Serial Peripheral Interface” on
page 20.
An external resistor creates the bias for the LVDS drivers.
A 10kΩ, 1% resistor must be connected from the RLVDS
pin to OVSS.
10 BITS
10
100
INPUT FREQUENCY (MHz)
Additionally, the drive current for LVDS mode can be set
to a nominal 3mA or a power-saving 2mA. The lower
current setting can be used in designs where the receiver
is in close physical proximity to the ADC. The applicability
of this setting is dependent upon the PCB layout,
therefore the user should experiment to determine if
performance degradation is observed.
Over Range Indicator
The over range (OR) bit is asserted when the output
code reaches positive full-scale (e.g. 0xFFF in offset
binary mode). The output code does not wrap around
during an over-range condition. The OR bit is updated at
the sample rate.
Power Dissipation
The power dissipated by the ISLA112P25MREP is
primarily dependent on the sample rate and the output
modes: LVDS vs CMOS and DDR vs SDR. There is a static
bias in the analog supply, while the remaining power
dissipation is linearly related to the sample rate. The
output supply dissipation is approximately constant in
LVDS mode, but linearly related to the clock frequency in
CMOS mode. Figures 34 and 35 illustrate these
relationships.
Nap/Sleep
Portions of the device may be shut down to save power
during times when operation of the ADC is not required.
Two power saving modes are available: Nap, and Sleep.
Nap mode reduces power dissipation to less than 95mW
and recovers to normal operation in approximately 1µs.
Sleep mode reduces power dissipation to less than 6mW
but requires approximately 1ms to recover from a sleep
command.
Wake-up time from sleep mode is dependent on the
state of CSB; in a typical application CSB would be held
high during sleep, requiring a user to wait 150µs max
after CSB is asserted (brought low) prior to writing
‘001x’ to SPI Register 25. The device would be fully
powered up, in normal mode 1ms after this command is
written.
FN7646.1
November 17, 2011
ISLA112P25M
Wake-up from Sleep Mode Sequence (CSB high)
• Pull CSB Low
• Wait 150µs
• Write ‘001x’ to Register 25
• Wait 1ms until ADC fully powered on
In an application where CSB was kept low in sleep
mode, the 150µs CSB setup time is not required as the
SPI registers are powered on when CSB is low, the chip
power dissipation increases by ~ 15mW in this case.
The 1ms wake-up time after the write of a ‘001x’ to
register 25 still applies. It is generally recommended to
keep CSB high in sleep mode to avoid any unintentional
SPI activity on the ADC.
All digital outputs (Data, CLKOUT and OR) are placed in
a high impedance state during Nap or Sleep. The input
clock should remain running and at a fixed frequency
during Nap or Sleep, and CSB should be high. Recovery
time from Nap mode will increase if the clock is stopped,
since the internal DLL can take up to 52µs to regain lock
at 250MSPS
By default after the device is powered on, the operational
state is controlled by the NAPSLP pin as shown in Table 3.
TABLE 3. NAPSLP PIN SETTINGS
NAPSLP PIN
MODE
AVSS
Normal
Float
Sleep
AVDD
Nap
Offset binary coding maps the most negative input
voltage to code 0x000 (all zeros) and the most positive
input to 0xFFF (all ones). Two’s complement coding
simply complements the MSB of the offset binary
representation.
When calculating Gray code the MSB is unchanged. The
remaining bits are computed as the XOR of the current
bit position and the next most significant bit. Figure 31
shows this operation.
BINARY
11
10
9
••••
1
0
••••
GRAY CODE
11
10
••••
9
1
0
FIGURE 31. BINARY TO GRAY CODE CONVERSION
Converting back to offset binary from Gray code must be
done recursively, using the result of each bit for the next
lower bit as shown in Figure 32.
GRAY CODE
11
10
9
••••
The power-down mode can also be controlled through
the SPI port, which overrides the NAPSLP pin setting.
Details on this are contained in “Serial Peripheral
Interface” on page 20. This is an indexed function when
controlled from the SPI, but a global function when
driven from the pin.
••••
Data Format
••••
1
0
Output data can be presented in three formats: two’s
complement, Gray code and offset binary. The data
format is selected via the OUTFMT pin as shown in
Table 4.
TABLE 4. OUTFMT PIN SETTINGS
OUTFMT PIN
MODE
AVSS
Offset Binary
Float
Two’s Complement
AVDD
Gray Code
BINARY
11
10
9
••••
1
0
FIGURE 32. GRAY CODE TO BINARY CONVERSION
The data format can also be controlled through the SPI
port, which overrides the OUTFMT pin setting. Details on
this are contained in “Serial Peripheral Interface” on
page 20.
18
FN7646.1
November 17, 2011
ISLA112P25M
Mapping of the input voltage to the various data formats is shown in Table 5.
TABLE 5. INPUT VOLTAGE TO OUTPUT CODE MAPPING
INPUT VOLTAGE
OFFSET BINARY
TWO’S COMPLEMENT
GRAY CODE
–Full Scale
000 00 000 00 00
100 00 000 00 00
000 00 000 00 00
–Full Scale + 1LSB
000 00 000 00 01
100 00 000 00 01
000 00 000 00 01
Mid–Scale
100 00 000 00 00
000 00 000 00 00
110 00 000 00 00
+Full Scale – 1LSB
111 11 111 11 10
011 11 111 11 10
100 00 000 00 01
+Full Scale
111 11 111 11 11
011 11 111 111 1
100 00 000 00 00
CSB
SCLK
SDIO
R/W
W1
W0
A12
A11
A10
A1
A0
D7
D6
D5
D4
D3
D2
D1D
0
D3
D4
D5
D6
D7
FIGURE 33. MSB-FIRST ADDRESSING
CSB
SCLK
SDIO
A0
A1
A2
A11
A12
W0
W1
R/W
D1
D0
D2
FIGURE 34. LSB-FIRST ADDRESSING
tDSW
CSB
tDHW
tS
tCLK
tHI
tH
tLO
SCLK
SDIO
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
SPI WRITE
FIGURE 35. SPI WRITE
19
FN7646.1
November 17, 2011
ISLA112P25M
tDSW
CSB
tDHW
tS
tCLK
tHI
tH
tDHR
tDVR
tLO
SCLK
WRITING A READ COMMAND
SDIO
R/W
W1
W0
A12
A11
A10
A9
A2
READING DATA (3 WIRE MODE)
A1
A0
D7
D6
SDO
D3
D2
D1 D0
(4 WIRE MODE)
D7
D3
D2
D1 D0
SPI READ
FIGURE 36. SPI READ
CSB STALLING
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD 2
FIGURE 37. 2-BYTE TRANSFER
LAST LEGAL
CSB STALLING
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD N
FIGURE 38. N-BYTE TRANSFER
Serial Peripheral Interface
A serial peripheral interface (SPI) bus is used to
facilitate configuration of the device and to optimize
performance. The SPI bus consists of chip select (CSB),
serial clock (SCLK) serial data output (SDO), and serial
data input/output (SDIO). The maximum SCLK rate is
equal to the ADC sample rate (fSAMPLE) divided by 16
for write operations and fSAMPLE divided by 66 for
reads. At fSAMPLE = 250MHz, maximum SCLK is
15.63MHz for writing and 3.79MHz for read operations.
There is no minimum SCLK rate.
The following sections describe various registers that
are used to configure the SPI or adjust performance or
functional parameters. Many registers in the available
address space (0x00 to 0xFF) are not defined in this
document. Additionally, within a defined register there
may be certain bits or bit combinations that are
reserved. Undefined registers and undefined values
within defined registers are reserved and should not be
20
selected. Setting any reserved register or value may
produce indeterminate results.
SPI Physical Interface
The serial clock pin (SCLK) provides synchronization for
the data transfer. By default, all data is presented on the
serial data input/output (SDIO) pin in three-wire mode.
The state of the SDIO pin is set automatically in the
communication protocol (described below). A dedicated
serial data output pin (SDO) can be activated by setting
0x00[7] high to allow operation in four-wire mode.
The SPI port operates in a half duplex master/slave
configuration, with the ISLA112P25MREP functioning as a
slave. Multiple slave devices can interface to a single
master in three-wire mode only, since the SDO output of
an unaddressed device is asserted in four-wire mode.
The chip-select bar (CSB) pin determines when a slave
device is being addressed. Multiple slave devices can be
written to concurrently, but only one slave device can be
FN7646.1
November 17, 2011
ISLA112P25M
read from at a given time (again, only in three-wire
mode). If multiple slave devices are selected for reading
at the same time, the results will be indeterminate.
The communication protocol begins with an
instruction/address phase. The first rising SCLK edge
following a high to low transition on CSB determines the
beginning of the two-byte instruction/address command;
SCLK must be static low before the CSB transition. Data
can be presented in MSB-first order or LSB-first order.
The default is MSB-first, but this can be changed by
setting 0x00[6] high. Figures 33 and 34 show the
appropriate bit ordering for the MSB-first and LSB-first
modes, respectively. In MSB-first mode the address is
incremented for multi-byte transfers, while in LSB-first
mode it’s decremented.
In the default mode the MSB is R/W, which determines if
the data is to be read (active high) or written. The next
two bits, W1 and W0, determine the number of data
bytes to be read or written (see Table 6). The lower 13
bits contain the first address for the data transfer. This
relationship is illustrated in Figure 35, and timing values
are given in “Switching Specifications” on page 9.
After the instruction/address bytes have been read, the
appropriate number of data bytes are written to or read
from the ADC (based on the R/W bit status). The data
transfer will continue as long as CSB remains low and
SCLK is active. Stalling of the CSB pin is allowed at any
byte boundary (instruction/address or data) if the
number of bytes being transferred is three or less. For
transfers of four bytes or more, CSB is allowed stall in
the middle of the instruction/address bytes or before the
first data byte. If CSB transitions to a high state after
that point the state machine will reset and terminate the
data transfer.
Bit 6 LSB First
Setting this bit high configures the SPI to interpret serial data
as arriving in LSB to MSB order.
Bit 5 Soft Reset
Setting this bit high resets all SPI registers to default values.
Bit 4 Reserved
This bit should always be set high.
Bits 3:0 These bits should always mirror bits 4:7 to
avoid ambiguity in bit ordering.
ADDRESS 0X02: BURST_END
If a series of sequential registers are to be set, burst
mode can improve throughput by eliminating redundant
addressing. In 3-wire SPI mode the burst is ended by
pulling the CSB pin high. If the device is operated in
2-wire mode the CSB pin is not available. In that case,
setting the burst_end address determines the end of the
transfer. During a write operation, the user must be
cautious to transmit the correct number of bytes based
on the starting and ending addresses.
Bits 7:0 Burst End Address
This register value determines the ending address of the
burst data.
Device Information
ADDRESS 0X08: CHIP_ID
ADDRESS 0X09: CHIP_VERSION
The generic die identifier and a revision number,
respectively, can be read from these two registers.
Indexed Device Configuration/Control
TABLE 6. BYTE TRANSFER SELECTION
ADDRESS 0X10: DEVICE_INDEX_A
[W1:W0]
BYTES TRANSFERRED
00
1
01
2
A common SPI map, which can accommodate
single-channel or multi-channel devices, is used for all
Intersil ADC products. Certain configuration commands
(identified as Indexed in the SPI map) can be executed
on a per-converter basis. This register determines which
converter is being addressed for an Indexed command. It
is important to note that only a single converter can be
addressed at a time.
10
3
11
4 or more
Figures 37 and 38 illustrate the timing relationships for
2-byte and N-byte transfers, respectively. The operation
for a 3-byte transfer can be inferred from these
diagrams.
SPI Configuration
ADDRESS 0X00: CHIP_PORT_CONFIG
Bit ordering and SPI reset are controlled by this register.
Bit order can be selected as MSB to LSB (MSB first) or
LSB to MSB (LSB first) to accommodate various
microcontrollers.
Bit 7 SDO Active
This register defaults to 00h, indicating that no ADC is
addressed. Therefore Bit 0 must be set high in order to
execute any Indexed commands. Error code ‘AD’ is
returned if any indexed register is read from without
properly setting device_index_A.
ADDRESS 0X20: OFFSET_COARSE AND
ADDRESS 0X21: OFFSET_FINE
The input offset of the ADC core can be adjusted in fine
and coarse steps. Both adjustments are made via an
8-bit word as detailed in Table 7.
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
21
FN7646.1
November 17, 2011
ISLA112P25M
incremented or decremented, the user should first read
the register value then write the incremented or
decremented value back to the same register.
ADDRESS 0X25: MODES
PARAMETER
0x20[7:0]
COARSE OFFSET
0x21[7:0]
FINE OFFSET
Steps
255
255
–Full Scale (0x00)
-133LSB (-47mV)
-5LSB (-1.75mV)
Two distinct reduced power modes can be selected. By
default, the tri-level NAPSLP pin can select normal
operation or sleep modes (refer to “Nap/Sleep” on
page 17). This functionality can be overridden and
controlled through the SPI. This is an indexed function
when controlled from the SPI, but a global function when
driven from the pin. This register is not changed by a
Soft Reset.
Mid–Scale (0x80)
0.0LSB (0.0mV)
0.0LSB
TABLE 10. POWER-DOWN CONTROL
TABLE 7. OFFSET ADJUSTMENTS
+Full Scale (0xFF) +133LSB (+47mV) +5LSB (+1.75mV)
Nominal Step Size
1.04LSB (0.37mV)
0x25[2:0]
POWER-DOWN MODE
VALUE
0.04LSB
(0.014mV)
000
Pin Control
001
Normal Operation
ADDRESS 0X22: GAIN_COARSE
010
Nap Mode
ADDRESS 0X23: GAIN_MEDIUM
100
Sleep Mode
ADDRESS 0X24: GAIN_FINE
Gain of the ADC core can be adjusted in coarse, medium
and fine steps. Coarse gain is a 4-bit adjustment while
medium and fine are 8-bit. Multiple Coarse Gain Bits can
be set for a total adjustment range of +/- 4.2%. (‘0011’
=~ -4.2% and ‘1100’ =~ +4.2%) It is recommended to
use one of the coarse gain settings (-4.2%, -2.8%, 1.4%, 0, 1.4%, 2.8%, 4.2%) and fine-tune the gain
using the registers at 23h and 24h.
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read
the register value then write the incremented or
decremented value back to the same register.
TABLE 8. COARSE GAIN ADJUSTMENT
Nap mode must be entered by executing the following
sequence:
SEQUENCE
REGISTER
VALUE
1
0x10
0x01
2
0x25
0x02
3
0x10
0x02
4
0x25
0x02
Return to Normal operation as follows:
SEQUENCE
REGISTER
VALUE
1
0x10
0x01
NOMINAL COARSE GAIN ADJUST
(%)
2
0x25
0x01
0x22[3:0]
3
0x10
0x02
Bit3
+2.8
4
0x25
0x01
Bit2
+1.4
Bit1
-2.8
Global Device Configuration/Control
Bit0
-1.4
ADDRESS 0X71: PHASE_SLIP
TABLE 9. MEDIUM AND FINE GAIN ADJUSTMENTS
PARAMETER
0x23[7:0]
MEDIUM GAIN
0x24[7:0]
FINE GAIN
Steps
256
256
–Full Scale (0x00)
-2%
-0.20%
Mid–Scale (0x80)
0.00%
0.00%
+Full Scale (0xFF)
+2%
+0.2%
Nominal Step Size
0.016%
0.0016%
22
When using the clock divider, it’s not possible to
determine the synchronization of the incoming and
divided clock phases. This is particularly important when
multiple ADCs are used in a time-interleaved system.
The phase slip feature allows the rising edge of the
divided clock to be advanced by one input clock cycle
when in CLK/4 mode, as shown in Figure 39. Execution
of a phase_slip command is accomplished by first writing
a ‘0’ to bit 0 at address 71h followed by writing a ‘1’ to bit
0 at address 71h (32 sclk cycles).
FN7646.1
November 17, 2011
ISLA112P25M
TABLE 12. OUTPUT MODE CONTROL
CLK = CLKP – CLKN
VALUE
0x93[7:5]
000
Pin Control
001
LVDS 2mA
010
LVDS 3mA
100
LVCMOS
CLK
1.00ns
CLK÷4
4.00ns
CLK÷4
SLIP ONCE
TABLE 13. OUTPUT FORMAT CONTROL
CLK÷4
SLIP TWICE
VALUE
0x93[2:0]
OUTPUT FORMAT
000
Pin Control
001
Two’s Complement
010
Gray Code
100
Offset Binary
FIGURE 39. PHASE SLIP: CLK÷4 MODE,
fCLOCK = 1000MHz
ADDRESS 0X72: CLOCK_DIVIDE
The ISLA112P25MREP has a selectable clock divider that
can be set to divide by four, two or one (no division). By
default, the tri-level CLKDIV pin selects the divisor (refer
to “Clock Input” on page 16). This functionality can be
overridden and controlled through the SPI, as shown in
Table 11. This register is not changed by a Soft Reset.
ADDRESS 0X74: OUTPUT_MODE_B
ADDRESS 0X75: CONFIG_STATUS
Bit 6 DLL Range
This bit sets the DLL operating range to fast (default) or slow.
Internal clock signals are generated by a delay-locked loop
(DLL), which has a finite operating range. Table 14 shows
the allowable sample rate ranges for the slow and fast
settings.
TABLE 11. CLOCK DIVIDER SELECTION
VALUE
0x72[2:0]
CLOCK DIVIDER
000
Pin Control
001
Divide by 1
DLL RANGE
MIN
MAX
UNIT
010
Divide by 2
Slow
40
100
MSPS
100
Divide by 4
Fast
80
fS MAX
MSPS
ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the physical output
format of the data, as well as the logical coding. The
ISLA112P25MREP can present output data in two
physical formats: LVDS or LVCMOS. Additionally, the
drive strength in LVDS mode can be set high (3mA) or
low (2mA). By default, the tri-level OUTMODE pin selects
the mode and drive level (refer to “Digital Outputs” on
page 17). This functionality can be overridden and
controlled through the SPI, as shown in Table 12.
Data can be coded in three possible formats: two’s
complement, Gray code or offset binary. By default, the
tri-level OUTFMT pin selects the data format (refer to
“Data Format” on page 18). This functionality can be
overridden and controlled through the SPI, as shown in
Table 13.
This register is not changed by a Soft Reset.
TABLE 14. DLL RANGES
.
The output_mode_B and config_status registers are used
in conjunction to enable DDR mode and select the
frequency range of the DLL clock generator. The method
of setting these options is different from the other
registers.
READ
OUTPUT_MODE_B
0x74
READ
CONFIG_STATUS
0x75
DESIRED
VALUE
WRITE TO
0x74
FIGURE 40. SETTING OUTPUT_MODE_B REGISTER
The procedure for setting output_mode_B is shown in
Figure 40. Read the contents of output_mode_B and
config_status and XOR them. Then XOR this result with
the desired value for output_mode_B and write that XOR
result to the register.
Device Test
The ISLA112P25MREP can produce preset or user
defined patterns on the digital outputs to facilitate in-site
23
FN7646.1
November 17, 2011
ISLA112P25M
testing. A static word can be placed on the output bus, or
two different words can alternate. In the alternate mode,
the values defined as Word 1 and Word 2 (as shown in
Table 15) are set on the output bus on alternating clock
phases. The test mode is enabled asynchronously to the
sample clock, therefore several sample clock cycles may
elapse before the data is present on the output bus.
TABLE 15. OUTPUT TEST MODES
VALUE
0xC0[3:0]
OUTPUT TEST
MODE
0000
Off
0001
ADDRESS 0XC0: TEST_IO
Bits 7:6 User Test Mode
These bits set the test mode to static (0x00) or alternate
(0x01) mode. Other values are reserved.
The four LSBs in this register (Output Test Mode)
determine the test pattern in combination with registers
0xC2 through 0xC5. Refer to Table 16.
WORD 1
WORD 2
Midscale
0x8000
N/A
0010
Positive Full-Scale
0xFFFF
N/A
0011
Negative Full-Scale
0x0000
N/A
0100
Checkerboard
0xAAAA
0x5555
0101
Reserved
N/A
N/A
0110
Reserved
N/A
N/A
0111
One/Zero
0xFFFF
0x0000
1000
User Pattern
user_patt1 user_patt2
ADDRESS 0XC2: USER_PATT1_LSB AND
ADDRESS 0XC3: USER_PATT1_MSB
These registers define the lower and upper eight bits,
respectively, of the first user-defined test word.
ADDRESS 0XC4: USER_PATT2_LSB AND
ADDRESS 0XC5: USER_PATT2_MSB
These registers define the lower and upper eight bits,
respectively, of the second user-defined test word.
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
24
FN7646.1
November 17, 2011
ISLA112P25M
SPI Memory Map
Indexed Device Config/Control
Info
SPI Config
TABLE 16. SPI MEMORY MAP
ADDR
(Hex)
PARAMETER
NAME
BIT 7
(MSB)
00
port_config
SDO
Active
01
reserved
Reserved
02
burst_end
Burst end address [7:0]
03-07
reserved
Reserved
08
chip_id
09
chip_version
10
device_index_A
11-1F
reserved
Reserved
20
offset_coarse
Coarse Offset
BIT 5
LSB First
Soft
Reset
BIT 4
Mirror
(bit5)
Mirror
(bit6)
Mirror
(bit7)
DEF. VALUE INDEXED/
(Hex)
GLOBAL
G
Chip ID #
Read only
G
Chip Version #
Read only
G
00h
I
cal. value
I
offset_fine
23
gain_medium
24
gain_fine
25
modes
26-5F
reserved
Reserved
60-6F
reserved
Reserved
reserved
Bit 0
(LSB)
00h
gain_coarse
phase_slip
BIT 1
G
22
71
BIT 2
00h
21
70
BIT 3
Reserved
ADC00
Fine Offset
cal. value
I
cal. value
I
Medium Gain
cal. value
I
Fine Gain
cal. value
I
00h
NOT
affected by
Soft Reset
I
00h
G
Clock Divide [2:0]
000 = Pin Control
001 = divide by 1
010 = divide by 2
100 = divide by 4
other codes = reserved
00h
NOT
affected by
Soft Reset
G
Output Format [2:0]
000 = Pin Control
001 = Twos Complement
010 = Gray Code
100 = Offset Binary
other codes = reserved
00h
NOT
affected by
Soft Reset
G
Reserved
Coarse Gain
Reserved
Power-Down Mode [2:0]
000 = Pin Control
001 = Normal Operation
010 = Nap
100 = Sleep
other codes = reserved
Reserved
Reserved
72
Global Device Config/Control
BIT 6
clock_divide
Output Mode [2:0]
000 = Pin Control
001 = LVDS 2mA
010 = LVDS 3mA
100 = LVCMOS
other codes = reserved
Next
Clock
Edge
73
output_mode_A
74
output_mode_B
DLL Range
0 = fast
1 = slow
DDR
Enable
(Note 16)
00h
NOT
affected by
Soft Reset
G
75
config_status
XOR
Result
XOR
Result
Read Only
G
76-BF
reserved
Reserved
25
FN7646.1
November 17, 2011
ISLA112P25M
TABLE 16. SPI MEMORY MAP (Continued)
PARAMETER
NAME
C0
test_io
Device Test
ADDR
(Hex)
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
User Test Mode
[1:0]
00 = Single
01 = Alternate
10 = Reserved
11 = Reserved
BIT 3
BIT 2
Bit 0
(LSB)
BIT 1
DEF. VALUE INDEXED/
(Hex)
GLOBAL
Output Test Mode [3:0]
0 = Off
1 = Midscale Short
2 = +FS Short
3 = -FS Short
4 = Checker Board
5 = Reserved
6 = Reserved
00h
G
00h
G
7 = One/Zero Word
Toggle
8 = User Input
9-15 = Reserved
C1
Reserved
Reserved
C2
user_patt1_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
G
C3
user_patt1_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
G
C4
user_patt2_lsb
B7
B6
B5
B4
B3
B2
B1
B0
00h
G
C5
user_patt2_msb
B15
B14
B13
B12
B11
B10
B9
B8
00h
G
C6-FF
Reserved
Reserved
NOTE:
16. At power-up, the DDR Enable bit is at a logic ‘0’ for the 72 pin package and set to a logic ‘1’ internally for the 48 pin package by an internal pull-up.
Equivalent Circuits
AVDD
TO
CLOCK-PHASE
GENERATION
AVDD
CLKP
AVDD
CSAMP
1.6pF
TO
CHARGE
PIPELINE
ΦF 3
INP
Ω
1000O
ΦF 2
ΦF 1
CSAMP
1.6pF
AVDD
TO
CHARGE
PIPELINE
ΦF 3
INN
ΦF 2
ΦF 1
AVDD
Ω
11kO
AVDD
FIGURE 42. CLOCK INPUTS
AVDD
(20k PULL-UP
ON RESETN
ONLY)
AVDD
Ω
75kO
AVDD
INPUT
Ω
18kO
Ω
11kO
CLKN
FIGURE 41. ANALOG INPUTS
AVDD
Ω
18kO
TO
SENSE
LOGIC
Ω
75kO
Ω
280O
OVDD
OVDD
OVDD
20kΩ
INPUT
Ω
75kO
Ω
75kO
FIGURE 43. TRI-LEVEL DIGITAL INPUTS
26
280Ω
TO
LOGIC
FIGURE 44. DIGITAL INPUTS
FN7646.1
November 17, 2011
ISLA112P25M
Equivalent Circuits
(Continued)
OVDD
2mA OR
3mA
OVDD
DATA
DATA
D[11:0]P
OVDD
OVDD
OVDD
D[11:0]N
DATA
DATA
DATA
D[11:0]
2mA OR
3mA
FIGURE 46. CMOS OUTPUTS
FIGURE 45. LVDS OUTPUTS
AVDD
VCM
0.535V
+
–
FIGURE 47. VCM_OUT OUTPUT
ADC Evaluation Platform
Clock Input Considerations
Intersil offers an ADC Evaluation platform which can be
used to evaluate the KADxxxxx ADC family. The platform
consists of a FPGA based data capture motherboard and
a family of ADC daughter cards. This USB based platform
allows a user to quickly evaluate the functioning of the
ISLA112P25MREP at room temperature with the
KAD5512P-25Q72 based daughter card at a user’s
specific application frequency requirements. More
information is available at:
http://www.intersil.com/converters/adc_eval_platform/
Use matched transmission lines to the transformer inputs
for the analog input and clock signals. Locate
transformers and terminations as close to the chip as
possible.
Exposed Paddle
Layout Considerations
Bypass and Filtering
Split Ground and Power Planes
Data converters operating at high sampling frequencies
require extra care in PC board layout. Many complex
board designs benefit from isolating the analog and
digital sections. Analog supply and ground planes should
be laid out under signal and clock inputs. Locate the
digital planes under outputs and logic pins. Grounds
should be joined under the chip.
27
The exposed paddle must be electrically connected to
analog ground (AVSS) and should be connected to a
large copper plane using numerous vias for optimal
thermal performance.
Bulk capacitors should have low equivalent series
resistance. Tantalum is a good choice. For best
performance, keep ceramic bypass capacitors very close
to device pins. Longer traces will increase inductance,
resulting in diminished dynamic performance and
accuracy. Make sure that connections to ground are
direct and low impedance. Avoid forming ground loops.
LVDS Outputs
Output traces and connections must be designed for 50Ω
(100Ω differential) characteristic impedance. Keep traces
FN7646.1
November 17, 2011
ISLA112P25M
direct and minimize bends where possible. Avoid crossing
ground and power-plane breaks with signal traces.
transitions to the full-scale voltage less 2 LSB. It is
typically expressed in percent.
LVCMOS Outputs
Integral Non-Linearity (INL) is the maximum
deviation of the ADC’s transfer function from a best fit
line determined by a least squares curve fit of that
transfer function, measured in units of LSBs.
Output traces and connections must be designed for 50Ω
characteristic impedance.
Unused Inputs
Standard logic inputs (RESETN, CSB, SCLK, SDIO, SDO)
which will not be operated do not require connection to
ensure optimal ADC performance. These inputs can be
left floating if they are not used. Tri-level inputs (NAPSLP,
OUTMODE, OUTFMT, CLKDIV) accept a floating input as a
valid state, and therefore should be biased according to
the desired functionality.
Definitions
Analog Input Bandwidth is the analog input frequency
at which the spectral output power at the fundamental
frequency (as determined by FFT analysis) is reduced by
3dB from its full-scale low-frequency value. This is also
referred to as Full Power Bandwidth.
Aperture Delay or Sampling Delay is the time
required after the rise of the clock input for the sampling
switch to open, at which time the signal is held for
conversion.
Aperture Jitter is the RMS variation in aperture delay
for a set of samples.
Clock Duty Cycle is the ratio of the time the clock wave
is at logic high to the total time of one clock period.
Differential Non-Linearity (DNL) is the deviation of
any code width from an ideal 1 LSB step.
Effective Number of Bits (ENOB) is an alternate
method of specifying Signal to Noise-and-Distortion
Ratio (SINAD). In dB, it is calculated as:
ENOB = (SINAD - 1.76)/6.02
Gain Error is the ratio of the difference between the
voltages that cause the lowest and highest code
Least Significant Bit (LSB) is the bit that has the
smallest value or weight in a digital word. Its value in
terms of input voltage is VFS/(2N-1) where N is the
resolution in bits.
Missing Codes are output codes that are skipped and
will never appear at the ADC output. These codes cannot
be reached with any input value.
Most Significant Bit (MSB) is the bit that has the
largest value or weight.
Pipeline Delay is the number of clock cycles between
the initiation of a conversion and the appearance at the
output pins of the data.
Power Supply Rejection Ratio (PSRR) is the ratio of
the observed magnitude of a spur in the ADC FFT, caused
by an AC signal superimposed on the power supply
voltage.
Signal to Noise-and-Distortion (SINAD) is the ratio
of the RMS signal amplitude to the RMS sum of all other
spectral components below one half the clock frequency,
including harmonics but excluding DC.
Signal-to-Noise Ratio (without Harmonics) is the ratio
of the RMS signal amplitude to the RMS sum of all other
spectral components below one-half the sampling
frequency, excluding harmonics and DC.
SNR and SINAD are either given in units of dB when the
power of the fundamental is used as the reference, or
dBFS (dB to full scale) when the converter’s full-scale
input power is used as the reference.
Spurious-Free-Dynamic Range (SFDR) is the ratio of
the RMS signal amplitude to the RMS value of the largest
spurious spectral component. The largest spurious
spectral component may or may not be a harmonic.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
6/25/10
FN7646.0
CHANGE
Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISLA112P25MREP
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
28
FN7646.1
November 17, 2011
ISLA112P25M
Package Outline Drawing
L72.10x10D
72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 11/08
10.00
PIN 1
INDEX AREA
A
4X 8.50
B
55
6
72
1
54
68X 0.50
Exp. DAP
6.00 Sq.
10.00
(4X)
PIN 1
INDEX AREA
6
18
37
0.15
36
19
72X 0.24
72X 0.40
TOP VIEW
4
0.10 M C A B
BOTTOM VIEW
SEE DETAIL "X"
0.90 Max
0.10 C
C
0.08 C
SEATING PLANE
68X 0.50
SIDE VIEW
72X 0.24
9.80 Sq
6.00 Sq
C
0 . 2 REF
5
0 . 00 MIN.
0 . 05 MAX.
72X 0.60
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
29
FN7646.1
November 17, 2011