ISL83202 ® Data Sheet December 20, 2006 FN6382.0 55V, 1A Peak Current H-Bridge FET Driver Features The ISL83202 is a medium-frequency H-Bridge FET driver capable of 1A (typ) of peak drive current that is designed to drive high- and low-side N-Channel MOSFETs in mediumvoltage applications. Optimized for PWM motor control and uninterruptible power supply systems, the ISL83202 enables simple and flexible bridge-based design. With typical inputto-output propagation delays as low as 25ns and with a userprogrammable dead-time range of 0.1µs to 4.5µs, the ISL83202 is ideal for switching frequencies up to 200kHz. • Independently Drives 4 N-Channel FETs in Half Bridge or Full Bridge Configurations The dead-time of the ISL83202 is programmable via a single resistor. The ISL83202's four independent driver control inputs (ALI, AHI, BLI, and BHI) allow driving of every possible switch combination except those that would cause a shoot-through condition. A global disable input, DIS, overrides input control and causes the ISL83202 to refresh the bootstrap capacitor when pulled low. Integrated undervoltage protection and shoot-through protection ensure reliable system operation. The ISL83202 is available in compact 16 Ld SOIC and 16 Ld PDIP packages and operates over the range of -55°C to +125°C. ISL83202IBZ (Note) PART MARKING 83202IBZ TEMP. RANGE (°C) PACKAGE PKG. DWG. # -55 to +125 16 Ld SOIC (N) M16.15 (Pb-free) ISL83202IBZT 16 Ld SOIC (N) Tape and Reel (Note) (Pb-free) M16.15 ISL83202IPZ (Note) E16.3 ISL83202IPZ • Drives a 1000pF Load in Free Air at +50°C with Rise and Fall Times of 15ns (typ) • User-Programmable Dead Time from 0.1 to 4.5μs • DIS (Disable) Overrides Input Control and Refreshes Bootstrap Capacitor when Pulled Low • Input Logic Thresholds Compatible with 5V to 15V Logic Levels • Shoot-Through Protection • Undervoltage Protection • Pb-Free Plus Anneal Available (RoHS Compliant) Applications • UPS Systems • DC Motor Controls • Full Bridge Power Supplies • Switching Power Amplifiers Ordering Information PART NUMBER • Bootstrap Supply Max Voltage: 70VDC -55 to +125 16 Ld PDIP** (Pb-free) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/ JEDEC J STD-020. **Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. • Noise Cancellation Systems • Battery Powered Vehicles • Peripherals • Medium/Large Voice Coil Motors • Related Literature - TB363, Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs) Pinout ISL83202 (PDIP, SOIC) TOP VIEW BHB 1 16 BHO BHI 2 15 BHS BLI 3 14 BLO ALI 4 13 ALO DEL 5 12 VDD 6 11 AHS AHI 7 10 AHO DIS 8 9 AHB VSS 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL83202 Application Block Diagram 55V 12V BHO BHS BHI LOAD BLO BLI ISL83202 ALI ALO AHS AHI AHO GND GND Functional Block Diagram 9 LEVEL SHIFT U/V BHI 2 AHI 7 DIS 8 AHB BHB 1 DRIVER DRIVER LEVEL SHIFT 10 AHO BHO 16 11 AHS U/V BHS 15 TURN-ON DELAY TURN-ON DELAY VDD VDD 12 ALI 4 DEL 5 BLI 3 VSS 6 DETECTOR UNDERVOLTAGE DRIVER TURN-ON DELAY 2 DRIVER 13 ALO BLO 14 TURN-ON DELAY FN6382.0 December 20, 2006 ISL83202 Typical Application (PWM Mode Switching) 55V 12V PWM INPUT DELAY RESISTOR DIS FROM OPTIONAL OVERCURRENT LATCH 1 BHB BHO 16 2 BHI BHS 15 3 BLI BLO 14 4 ALI ALO 13 5 DEL VDD 12 6 VSS AHS 11 7 AHI AHO 10 8 DIS AHB 9 LOAD 12V GND RDIS TO OPTIONAL CURRENT CONTROLLER OR OVERCURRENT LATCH + - RSH GND 3 FN6382.0 December 20, 2006 ISL83202 Absolute Maximum Ratings Thermal Information Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Voltage on AHS, BHS . . . . -6V (Transient) to 65V (-55°C to+150°C) Voltage on AHB, BHB . . . . . . . . VAHS, BHS -0.3V to VAHS, BHS +VDD Voltage on ALO, BLO. . . . . . . . . . . . . . . . . . VSS -0.3V to VDD +0.3V Voltage on AHO, BHO . . . VAHS, BHS -0.3V to VAHB, BHB +0.3V Input Current, DEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5mA to 0mA Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns NOTE: All voltages are relative VSS unless otherwise specified. Thermal Resistance θJA (°C/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Maximum Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . See Curve Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Operating Max. Junction Temperature. . . . . . . . . . . . . . . . . . +150°C Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300°C (For SOIC - Lead Tips Only)) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Operating Conditions Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . +8.5V to +15V Voltage on VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +1.0V Voltage on AHB, BHB . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +55V Voltage on AHB, BHB . . . . . . . . VAHS, BHS +7.5V to VAHS, BHS +VDD Input Current, DEL . . . . . . . . . . . . . . . . . . . . . . . . . -4mA to -100μA CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. +150°C max junction temperature is intended for short periods of time to prevent shortening the lifetime. Operation close to +150°C junction may trigger the shutdown of the device even before +150°C, since this number is specified as typical. Electrical Specifications VDD = VAHB = VBHB = 12V, VSS = VAHS = VBHS = 0V, RDEL = 100k TJ = -55°C TO +150°C TJ = +25°C PARAMETER MIN TYP MAX MIN All inputs = 0V, RDEL = 100k 1.2 2.3 3.5 0.85 4 mA All inputs = 0V, RDEL = 10k 2.2 4.0 5.5 1.9 6.0 mA SYMBOL TEST CONDITIONS MAX UNITS SUPPLY CURRENTS AND UNDER VOLTAGE PROTECTION VDD Quiescent Current IDD VDD Operating Current IDDO f = 50kHz, no load 1.5 2.6 4.0 1.1 4.2 mA 50kHz, no load, RDEL = 10kΩ 2.5 4.0 6.4 2.1 6.6 mA AHB, BHB Off Quiescent Current IAHBL, IBHBL AHI = BHI = 0V 0.5 1.0 1.5 0.4 1.6 mA AHB, BHB On Quiescent Current IAHBH, IBHBH AHI = BHI = VDD 65 145 240 40 250 μA AHB, BHB Operating Current IAHBO, IBHBO f = 50kHz, CL = 1000pF .65 1.1 1.8 .45 2.0 mA AHS, BHS Leakage Current IHLK - - 1.0 - - μA VAHS = VBHS = 55V VAHB = VBHB = 70V VDD = Not Connected VDD Rising Undervoltage Threshold VDDUV+ 6.8 7.6 8.25 6.5 8.5 V VDD Falling Undervoltage Threshold VDDUV- 6.5 7.1 7.8 6.25 8.1 V Undervoltage Hysteresis UVHYS AHB, BHB Undervoltage Threshold VHBUV 0.17 0.4 0.75 0.15 0.90 V Referenced to AHS and BHS 5 6.0 7 4.5 7.5 V - 1.0 - 0.8 V INPUT PINS: ALI, BLI, AHI, BHI, and DIS Low Level Input Voltage VIL Full Operating Conditions - High Level Input Voltage VIH Full Operating Conditions 2.5 - - 2.7 - 35 - - - mV Input Voltage Hysteresis V Low Level Input Current IIL VIN = 0V, Full Operating Conditions -145 -100 -60 -150 -50 μA High Level Input Current IIH VIN = 5V, Full Operating Conditions -1 - +1 -10 +10 μA RDEL = 100k 2.5 4.5 8.0 2.0 8.5 μs RDEL = 10k 0.27 0.5 0.75 0.2 0.85 μs TURN-ON DELAY PIN DEL Dead Time TDEAD 4 FN6382.0 December 20, 2006 ISL83202 Electrical Specifications VDD = VAHB = VBHB = 12V, VSS = VAHS = VBHS = 0V, RDEL = 100k (Continued) TJ = -55°C TO +150°C TJ = +25°C PARAMETER SYMBOL MIN TEST CONDITIONS TYP MAX MIN MAX UNITS GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, and BHO Low Level Output Voltage VOL IOUT = 50mA 0.65 1.1 0.5 1.2 V High Level Output Voltage VDD-VOH IOUT = -50mA 0.7 1.2 0.5 1.3 V Peak Pullup Current IO + VOUT = 0V 1.0 0.6 2.0 A Peak Pulldown Current IO - VOUT = 12V 1.0 0.6 2.0 A Switching Specifications VDD = VAHB = VBHB = 12V, VSS = VAHS = VBHS = 0V, RDEL= 100k, CL = 1000pF. TJ = -55°C TO +150°C TJ = +25°C PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS Lower Turn-off Propagation Delay (ALI-ALO, BLI-BLO) TLPHL - 25 50 - 70 ns Upper Turn-off Propagation Delay (AHI-AHO, BHI-BHO) THPHL - 55 80 - 100 ns Lower Turn-on Propagation Delay (ALI-ALO, BLI-BLO) TLPLH - 40 85 - 100 ns Upper Turn-on Propagation Delay (AHI-AHO, BHI-BHO) THPLH - 75 110 - 150 ns Rise Time TR - 9 20 - 25 ns Fall Time TF - 9 20 - 25 ns TPWIN-ON/OFF 50 - - 50 - ns 80 ns Minimum Input Pulse Width Output Pulse Response to 50ns Input Pulse 63 TPWOUT Disable Turn-off Propagation Delay (DIS - Lower Outputs) TDISLOW - 50 80 - 90 ns Disable Turn-off Propagation Delay (DIS - Upper Outputs) TDISHIGH - 75 100 - 125 ns Disable Turn-on Propagation Delay (DIS - ALO and BLO) TDLPLH - 40 70 - 100 ns Disable Turn-on Propagation Delay (DIS- AHO and BHO) TDHPLH - 1.2 2 - 3 μs Refresh Pulse Width (ALO and BLO) TREF-PW 375 580 900 350 950 ns RDEL = 10k TRUTH TABLE INPUT OUTPUT ALI, BLI AHI, BHI VDDUV VHBUV DIS ALO, BLO AHO, BHO X X X X 1 0 0 X X 1 X X 0 0 0 X 0 1 0 0 0 1 X 0 X 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 NOTE: X signifies that input can be either a “1” or “0”. 5 FN6382.0 December 20, 2006 ISL83202 Pin Descriptions PIN NUMBE R SYMBOL DESCRIPTION 1 BHB B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. 2 BHI B High-side Input. Logic level input that controls BHO driver (Pin 16). BLI (Pin 3) high level input overrides BHI high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 8) high level input overrides BHI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). 3 BLI B Low-side Input. Logic level input that controls BLO driver (Pin 14). If BHI (Pin 2) is driven high or not connected externally then BLI controls both BLO and BHO drivers, with dead time set by delay currents at DEL (Pin 5). DIS (Pin 8) high level input overrides BLI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). 4 ALI A Low-side Input. Logic level input that controls ALO driver (Pin 13). If AHI (Pin 7) is driven high or not connected externally then ALI controls both ALO and AHO drivers, with dead time set by delay currents at DEL (Pin 5). DIS (Pin 8) high level input overrides ALI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). 5 DEL Turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the dead time between drivers. All drivers turn-off with no adjustable delay, so the DEL resistor guarantees no shoot-through by delaying the turn-on of all drivers. The voltage across the DEL resistor is approximately VDD -2V. 6 VSS Chip negative supply, generally will be ground. 7 AHI A High-side Input. Logic level input that controls AHO driver (Pin 10). ALI (Pin 4) high level input overrides AHI high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 8) high level input overrides AHI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). 8 DIS DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs. When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). 9 AHB A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. 10 AHO A High-side Output. Connect to gate of A High-side power MOSFET. 11 AHS A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. 12 VDD Positive supply to control logic and lower gate drivers. De-couple this pin to VSS (Pin 6). 13 ALO A Low-side Output. Connect to gate of A Low-side power MOSFET. 14 BLO B Low-side Output. Connect to gate of B Low-side power MOSFET. 15 BHS B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. 16 BHO B High-side Output. Connect to gate of B High-side power MOSFET. 6 FN6382.0 December 20, 2006 ISL83202 Timing Diagrams X = A OR B, A AND B HALVES OF BRIDGE CONTROLLER ARE INDEPENDENT TLPHL THPHL DIS=0 and UV XLI XHI XLO XHO THPLH TLPLH TR (10% - 90%) TF (10% - 90%) FIGURE 1. INDEPENDENT MODE DIS=0 and UV XLI XHI = HI OR NOT CONNECTED XLO XHO FIGURE 2. BISTATE MODE TDLPLH DIS or UV TDIS TREF-PW XLI XHI XLO XHO TDHPLH FIGURE 3. DISABLE FUNCTION 7 FN6382.0 December 20, 2006 ISL83202 Performance Curves 16 3.5 200kHz VDD = 16V 3 IDD SUPPLY CURRENT (mA) IDD SUPPLY CURRENT (mA) 15 3.25 VDD = 15V 2.75 2.5 VDD = 12V 2.25 VDD = 10V 2 VDD = 8V 1.75 1.5 -60 14 13 12 11 10 8 -20 50kHz 7 6 10kHz 5 4 -40 100kHz 9 0 20 40 60 80 100 JUNCTION TEMPERATURE (°C) 120 140 -60 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (°C) 120 140 FIGURE 5. VDD SUPPLY CURRENT vs TEMPERATURE AND SWITCHING FREQUENCY (1000pF LOAD) FIGURE 4. IDD SUPPLY CURRENT vs TEMPERATURE AND VDD SUPPLY VOLTAGE 2 8 7 PEAK GATE CURRENT (A) LOADED, NL BIAS CURRENTS (mA) -40 6 5 4 1000pF LOAD 3 NO LOAD 2 1.75 1.5 1.25 SOURCE and SINK 1 0.75 1 0.5 0 0 50 100 FREQUENCY (kHz) 150 8 9 200 FIGURE 6. FLOATING (IXHB) BIAS CURRENT vs FREQUENCY AND LOAD 10 11 12 13 14 BIAS BIAS SUPPLY VOLTAGE (V) AT +25°C 15 FIGURE 7. GATE SOURCE/SINK PEAK CURRENT vs BIAS SUPPLY VOLTAGE AT +25°C 1.2 -40°C 1.1 -55°C 1.2 VDD-VOH (V) NORMALIZED GATE SINK/SOURCE CURRENT (A) 1.4 1 0°C +25°C 1 +125°C +150°C 0.8 0.9 0.6 0.8 -75 -50 -25 0 25 50 75 100 JUNCTION TEMPERATURE (°C) FIGURE 8. GATE CURRENT vs TEMPERATURE, NORMALIZED TO +25°C 8 125 150 8 9 10 11 12 13 VDD SUPPLY VOLTAGE (V) 14 15 FIGURE 9. VDD-VOH vs BIAS VOLTAGE TEMPERATURE FN6382.0 December 20, 2006 ISL83202 Performance Curves (Continued) 8 VDD, BIAS SUPPLY VOLTAGE (V) 1.4 VOL (V) 1.2 -40°C -55°C 0°C +25°C 1 0.8 +125°C +150°C 0.6 8 9 10 11 12 13 VDD SUPPLY VOLTAGE (V) 14 LOWER U/V SET 6.5 6 UPPER U/V SET/RESET 5.5 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (°C) DIS TO TURN-ON/OFF TIME (ns) 80 UPPER tON 70 60 UPPER tOFF LOWER tON 50 40 30 LOWER tOFF DISHTON 1000 DISHTOFF 100 DISLOFF DISLTON 20 -60 -40 -20 0 20 40 60 80 100 120 10 140 160 -60 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (°C) JUNCTION TEMPERATURE (°C) FIGURE 12. UPPER LOWER TURN-ON / TURN-OFF PROPAGATION DELAY vs TEMPERATURE 120 140 160 FIGURE 13. UPPER/LOWER DIS(ABLE) TO TURN-ON/OFF vs TEMPERATURE (°C) 2 2.5 TOTAL POWER DISSIPATION (W) LEVEL-SHIFT CURRENT (mA) 140 160 104 90 1.5 1 0.5 120 FIGURE 11. UNDERVOLTAGE TRIP VOLTAGES vs TEMPERATURE 100 PROPAGATION DELAYS (ns) 7 5 -60 15 FIGURE 10. VOL vs BIAS VOLTAGE AND TEMPERATURE LOWER U/V RESET 7.5 0 20 40 60 80 SWITCHING FREQUENCY (kHz) FIGURE 14. FULL BRIDGE LEVEL-SHIFT CURRENT vs FREQUENCY (kHz) 9 100 2 16 PIN DIP 1.5 SOIC 1 0.5 QUIESCENT BIAS COMPONENT 0 -60 -30 0 30 60 90 AMBIENT TEMPERATURE (°C) 120 150 FIGURE 15. MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE FN6382.0 December 20, 2006 ISL83202 Performance Curves (Continued) 104 DEAD TIME (ns) VDD = 15V VDD = 12V VDD = 9V 1000 100 0 10 20 30 40 50 60 70 DEAD TIME RESISTANCE (kΩ) 80 90 100 FIGURE 16. DEAD-TIME vs DEL RESISTANCE AND BIAS SUPPLY (VDD) VOLTAGE 10 FN6382.0 December 20, 2006 ISL83202 Dual-In-Line Plastic Packages (PDIP) E16.3 (JEDEC MS-001-BB ISSUE D) N E1 INDEX AREA 1 2 3 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE N/2 INCHES -B- SYMBOL -AE D BASE PLANE -C- A2 SEATING PLANE A L D1 e B1 D1 eA A1 eC B 0.010 (0.25) M C L C A B S C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. MILLIMETERS MIN MAX MIN MAX A - A1 0.015 NOTES 0.210 - 5.33 4 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 0.355 - D 0.735 0.775 18.66 19.68 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. eA 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. L 0.115 0.150 2.93 3.81 4 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . N 16 16 9 Rev. 0 12/93 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 11 FN6382.0 December 20, 2006 ISL83202 Small Outline Plastic Packages (SOIC) M16.15 (JEDEC MS-012-AC ISSUE C) N INDEX AREA H 0.25(0.010) M 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE B M INCHES E -B1 2 3 L SEATING PLANE -A- A D h x 45° -C- e A1 B C 0.10(0.004) 0.25(0.010) M C A M SYMBOL MIN MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.3859 0.3937 9.80 10.00 3 E 0.1497 0.1574 3.80 4.00 4 e α B S 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N α NOTES: MILLIMETERS 16 0° 16 8° 0° 7 8° 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. Rev. 1 6/05 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 FN6382.0 December 20, 2006