HIP4081A 80V/2.5A Peak, High Frequency Full Bridge FET Driver November 1996 Features Description • Independently Drives 4 N-Channel FET in Half Bridge or Full Bridge Configurations The HIP4081A is a high frequency, medium voltage Full Bridge N-Channel FET driver IC, available in 20 lead plastic SOIC and DIP packages. The HIP4081A can drive every possible switch combination except those which would cause a shoot-through condition. The HIP4081A can switch at frequencies up to 1MHz and is well suited to driving Voice Coil Motors, high-frequency Class D audio amplifiers, and power supplies. • Bootstrap Supply Max Voltage to 95VDC • Drives 1000pF Load at 1MHz in Free Air at 50oC with Rise and Fall Times of Typically 10ns • User-Programmable Dead Time • On-Chip Charge-Pump and Bootstrap Upper Bias Supplies For example, the HIP4081A can drive medium voltage brush motors, and two HIP4081As can be used to drive high performance stepper motors, since the short minimum “on-time” can provide fine micro-stepping capability. • DIS (Disable) Overrides Input Control • Input Logic Thresholds Compatible with 5V to 15V Logic Levels Short propagation delays of approximately 55ns maximizes control loop crossover frequencies and dead-times which can be adjusted to near zero to minimize distortion, resulting in rapid, precise control of the driven load. • Very Low Power Consumption • Undervoltage Protection Applications A similar part, the HIP4080A, includes an on-chip input comparator to create a PWM signal from an external triangle wave and to facilitate “hysteresis mode” switching. • Medium/Large Voice Coil Motors • Full Bridge Power Supplies The Application Note for the HIP4081A is the AN9405. • Class D Audio Power Amplifiers Ordering Information • High Performance Motor Controls PART NUMBER TEMP RANGE (oC) • Battery Powered Vehicles HIP4081AIP -40 to 85 20 Ld PDIP E20.3 • Peripherals HIP4081AIB -40 to 85 20 Ld SOIC (W) M20.3 • Noise Cancellation Systems PACKAGE PKG. NO. • U.P.S. Pinout Application Block Diagram 80V HIP4081A (PDIP, SOIC) TOP VIEW BHB 1 20 BHO BHI 2 19 BHS DIS 3 18 BLO VSS 4 17 BLS 12V BHO BHS BLI 5 16 VDD BHI ALI 6 15 VCC BLI AHI 7 14 ALS HDEL 8 13 ALO LDEL 9 12 AHS AHB 10 11 AHO LOAD BLO HIP4081A ALI ALO AHS AHI AHO GND GND CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 1 File Number 3659.5 HIP4081A Functional Block Diagram (1/2 HIP4081A) HIGH VOLTAGE BUS ≤ 80VDC AHB 10 UNDERVOLTAGE CHARGE PUMP LEVEL SHIFT AND LATCH DRIVER CBS AHS VDD 16 AHI AHO 11 12 7 TURN-ON DELAY TO VDD (PIN 16) DBS DIS 3 15 DRIVER ALI TURN-ON DELAY 6 VCC ALO 13 CBF ALS 14 HDEL 8 LDEL 9 VSS 4 Typical Application (PWM Mode Switching) 80V 2 BHI DIS 3 DIS BHO 20 HIP4081/HIP4081A 1 BHB 12V 4 VSS PWM INPUT 5 BLI 6 ALI 7 AHI 8 HDEL BHS 19 LOAD BLO 18 BLS 17 VDD 16 VCC 15 12V ALS 14 ALO 13 9 LDEL AHS 12 10 AHB AHO 11 GND - TO OPTIONAL CURRENT CONTROLLER + 6V GND 2 +12VDC BIAS SUPPLY HIP4081A Absolute Maximum Ratings Thermal Information Supply Voltage, VDD and VCC. . . . . . . . . . . . . . . . . . . . -0.3V to 16V Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Voltage on AHS, BHS . . . . -6.0V (Transient) to 80V (25oC to 125oC) Voltage on AHS, BHS . . . -6.0V (Transient) to 70V (-55oC to 125oC) Voltage on ALS, BLS . . . . . . . -2.0V (Transient) to +2.0V (Transient) Voltage on AHB, BHB . . . . . . . . . VAHS, BHS -0.3V to VAHS, BHS +VDD Voltage on ALO, BLO . . . . . . . . . . . . . VALS, BLS -0.3V to VCC +0.3V Voltage on AHO, BHO . . . . . . . VAHS, BHS -0.3V to VAHB, BHB +0.3V Input Current, HDEL and LDEL . . . . . . . . . . . . . . . . . . -5mA to 0mA Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns NOTE: All Voltages relative to VSS, unless otherwise specified. Thermal Resistance (Typical, Note 1) θJA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Storage Temperature Range . . . . . . . . . . . . . . . . . . . -65oC to 150oC Operating Max. Junction Temperature . . . . . . . . . . . . . . . . . . 125oC Lead Temperature (Soldering 10s)) . . . . . . . . . . . . . . . . . . . . 300oC (For SOIC - Lead Tips Only CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Operating Conditions Supply Voltage, VDD and VCC. . . . . . . . . . . . . . . . . . . +9.5V to +15V Voltage on ALS, BLS . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +1.0V Voltage on AHB, BHB . . . . . . . . . . VAHS, BHS +5V to VAHS, BHS +15V Electrical Specifications Input Current, HDEL and LDEL. . . . . . . . . . . . . . . . -500µA to -50µA Operating Ambient Temperature Range . . . . . . . . . . . -40oC to 85oC VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified TJ = PARAMETER SYMBOL TEST CONDITIONS TJS = -40oC TO 125oC 25oC MIN TYP MAX MIN MAX UNITS All inputs = 0V 8.5 10.5 14.5 7.5 14.5 mA Outputs switching f = 500kHz SUPPLY CURRENTS AND CHARGE PUMPS VDD Quiescent Current IDD VDD Operating Current IDDO VCC Quiescent Current ICC VCC Operating Current ICCO AHB, BHB Quiescent Current Qpump Output Current AHB, BHB Operating Current AHS, BHS, AHB, BHB Leakage Current AHB-AHS, BHB-BHS Qpump Output Voltage IAHB, IBHB 9.5 12.5 15.5 8.5 15.5 mA All Inputs = 0V, IALO = IBLO = 0 - 0.1 10 - 20 µA f = 500kHz, No Load 1 1.25 2.0 0.8 3 mA -50 -30 -11 -60 -10 µA 0.6 1.2 1.5 0.5 1.9 mA - 0.02 1.0 - 10 µA IAHB = IAHB = 0, No Load 11.5 12.6 14.0 10.5 14.5 V All Inputs = 0V, IAHO = IBHO = 0 VDD = VCC = VAHB = VBHB = 10V IAHBO, IBHBO f = 500kHz, No Load IHLK VAHB-VAHS VBHB-VBHS VBHS = VAHS = 80V, VAHB = VBHB = 93V INPUT PINS: ALI, BLI, AHI, BHI, AND DIS Low Level Input Voltage VIL Full Operating Conditions - - 1.0 - 0.8 V High Level Input Voltage VIH Full Operating Conditions 2.5 - - 2.7 - V - 35 - - - mV Low Level Input Current IIL VIN = 0V, Full Operating Conditions -130 -100 -75 -135 -65 µA High Level Input Current IIH VIN = 5V, Full Operating Conditions -1 - +1 -10 +10 µA 4.9 5.1 5.3 4.8 5.4 V Input Voltage Hysteresis TURN-ON DELAY PINS: LDEL AND HDEL LDEL, HDEL Voltage VHDEL, VLDEL IHDEL = ILDEL = -100µA GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, AND BHO Low Level Output Voltage VOL IOUT = 100mA 0.7 0.85 1.0 0.5 1.1 V High Level Output Voltage VCC-VOH IOUT = -100mA 0.8 0.95 1.1 0.5 1.2 V Peak Pullup Current IO+ VOUT = 0V 1.7 2.6 3.8 1.4 4.1 A Peak Pulldown Current I O- VOUT = 12V 1.7 2.4 3.3 1.3 3.6 A 3 HIP4081A Electrical Specifications VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified (Continued) TJS = -40oC TO 125oC TJ = 25oC PARAMETER SYMBOL MIN TYP MAX MIN MAX UNITS Undervoltage, Rising Threshold UV+ 8.1 8.8 9.4 8.0 9.5 V Undervoltage, Falling Threshold UV- 7.6 8.3 8.9 7.5 9.0 V Undervoltage, Hysteresis HYS 0.25 0.4 0.65 0.2 0.7 V Switching Specifications TEST CONDITIONS VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K, CL = 1000pF. TJS = -40oC TO 125oC TJ = 25oC PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX MIN MAX UNITS Lower Turn-off Propagation Delay (ALI-ALO, BLI-BLO) TLPHL - 30 60 - 80 ns Upper Turn-off Propagation Delay (AHI-AHO, BHI-BHO) THPHL - 35 70 - 90 ns Lower Turn-on Propagation Delay (ALI-ALO, BLI-BLO) TLPLH RHDEL = RLDEL = 10K - 45 70 - 90 ns Upper Turn-on Propagation Delay (AHI-AHO, BHI-BHO) THPLH RHDEL = RLDEL = 10K - 60 90 - 110 ns Rise Time TR - 10 25 - 35 ns Fall Time TF - 10 25 - 35 ns Turn-on Input Pulse Width TPWIN-ON RHDEL = RLDEL = 10K 50 - - 50 - ns Turn-off Input Pulse Width TPWIN-OFF RHDEL = RLDEL = 10K 40 - - 40 - ns Turn-on Output Pulse Width TPWOUT-ON RHDEL = RLDEL = 10K 40 - - 40 - ns Turn-off Output Pulse Width TPWOUT-OFF RHDEL = RLDEL = 10K 30 - - 30 - ns Disable Turn-off Propagation Delay (DIS - Lower Outputs) TDISLOW - 45 75 - 95 ns Disable Turn-off Propagation Delay (DIS - Upper Outputs) TDISHIGH - 55 85 - 105 ns Disable to Lower Turn-on Propagation Delay (DIS - ALO and BLO) TDLPLH - 40 70 - 90 ns Refresh Pulse Width (ALO and BLO) TREF-PW 240 410 550 200 600 ns TUEN - 450 620 - 690 ns Disable to Upper Enable (DIS - AHO and BHO) TRUTH TABLE INPUT NOTE: OUTPUT ALI, BLI AHI, BHI U/V DIS ALO, BLO AHO, BHO X X X 1 0 0 1 X 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 X X 1 X 0 0 X signifies that input can be either a “1” or “0”. 4 HIP4081A Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION 1 BHB B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30µA out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V. 2 BHI B High-side Input. Logic level input that controls BHO driver (Pin 20). BLI (Pin 5) high level input overrides BHI high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides BHI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). An internal 100µA pull-up to VDD will hold BHI high, so no connection is required if high-side and low-side outputs are to be controlled by the low-side input. 3 DIS DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs. When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). An internal 100µA pull-up to VDD will hold DIS high if this pin is not driven. 4 VSS Chip negative supply, generally will be ground. 5 BLI B Low-side Input. Logic level input that controls BLO driver (Pin 18). If BHI (Pin 2) is driven high or not connected externally then BLI controls both BLO and BHO drivers, with dead time set by delay currents at HDEL and LDEL (Pin 8 and 9). DIS (Pin 3) high level input overrides BLI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). An internal 100µA pull-up to VDD will hold BLI high if this pin is not driven. 6 ALI A Low-side Input. Logic level input that controls ALO driver (Pin 13). If AHI (Pin 7) is driven high or not connected externally then ALI controls both ALO and AHO drivers, with dead time set by delay currents at HDEL and LDEL (Pin 8 and 9). DIS (Pin 3) high level input overrides ALI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). An internal 100µA pull-up to VDD will hold ALI high if this pin is not driven. 7 AHI A High-side Input. Logic level input that controls AHO driver (Pin 11). ALI (Pin 6) high level input overrides AHI high level input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 3) high level input overrides AHI high level input. The pin can be driven by signal levels of 0V to 15V (no greater than VDD). An internal 100µA pull-up to VDD will hold AHI high, so no connection is required if high-side and low-side outputs are to be controlled by the low-side input. 8 HDEL High-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of both high-side drivers. The low-side drivers turn-off with no adjustable delay, so the HDEL resistor guarantees no shoot-through by delaying the turn-on of the high-side drivers. HDEL reference voltage is approximately 5.1V. 9 LDEL Low-side turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the turn-on delay of both low-side drivers. The high-side drivers turn-off with no adjustable delay, so the LDEL resistor guarantees no shoot-through by delaying the turn-on of the low-side drivers. LDEL reference voltage is approximately 5.1V. 10 AHB A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Internal charge pump supplies 30µA out of this pin to maintain bootstrap supply. Internal circuitry clamps the bootstrap supply to approximately 12.8V. 11 AHO A High-side Output. Connect to gate of A High-side power MOSFET. 12 AHS A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. 13 ALO A Low-side Output. Connect to gate of A Low-side power MOSFET. 14 ALS A Low-side Source connection. Connect to source of A Low-side power MOSFET. 15 VCC Positive supply to gate drivers. Must be same potential as VDD (Pin 16). Connect to anodes of two bootstrap diodes. 16 VDD Positive supply to lower gate drivers. Must be same potential as VCC (Pin 15). De-couple this pin to VSS (Pin 4). 17 BLS B Low-side Source connection. Connect to source of B Low-side power MOSFET. 18 BLO B Low-side Output. Connect to gate of B Low-side power MOSFET. 19 BHS B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. 20 BHO B High-side Output. Connect to gate of B High-side power MOSFET. 5 HIP4081A Timing Diagrams X = A OR B, A AND B HALVES OF BRIDGE CONTROLLER ARE INDEPENDENT TLPHL THPHL U/V = DIS = 0 XLI XHI XLO XHO THPLH TLPLH TR (10% - 90%) FIGURE 1. INDEPENDENT MODE U/V = DIS = 0 XLI XHI = HI OR NOT CONNECTED XLO XHO FIGURE 2. BISTATE MODE TDLPLH TDIS U/V OR DIS TREF-PW XLI XHI XLO XHO TUEN FIGURE 3. DISABLE FUNCTION 6 TF (10% - 90%) HIP4081A Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified 11.0 14.0 IDD SUPPLY CURRENT (mA) IDD SUPPLY CURRENT (mA) 10.5 12.0 10.0 8.0 6.0 4.0 10.0 9.5 9.0 8.5 8.0 2.0 6 8 10 12 VDD SUPPLY VOLTAGE (V) 0 14 100 200 300 400 500 600 700 800 900 1000 SWITCHING FREQUENCY (kHz) FIGURE 5. IDDO, NO-LOAD IDD SUPPLY CURRENT vs FREQUENCY (kHz) FIGURE 4. QUIESCENT IDD SUPPLY CURRENT vs VDD SUPPLY VOLTAGE 5.0 125oC 25.0 ICC SUPPLY CURRENT (mA) FLOATING SUPPLY BIAS CURRENT (mA) 30.0 20.0 15.0 10.0 5.0 0.0 75oC 4.0 25oC 0oC 3.0 -40oC 2.0 1.0 0.0 0 100 200 300 400 500 600 700 800 900 1000 0 100 200 SWITCHING FREQUENCY (kHz) 300 400 500 600 700 800 900 1000 SWITCHING FREQUENCY (kHz) FIGURE 6. SIDE A, B FLOATING SUPPLY BIAS CURRENT vs FREQUENCY (LOAD = 1000pF) FIGURE 7. ICCO, NO-LOAD ICC SUPPLY CURRENT vs FREQUENCY (kHz) TEMPERATURE 2.5 LOW LEVEL INPUT CURRENT (µA) FLOATING SUPPLY BIAS CURRENT (mA) -90 2 1.5 1 0.5 0 400 200 600 800 SWITCHING FREQUENCY (kHz) -100 -110 -120 -50 1000 FIGURE 8. IAHB, IBHB, NO-LOAD FLOATING SUPPLY BIAS CURRENT vs FREQUENCY -25 0 25 50 75 JUNCTION TEMPERATURE (oC) 100 125 FIGURE 9. ALI, BLI, AHI, BHI LOW LEVEL INPUT CURRENT IIL vs TEMPERATURE 7 HIP4081A VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K and TA = 25oC, Unless Otherwise Specified 80 15.0 14.0 PROPAGATION DELAY (ns) NO-LOAD FLOATING CHARGE PUMP VOLTAGE (V) Typical Performance Curves 13.0 12.0 11.0 10.0 -40 -20 0 20 40 60 80 100 70 60 50 40 30 -40 120 -20 0 JUNCTION TEMPERATURE (oC) FIGURE 10. AHB - AHS, BHB - BHS NO-LOAD CHARGE PUMP VOLTAGE vs TEMPERATURE 60 80 100 120 80 PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) 40 FIGURE 11. UPPER DISABLE TURN-OFF PROPAGATION DELAY TDISHIGH vs TEMPERATURE 525 500 475 450 425 -50 20 JUNCTION TEMPERATURE (oC) -25 0 25 50 75 100 70 60 50 40 30 -40 125 150 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (oC) JUNCTION TEMPERATURE (oC) FIGURE 12. DISABLE TO UPPER ENABLE, TUEN, PROPAGATION DELAY vs TEMPERATURE FIGURE 13. LOWER DISABLE TURN-OFF PROPAGATION DELAY TDISLOW vs TEMPERATURE 80 450 PROPAGATION DELAY (ns) REFRESH PULSE WIDTH (ns) 70 425 400 375 60 50 40 30 350 -50 -25 0 25 50 75 100 20 125 150 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (oC) JUNCTION TEMPERATURE (oC) FIGURE 14. TREF-PW REFRESH PULSE WIDTH vs TEMPERATURE FIGURE 15. DISABLE TO LOWER ENABLE TDLPLH PROPAGATION DELAY vs TEMPERATURE 8 120 HIP4081A VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K and TA = 25oC, Unless Otherwise Specified (Continued) 80 80 70 70 PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) Typical Performance Curves 60 50 40 30 60 50 40 30 20 -40 -20 0 20 40 60 80 100 20 -40 120 -20 JUNCTION TEMPERATURE (oC) 40 60 80 100 120 FIGURE 17. UPPER TURN-ON PROPAGATION DELAY THPLH vs TEMPERATURE 80 80 70 70 PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) 20 JUNCTION TEMPERATURE (oC) FIGURE 16. UPPER TURN-OFF PROPAGATION DELAY THPHL vs TEMPERATURE 60 50 40 30 60 50 40 30 20 20 -40 -20 0 20 40 60 80 100 120 -40 -20 JUNCTION TEMPERATURE (oC) 12.5 12.5 TURN-ON RISE TIME (ns) 13.5 11.5 10.5 9.5 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (oC) 20 40 60 80 100 120 FIGURE 19. LOWER TURN-ON PROPAGATION DELAY TLPLH vs TEMPERATURE 13.5 8.5 -40 0 JUNCTION TEMPERATURE (oC) FIGURE 18. LOWER TURN-OFF PROPAGATION DELAY TLPHL vs TEMPERATURE GATE DRIVE FALL TIME (ns) 0 11.5 10.5 9.5 8.5 -40 120 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (oC) FIGURE 20. GATE DRIVE FALL TIME TF vs TEMPERATURE FIGURE 21. GATE DRIVE RISE TIME TR vs TEMPERATURE 9 HIP4081A Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified 1500 1250 5.5 VCC - VOH (mV) HDEL, LDEL INPUT VOLTAGE (V) 6.0 5.0 750 -40oC 0oC 500 25oC 4.5 250 4.0 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (oC) 75oC 125oC 0 10 120 FIGURE 22. VLDEL, VHDEL VOLTAGE vs TEMPERATURE 12 BIAS SUPPLY VOLTAGE (V) 14 FIGURE 23. HIGH LEVEL OUTPUT VOLTAGE VCC - VOH vs BIAS SUPPLY AND TEMPERATURE AT 100mA 3.5 GATE DRIVE SINK CURRENT (A) 1500 1250 1000 VOL (mV) 1000 750 -40oC 500 0oC 25oC 250 75oC 3.0 2.5 2.0 1.5 1.0 0.5 125oC 0.0 0 10 6 12 14 BIAS SUPPLY VOLTAGE (V) FIGURE 24. LOW LEVEL OUTPUT VOLTAGE VOL vs BIAS SUPPLY AND TEMPERATURE AT 100mA 8 9 10 11 12 13 VDD , VCC, VAHB , VBHB (V) 14 15 16 FIGURE 25. PEAK PULLDOWN CURRENT IO vs BIAS SUPPLY VOLTAGE 3.5 500 LOW VOLTAGE BIAS CURRENT (mA) GATE DRIVE SINK CURRENT (A) 7 3.0 2.5 2.0 1.5 1.0 0.5 200 10,000pF 100 3,000pF 50 1,000pF 20 100pF 10 5 2 1 0.5 0.2 0.0 6 7 8 9 10 11 12 13 14 15 0.1 16 1 VDD, VCC, VAHB, VBHB (V) 2 5 10 20 50 100 200 500 1000 SWITCHING FREQUENCY (kHz) FIGURE 26. PEAK PULLUP CURRENT IO+ vs BIAS SUPPLY VOLTAGE FIGURE 27. LOW VOLTAGE BIAS CURRENT IDD (LESS QUIESCENT COMPONENT) vs FREQUENCY AND GATE LOAD CAPACITANCE 10 HIP4081A Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified (Continued) 1000 LEVEL-SHIFT CURRENT (µA) 500 200 100 50 20 10 10 20 50 100 200 500 1000 SWITCHING FREQUENCY (kHz) FIGURE 28. HIGH VOLTAGE LEVEL-SHIFT CURRENT vs FREQUENCY AND BUS VOLTAGE BIAS SUPPLY VOLTAGE, VDD (V) 9.0 UV+ 8.8 8.6 UV8.4 8.2 50 25 0 25 50 TEMPERATURE 75 100 125 150 (oC) FIGURE 29. UNDERVOLTAGE LOCKOUT vs TEMPERATURE 150 DEAD-TIME (ns) 120 90 60 30 0 10 50 100 150 200 HDEL/LDEL RESISTANCE (kΩ) 250 FIGURE 30. MINIMUM DEAD-TIME vs DEL RESISTANCE 11 IN2 IN1 POWER SECTION +12V B+ Q1 1 R29 JMPR1 2 U2 + C6 JMPR5 CONTROL LOGIC SECTION JMPR2 12 U2 IN+/ALI CD4069UB 5 JMPR3 HEN/BHI 6 U2 CD4069UB JMPR4 10 U2 IN-/AHI 2 12 CW CD4069UB 6 IN+/ALI 7 IN-/AHI VCC 15 ALS 14 8 HDEL 9 LDEL ALO 13 AHS 12 DD R22 3 L1 AO Q2 +12V R23 2 CW BO C2 3 Q4 R24 AHO 11 2 1 3 CR1 1 L2 C1 1 3 2 1 BLS 17 16 V 2 1 C3 R30 CX R31 CY C5 ENABLE IN I R32 3 U2 4 COM O ALS BLS NOTES: CD4069UB 1. DEVICE CD4069UB PIN 7 = COM, PIN 14 = +12V. 9 U2 8 CD4069UB O 2. COMPONENTS L1, L2, C1, C2, CX, CY, R30, R31, NOT SUPPLIED. REFER TO APPLICATION NOTE FOR DESCRIPTION OF INPUT LOGIC OPERATION TO DETERMINE JUMPER LOCATIONS FOR JMPR1 - JMPR4. FIGURE 31. HIP4081A EVALUATION PC BOARD SCHEMATIC HIP4081A 11 3 Q3 3 4 V SS 5 OUT/BLI 10 AHB R34 R33 C8 CR2 U1 C4 1 BHB BHO 20 2 HEN/BHI BHS 19 3 DIS BLO 18 OUT/BLI 2 1 HIP4080A/81A CD4069UB 13 R21 DRIVER SECTION R26 COM C8 C6 R28 R27 B+ CR2 + R32 + JMPR5 +12V C7 R29 GND Q1 C4 BHO U1 Q3 1 R22 1 O Q2 R23 Q4 1 1 R21 AHO O LDEL CY CX FIGURE 32. HIP4081A EVALUATION BOARD SILKSCREEN R31 R34 R30 CR1 R33 BLS C3 C5 ALS HDEL 13 IN2 ALS ALO L2 HIP4081A JMPR1 JMPR2 JMPR3 JMPR4 I BLO BLS L1 IN1 HIP4080/81 R24 DIS U2 HIP4081A Dual-In-Line Plastic Packages (PDIP) E20.3 (JEDEC MS-001-AD ISSUE D) N 20 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 SYMBOL -B- A2 -C- SEATING PLANE e B1 D1 B 0.010 (0.25) M A1 eC C A B S MAX NOTES - 0.210 - 5.33 4 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.55 1.77 8 eA C 0.008 0.014 0.204 0.355 - D 0.980 1.060 24.89 26.9 5 D1 0.005 - 0.13 - 5 A L D1 MIN A E D MAX A1 -ABASE PLANE MILLIMETERS MIN C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N 20 20 9 Rev. 0 12/93 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 14 HIP4081A Small Outline Plastic Packages (SOIC) M20.3 (JEDEC MS-013-AC ISSUE C) 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE N INDEX AREA H 0.25(0.010) M B M INCHES E SYMBOL -B1 2 3 L SEATING PLANE -A- h x 45o A D -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M B S MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 - 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.4961 0.5118 12.60 13.00 3 E 0.2914 0.2992 7.40 7.60 4 0.050 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 8o 0o N α NOTES: MILLIMETERS MAX A1 e α MIN 20 0o 20 7 8o Rev. 0 12/93 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. 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