Cypress Roadmap: USB Controllers Q2 2016 001-89682 Rev *L Owner: MARF BUM: AJS USB Roadmap USB Portfolio Device Hub USB 2.0 USB 3.1 CYUSB301x FX3 32-Bit Bus to USB 3.1 Gen 1 ARM9, 512KB RAM FX3PD USB 3.1 Gen 2 Type-C Peripheral Controller with PD Contact Sales Bridge Host CYUSB33xx CYUSB306x HX3 CX3 USB 3.1 Gen 1,Shared Link™1 CSI-24 to USB 3.1 Gen 1 BC 1.22, Ghost Charge™3 4 CSI-24 Lanes, 1 Gbps/Lane NEW Q216 HX3C USB 3.1 Gen 1 Type-C Hub with PD Contact Sales CYUSB361x GX3 USB 3.1 Gen 1 to GigE Energy Efficient Ethernet HX3PD USB 3.1 Gen 2 Type-C Hub with PD Contact Sales DX3 USB 3.1 Gen 1 to DSI8 TX Contact Sales CY7C6801x/53 FX2LP 16-Bit Bus to USB 2.0 8051, 16KB RAM CY7C656x4 HX2VL 4 Ports 4 Transaction Translators GX2 USB 2.0 to 10/100 Ethernet Contact Sales CY7C68003 TX2UL ULPI9 PHY 13, 19.2, 24, 26 MHz CY7C656x1 HX2LP 4 Ports, Industrial Grade 1 Transaction Translator CYWB016xBB Bay™ HS USB OTG Dual SDXC6/eMMC7 USB 1.1 SL811HS FS USB Host/Device 256Byte RAM CY7C64215 enCoRe III M8C MCU, 50 GPIOs, ADC I2C/SPI, 16KB Flash CY7C65213 USB-to-UART (Gen 2) 3 Mbps, 8 GPIOs CY7C67300 EZ-Host 4 Ports, FS USB OTG 32 GPIOs CY7C643xx enCoRe V M8C MCU, 36 GPIOs, ADC I2C/SPI, 32KB Flash CY7C65210/7 USB Billboard ARM® Cortex® M0 1 or 2 UART/SPI/I2C channels CY7C67200 EZ-OTG™ 2 Ports, FS USB OTG 25 GPIOs Owner: MARF BUM: AJS CYPD1xxx CCG1 USB Type-C Port Controller 1 PD Port, 5 Profiles, 100 W CYUSB302x SD3 USB 3.1 Gen 1 SD Reader SDXC6/eMMC7, RAID5 CYPD2xxx CCG2 USB Type-C Cable Controller 1 PD Port, Termination, ESD NEW CYWB0x2xABS Arroyo™, Astoria™ 16-Bit Bus to USB 2.0 8051, Dual SD/eMMC7 Q216 CYPD4xxx CCG4/CCG4M USB Type-C Port Controller 2 PD Ports, 128KB Flash, Mux CY7C6803x NX2LP NAND Flash to USB 2.0 8051, 15KB RAM CCG5 USB Type-C AFE Contact Sales CY7C683xx AT2LP Parallel ATA to USB 2.0 8051 CY7C6521x USB-Serial UART/SPI/I2C to USB 2 Channels, CapSense® 001-89682 Rev *L CYUSB303x FX3S 16-Bit Bus to USB 3.1 Gen 1 RAID5, Dual SDXC6/eMMC7 Q216 CYPD3xxx CCG3 USB Type-C Port Controller 20-V, Crypto, Billboard CY7C638xx enCoRe™ II M8C MCU, 20 GPIOs SPI, 8KB Flash USB 2.0 and SuperSpeed traffic on the same port 2 Battery Charging specification v1.2 Type-C NEW CYUSB201x FX2G2 32-Bit Bus to USB 2.0 ARM9 512KB RAM 1 Simultaneous Storage 3 Enables USB charging without host connection 4 Camera Serial Interface v2.0 5 Redundant array of independent disks 6 SD extended capacity Production Sampling 7 Embedded MultiMedia Card Serial Interface 9 UTMI low-pin interface 8 Display USB Roadmap Type-C product applies to any USB speed Status Availability QQYY Development Concept QQYY 2 CCG1: USB Type-C and PD Port Controller Applications Block Diagram Notebooks, tablets, monitors, docking stations, power adapters, Type-C EMCAs and dongles CCG1: USB Type-C Port Controller with PD MCU Subsystem Programmable Analog Blocks Features IDAC 32-bit MCU Subsystem 48-MHz ARM® Cortex®-M0 CPU with 32KB flash and 4KB SRAM Integrated Analog Blocks 12-bit, 1-Msps ADC for VBUS voltage and current monitoring Dynamic overcurrent and overvoltage protection Integrated Digital Blocks Two configurable 16-bit TCPWM1 blocks One SCB1: I2C master or slave, SPI master or slave, or UART Up to eight GPIOs Type-C Support Integrated Type-C Transceiver, supporting two Type-C ports Controls routing of all protocols to an external MUX PD Support Supports Provider2 and Consumer3 roles and all power profiles Low-Power Operation 1.71-5.5 V operation Sleep: 1.3 mA, Deep Sleep: 1.3 µA Packages 40-pin QFN (36 mm2), 35-ball CSP (6.8 mm 2), 16-pin SOIC (60 mm2) 1 Serial Flash (32KB) SRAM (4KB) Comparators Programmable Digital Blocks TCPWM4 SCB1 (I2C, SPI, UART) Profiles and Configurations Baseband MAC Programmable Interconnect and Routing 48 MHZ Advanced High-Performance Bus (AHB) CORTEX®-M0 Type-C Port 2 GPIO Port Serial Wire Debug Baseband PHY Availability CCG1 Datasheet CCG1 RDK communication block A Type-C port that sources power over VBUS 001-89682 Owner: MARF Rev *L BUM: AJS 2 ADC Type-C Port 1 Collateral Datasheet: Reference Design Kit: I/O Subsystem Production: Now 3A Type-C port that sinks power from VBUS counter, pulse-width modulation block USB Roadmap 4 Timer, 3 CCG2: USB Type-C and PD Port Controller Block Diagram Applications USB Type-C EMCA, Powered Accessories, UFP, DFP, DRP CCG2: USB Type-C Port Controller With PD MCU Subsystem Collateral CORTEX-M0 48 MHz Flash (32KB) SRAM (4KB) 3 2 communication block configurable as UART, SPI or I2C Termination resistor read as a DFP 4 Owner: MARF BUM: AJS (I2C, VCONN1 SCB1 SPI, UART) VCONN2 SCB1 (I2C, SPI, UART) Profiles and Configurations Baseband MAC Baseband PHY VDDIO GPIO5 Port Integrated RP2, RD3, RA4 Serial Wire Debug Availability Now CCG2 Datasheet CCG2 RDK 1 Serial 001-89682 Rev *L CC7 Production: Datasheet: Reference Design Kit: I/O Subsystem TCPWM6 Advanced High-Performance Bus (AHB) 32-bit MCU Subsystem 48-MHz ARM® Cortex® -M0 CPU with 32KB flash and 4KB SRAM Integrated Digital Blocks Integrated timers, counters and pulse-width modulators Two SCBs1 configurable to I2C, SPI or UART modes Type-C Support Integrated transceiver, supporting one Type-C port Integrated DFP (RP2), UFP (RD3), EMCA (RA4) termination resistors Power Delivery (PD) Support Standard power profiles Low-Power Operation Two independent VCONN rails with integrated isolation Independent supply voltage pin for GPIO5 2.7-V to 5.5-V operation Sleep: 2.0 mA; Deep Sleep: 2.5 µA System-Level ESD on CC6 and VDD Pins ±8-kV contact, ±15-kV Air Gap IEC61000-4-2 level 4C Packages 20-ball, 3.3-mm2 CSP with 0.4-mm ball pitch 14-pin 2.5mm x 3.5mm DFN with 0.6mm pin pitch 24-pin 4mm x 4mm QFN with 0.55mm pin pitch Integrated Digital Blocks Programmable I/O Matrix Features Termination resistor read as a UFP Termination resistor read as an EMCA USB Roadmap 5 6 General-purpose input/output Timer, counter, pulse-width modulation block 7 Configuration Channel 4 CCG3: USB Type-C and PD Port Controller Applications Block Diagram Accessories and power adapters CCG3: USB Type-C Cable Controller Collateral Datasheet: Cortex®-M0 48 MHz Flash (64KB) Flash (64KB) 4x TCPWM9 4x SCB4 (I2C, SPI, UART) Crypto Engine I/O Subsystem Programmable I/O Matrix Type-C Support Integrated transceiver, supporting one Type-C port Alternate Modes1, Crypto Engine2 for USB Authentication3 Power Delivery (PD) Support for Standard Power Profiles Integrated Digital Blocks for VBUS Power and MUX Interface Four timers, counters and pulse-width modulators, 24x GPIOs Four SCBs4 for configurable master/slave I2C, SPI or UART USB Billboard Controller5 with Billboard Device Class6 support Integrated Analog Blocks for OVP, OCP7 20-V OVP7 and OCP8; 4:2 cross-bar switch 32-bit ARM® Cortex®-M0 CPU with MCU Subsystem 2x64KB flash for fail-safe updates over CC, I2C or USB interfaces Low-Power Operation 2x VBUS Gate Drivers8, for consumer and provider power paths 2x high-voltage (5-20 V, 25 V Max) VBUS voltage inputs Sleep: 2.0 mA; Deep Sleep: 2.5 µA with wake-on-I2C/wake-on-CC System-Level ESD on CC/VCONN, VBUS, and SBU Pins ±8-kV contact, ±15-kV Air Gap IEC61000-4-2 level 4C Packages 42-ball (8.5 mm2) CSP and 40-pin (36 mm2) QFN Integrated Digital Blocks Advanced High-Performance Bus (AHB) MCU Subsystem Features CC 24x GPIO Ports USB PD Subsystem Baseband MAC Baseband PHY 20-V Regulator 2x VCONN FETs Overcurrent Protection 2x 20V VBUS FET Gate Drivers8 System Resources Overvoltage Protection Integrated Resistors (RP, RD, RA)10 Full-Speed USB Billboard Controller 4:2 Analog Cross-Bar Switch 8-bit SAR ADC SRAM (8KB) Availability Samples: CCG3 Datasheet 1 Mode of operation in which the data lines are repurposed to transmit non-USB data The encryption hardware and software required to implement USB Authentication 3 A USB-IF specification that defines the authentication protocol for Type-C accessories 4 Serial communication block configurable as UART, SPI or I2C 5 A USB Device controller that informs the USB Host of the supported Alternate Modes 6 2 7 001-89682 Rev *L USB Roadmap Owner: MARF BUM: AJS Now Production: Q2 2016 A specification that defines the method for a USB Device to communicate the supported Alternate Modes Overvoltage protection, overcurrent protection 8 Circuits to control the gates of external power Field-Effect Transistors (FETs) on V BUS (5-20 V) 9 Timer/counter/pulse-width modulator block 10 Termination resistors: R read as a DFP, R as a UFP, R as an EMCA P D P 5 CCG4/4M: USB Type-C and PD Port Controller Applications Block Diagram Notebooks, tablets, monitors, docking stations, power adapters Features Collateral ARM Cortex®-M0 48 MHz Flash (128KB) 16 4x SCB1 32 32 Type-C Baseband Transceiver Type-C Baseband Transceiver CC7 CC7 2x VCONN FETs 4x 8-bit SAR ADC 4 4x TCPWM 4 24 GPIOs 2x VCONN FETs 2 USB/DP Mux (CCG4M) 2 To EC8 24 SS_ USB + DP 8 AUX 2 12 Type-C Port 1 3 Type-C Port 2 Samples: Now I2C resistor read as a DFP Serial communication block configurable as UART, SPI or 4 An interface jointly defined by intel and Apple that connects peripherals to a computer Termination resistor read as a UFP 001-89682 Owner: MARF USB Roadmap Rev *L BUM: AJS 2 SRAM (8KB) SS_USB + DP 2 SBU Availability Datasheet: CCG4 Datasheet 1 Termination CCG4/4M: Two-Port Type-C Controller with Power Delivery Programmable I/O Matrix Integrated USB Type-C Transceivers Support 2 Type-C Ports Integrated 2x 1-W VCONN FETs and 2x FET control signals, per port programmable RP1 and removable RP1, and RD2 terminations Supports dead battery mode operation Integrated SuperSpeed USB/DisplayPort (DP) Mux (CCG4M) Increased Flash Enables Fail-Safe Bootup Integrates 128KB flash to store dual firmware images Dual firmware images enable Fail-Safe Bootup every time Integrated Digital Blocks for Inter-Chip Communications Four SCBs3 master or slave configurable to I2C, SPI or UART SCBs3 interconnect CCG4 with embedded controller, two alternate muxes and Thunderbolt4 controller (optional) Integrated Blocks for OVP5 and OCP6 Four 8-bit SAR ADCs configurable for OVP5 and OCP6 Low-Power Operation 2.7-V to 5.5-V operation and independent supply voltage for general-purpose input/output (GPIO) Sleep: 2.0 mA; Deep Sleep: 2.5 µA with wake-on-I2C/wake-on-CC7 System-Level ESD on CC7 Pins ±8-kV contact, ±15-kV Air Gap IEC61000-4-2 level 4C 32-bit ARM® Cortex® -M0 CPU with MCU Subsystem 128KB flash, upgradable over CC7 lines or I2C interface Packages 40-pin QFN, 96-ball BGA (CCG4M) Production: Q2 2016 5 6 Overvoltage protection Overcurrent protection 7 8 Configuration Channel Embedded controller in a PC 6 HX3C: USB 3.0 Type-C Hub1 With Power Delivery (PD)2 Block Diagram Applications USB Type-C charging Hubs1, adapters and accessories Docking stations for notebook PCs and tablets Televisions and monitors PC motherboards and servers Set-top boxes, home gateways and routers EEPROM USB Type-C (US Port) 2 4 2 HX3C Hub SS7 PHY MCU 2 USB 2.0 PHY CC6 2 PD2 Controller USB 3.1 Gen 1 PHY 32 Features 16 32 Hub1 USB 3.1 Gen 1-compliant controller Upstream (US): Type-C Downstream (DS): 1 Type-C and 2 Type-A ports Integrated Type-C transceivers, supporting two ports Integrated DFP (RP) and UFP (RD) termination resistors Integrated USB Billboard Controller3 Charging Support: USB PD2, BC v1.24, Apple Charging Standard5 PD policy engine configures power profiles dynamically Ghost Charge™: Charging DS without US connection Firmware upgradable over USB System-Level ESD on CC6 Pins: 8 kV contact, 15 kV airconfigurable USB SS7 and USB 2.0 PHY (drives 11ʺ trace) 121-ball BGA (10 mm x 100 mm, 0.8 mm ball-pitch) Buffers 1 16 Routing Logic USB Billboard Controller3 Routing Logic 16 32 USB 3.1 Gen 1 PHY SS7 PHY USB 2.0 PHY 2 USB 3.1 Gen 1 PHY SS7 PHY 2 USB Type-A (DS Port) Directs data traffic between a USB Host and multiple USB Devices A new USB standard that increases power delivery over V BUS from 7.5 W to 100 W 3 A USB Device controller that is used to implement the USB Billboard Device Class Informs the USB Host of the supported Alternate Modes as well as any failures 001-89682 Owner: MARF Rev *L BUM: AJS 2 4x TT8 Repeater 32 Collateral HX3C Datasheet HX3C Overview EZ-USB™ HX3C: USB Type-C Hub with Power Delivery 2 16 32 4 Datasheet: Product Overview: App Note: USB 2.0 Hub1 Controller SS7 Hub1 Controller 4 USB 2.0 PHY 2 USB Type-A (DS Port) 2 USB 3.1 Gen 1 PHY SS7 PHY 4 USB 2.0 PHY CC6 2 PD2 Controller 2 USB Type-C (DS Port) Availability Samples: Production: 4A Q2 2016 Q3 2016 specification published by the USB Implementers Forum (USB-IF) for charging portable USB Devices 5 An Apple-specified battery charging standard for the iPhone, iPod and iPad USB Roadmap 6 Configuration Channel USB SuperSpeed 8 Transaction Translator 7 7 GX3: USB 3.1 Gen 1 to Gigabit Ethernet Bridge Applications Block Diagram USB dongles, docking stations, USB port replicators Network printers, security cameras Ultrabooks, home gateways Game consoles, portable media players DVRs, IP set-top boxes, IP TVs Other embedded systems One-chip USB 3.1 Gen 1 to 10/100/1000M GigE1 bridge Integrates USB 3.1 Gen 1 PHY and GigE1 PHY Integrates USB 3.1 Gen 1 Controller and GigE1 MAC2 Needs only a 25-MHz crystal to drive both USB and GigE1 PHY IEEE 802.3az3 support for low-power idle state Supports dynamic cable length and power adjustment Offers multiple power management Wake-on-LAN4 features Supports optional EEPROM to store USB descriptors Integrates on-chip POR5 circuitry 68-QFN (8 x 8 x 0.85 mm) 8 GigE1 PHY Features Data SRAM Program ROM DMA Engine RISC SOC GigE1 MAC2 Controller USB Controller I2C GPIO 2 Clock USB 3.1 Gen 1 PHY GX3 Bridge 6 USB 3.1 Gen 1 Host Reset 8 Collateral Datasheet: GX3 Datasheet Reference Design Kit: GX3 RDK Software Drivers: GX3 Drivers Availability Production: 1 Gigabit 4 2 5 Ethernet Media access controller that provides the address to an Ethernet node 3 A new-energy efficient Ethernet standard 001-89682 Rev *L Owner: MARF BUM: AJS Now An Ethernet standard that allows a computer to be turned on by a network message Power-on reset USB Roadmap 8 HX3: USB 3.1 Gen 1 Hub Applications Block Diagram Docking stations for notebook PCs and tablets PC motherboards, servers Digital TV, monitors Retail hub boxes Printers, scanners Set-top boxes, home gateways, routers, game consoles Upstream Port HX3 Hub SS3 PHY USB 2.0 PHY I2C 32 16 SuperSpeed Hub Controller USB 2.0 Hub Controller 16 32 Buffers 4x TT1 Repeater 16 32 Routing Logic Routing Logic 32 16 USB 3.1 Gen 1 PHY SS3 PHY USB 3.1 Gen 1 PHY USB 2.0 PHY SS3 PHY 4 2 Downstream Port 1 4 USB 3.1 Gen 1 PHY USB 2.0 PHY SS3 PHY 2 USB 2.0 PHY 4 Downstream Port 2 2 Downstream Port 3 USB 3.1 Gen 1 PHY SS3 PHY 4 USB 2.0 PHY 2 Downstream Port 4 Availability Collateral Datasheet: Application Note: Kits: Configuration Utility: HX3 Datasheet HX3 Hardware Design Guide CY4609, CY4603, CY4613 Blaster Plus2 2 Transaction translator 001-89682 Rev *L 8 MCU USB 3.1 Gen 1 PHY 32 1 2 2 4 Features USB 3.1 Gen 1-compliant four-port Hub Controller USB-IF certified (Test ID: 330000047) WHQL certified for Windows 7, Window 8, Windows 8.1 Shared Link™: Supports simultaneous USB 2.0 and USB SuperSpeed (SS) Devices on the same port Ghost Charge™: Enables USB charging while the Hub is disconnected from a USB Host Charging Standard support: USB-IF Battery Charging v1.2 Apple Charging Standard Charging an OTG Host in an ACA-Dock Programming of external EEPROM via USB Configurable USB SS & USB 2.0 PHY. Drives 11ʺ trace 68-QFN (8 x 8 x 1.0 mm), 88-QFN (10 x 10 x 1.0 mm), 100-BGA (6 x 6 x 1.0 mm) EEPROM Owner: MARF BUM: AJS Production: Now A Cypress GUI-based PC application for setting HX3 configuration parameters USB Roadmap 3 SuperSpeed 9 FX3: USB 3.1 Gen 1 Peripheral Controller Applications Block Diagram Industrial, medical and machine vision cameras 3-D, 1080p Full HD and 4K Ultra HD (UHD) cameras Document scanners, fingerprint scanners Videoconferencing systems Data acquisition systems Video capture cards and HDMI converters Protocol and logic analyzers USB test tools and software-designed radios (SDRs) 5 FX3 Controller JTAG 512KB RAM USB 3.1 Gen 1-compliant Peripheral Controller USB-IF certified (TID:340800007) Fully accessible 32-bit, 200-MHz ARM926EJ core 512KB of embedded SRAM for code space and buffers Up to 32-bit, 100-MHz, flexible GPIF II interface Other peripheral interfaces such as I2C, I2S, UART, SPI and 12 GPIOs Unused I/O pins can be used as GPIOs Up to 32 USB endpoints Flexible clock options: 19.2-MHz crystal 19.2-MHz, 26-MHz, 38.4-MHz and 52-MHz clock input 121-ball BGA (10 x 10 mm), 131-ball WLCSP (4.7 x 5.1 mm Image Sensor, FPGA or ASIC 32 32 32 USB 3.1 Gen 1 Features GPIF-II ARM9 32 32 32 UART 4 I2C I2S 2 4 SPI 4 6 USB 3.1 Gen1 Host GPIO 12 Collateral Datasheet: Development Kit: Software Development Kit: 001-89682 Rev *L Owner: MARF BUM: AJS FX3 Datasheet FX3 SuperSpeed Explorer Kit EZ-USB FX3 SDK Availability Production: USB Roadmap Now 10 FX3S: USB 3.1 Gen 1 RAID1-on-Chip Applications Block Diagram Servers, routers Mobile storage, USB flash drives POS terminals Automatic Teller Machines (ATM) SDIO expanders Data logging devices 5 JTAG ARM9 USB 3.1 Gen 1-compliant Peripheral Controller USB-IF certified (TID:340800007) Fully accessible 32-bit, 200-MHz ARM926EJ core 512KB of embedded SRAM for code space and buffers Up to 16-bit, 100-MHz, flexible GPIF II interface Peripheral interfaces such as I2C, UART, SPI and GPIOs Supports two SDXC2, eMMC3 4.4, or SDIO 3.0 interfaces Support RAID0 or RAID1 configurations Flexible clock options: 19.2-MHz crystal 19.2-MHz, 26-MHz, 38.4-MHz and 52-MHz clock input 121-ball BGA (10 x 10 mm) 131-ball WLCSP (4.7 x 5.1 mm) Collateral FX3S Datasheet FX3S RAID1-on-Chip Boot Disk Kit FX3 Software Development Kit (SDK) FX3S Hardware Design Guidelines USB RAID11 Disk Design Using FX3S array of independent disks extended capacity 001-89682 Rev *L 16 32 32 32 32 SDXC2/eMMC3S DIO 4 SD Card, eMMC3 NAND, SDIO Device 6 USB 3.1 Gen 1 Host SDXC2/eMMC3S DIO 4 SD Card, eMMC3 NAND, SDIO Device Availability 1 Redundant 2 SD ASIC, FPGA, SoC GPIF II Features Datasheet Kit: Software: App Notes: 512KB RAM (RAID1 Firmware) USB 3.1 Gen 1 FX3S RAID1-on-Chip Owner: MARF BUM: AJS 3 Embedded Production: Now MultiMedia Card USB Roadmap 11 CX3: MIPI1 CSI-2 to USB 3.1 Gen 1 Bridge Applications Block Diagram Industrial, medical and machine vision cameras 1080p Full HD and 4K Ultra HD (UHD) camera Document scanners, fingerprint scanners Game consoles Videoconferencing systems Notebook PCs, tablets Image acquisition systems 5 CX3 Bridge JTAG 512KB RAM 4 MIPI1 CSI-2 USB 3.1 Gen 1-compliant video-class controller Four-lane MIPI1 Camera Serial Interface v2.0 (CSI-2) input Camera Control Interface (CCI) for image sensor configuration Supports industry-standard video data formats: RAW8/10/12/142, YUV422/4443, RGB888/666/5654 Supports uncompressed streaming video: 4K UHD at 15 fps, 1080p at 30 fps, 720p at 60 fps On-chip ARM9 with 512KB RAM for data processing Supports I2C, I2S, SPI, UART and 12 GPIOs 121-BGA (10 x 10 x 1.7 mm) Image Sensor or Image Signal Processor 32 32 32 32 UART 4 I2C SPI 2 4 USB 3.1 Gen 1 ARM9 Features 6 USB 3.1 Gen 1 Host GPIO 12 Collateral Datasheet: Reference Design Kit: Software Development Kit: 1 Mobile Industry Processor Interface format for raw video data 2 Video 001-89682 Rev *L Owner: MARF BUM: AJS CX3 Datasheet CX3 RDK EZ-USB SDK 3 4 Availability Production: Now Video format for luminance and chrominance components Video format for red, green and blue pixel components USB Roadmap 12