HS-0508RH, HS-0509RH TM Data Sheet August 1999 Radiation Hardened Single 8/Differential 4-Channel CMOS Analog Multiplexers These radiation hardened monolithic CMOS multiplexers each include an array of eight analog switches, a digital decode circuit for channel selection, a voltage reference for logic thresholds, and an ENABLE input for device selection when several multiplexers are present. The Dielectric Isolation (DI) process used in fabrication of these devices eliminates the problem of latch-up. Also, DI offers much lower substrate leakage and parasitic capacitance than conventional junction-isolated CMOS. Switches are guaranteed to break-before-make, so that two channels are never shorted together. The switching threshold for each digital input is established by an internal +5V reference, providing a guaranteed minimum 2.4V for logic “1” and maximum 0.8 for logic “0”. This allows direct interface without pull-up resistors to signals from most logic families: CMOS, TTL, DTL and some PMOS. For protection against transient overvoltage, the digital inputs include a series 200Ω resistor and a diode clamp to each supply. The HS-0508RH is an eight channel single-ended multiplexer, and the HS-0509RH is a four channel differential version. If input overvoltage protection is needed, the HS-0548RH and HS-0549RH multiplexers are recommended. Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. Detailed Electrical Specifications for these devices are contained in SMD 5962-95692. A “hot-link” is provided on our homepage for downloading. http://www.intersil.com/spacedefense/space.htm FN3977.2 Features • Electrically Screened to SMD # 5962-95692 • QML Qualified per MIL-PRF-38535 Requirements • Gamma Dose . . . . . . . . . . . . . . . . . . . . . . 1 x 104RAD(Si) • No Latch-Up • No Channel Interaction During Overvoltage • Low On Resistance . . . . . . . . . . . . . . . . . . . . <200Ω (Typ) • 44V Maximum Power Supply • Break-Before-Make Switch • Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . ±15V • Access Time. . . . . . . . . . . . . . . . . . . . . . . . . <300ns (Typ) Applications • Data Acquisition Systems • Control Systems • Telemetry Ordering Information INTERNAL MKT. NUMBER ORDERING NUMBER TEMP. RANGE (oC) 5962D9569201VEA HS1-0508RH-Q -55 to 125 5962D9569201VEC HS1B-0508RH-Q -55 to 125 5962D9569202VEA HS1-0509RH-Q -55 to 125 5962D9569202VEC HS1B-0509RH-Q -55 to 125 Pinouts HS-0508RH GDIP1-T16 (CERDIP) OR CDIP2-T16 (SBDIP) TOP VIEW A0 1 16 A1 ENABLE 2 15 A2 14 GND -VSUPPLY 3 HS-0509RH GDIP1-T16 (CERDIP) OR CDIP2-T16 (SBDIP) TOP VIEW A0 1 ENABLE 2 -VSUPPLY 3 16 A1 15 GND 14 +VSUPPLY IN 1 4 13 +VSUPPLY IN 1A 4 13 IN 1B IN 2 5 12 IN 5 IN 2A 5 12 IN 2B IN 3 6 11 IN 6 IN 3A 6 11 IN 3B IN 4 7 10 IN 7 IN 4A 7 10 IN 4B 8 9 IN 8 OUT 1 OUTA 8 9 OUT B CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved HS-0508RH, HS-0509RH Functional Diagrams HS-0508RH HS-0509RH IN1 OUT IN2 IN1A OUT A IN4A DECODER/ DRIVER IN1B IN8 OUT B DECODER/ DRIVER IN4B LEVEL SHIFT 5V REF † †DIGITAL INPUT PROTECTION † LEVEL SHIFT 5V REF † † †DIGITAL INPUT PROTECTION † † A0 A1 A0 A1 A2 EN HS-0508RH TRUTH TABLE † EN HS-0509RH TRUTH TABLE A2 A1 A0 EN “ON” CHANNEL A1 A0 EN “ON” CHANNEL PAIR X X X L NONE X X L NONE L L L H 1 L L H 1 L L H H 2 L H H 2 L H L H 3 H L H 3 L H H H 4 H H H 4 H L L H 5 H L H H 6 H H L H 7 H H H H 8 2 HS-0508RH, HS-0509RH Schematic Diagrams TTL REFERENCE CIRCUIT V+ R10 R9 Q1 Q4 D3 LEVEL SHIFTER V+ P P P P P P P R3 V+ D2 R1 N P P LEVEL SHIFTED ADDRESS TO DECODE R2 N OVERVOLTAGE PROTECTION ADD IN. P R5 R7 R6 R8 LEVEL SHIFTED ADDRESS TO DECODE R4 N N N N N N N N 200Ω D1 V- V- FIGURE 1. ADDRESS INPUT BUFFER AND LEVEL SHIFTER P P P N A0 OR A0 P N N P N N18 FROM DECODE V+ N17 N19 IN A1 OR A1 TO N-CHANNED DEVICE OF THE SWITCH P P TO P-CHANNED DEVICE OF THE SWITCH +V N A2 OR A2 N A3 OR A3 N ENABLE DELETE A3 OR A3 INPUT FOR HI-507 DELETE A3 OR A3 INPUT FOR HI-508 DELETE A2 OR A2 INPUT FOR HI-509 V- FIGURE 2. ADDRESS DECODER 3 OUT P17 V- P18 FROM DECODE FIGURE 3. MULTIPLEX SWITCH HS-0508RH, HS-0509RH Burn-In/Life Test Circuits V1 F0 1 16 F1 1 16 F3 2 15 F2 2 15 3 14 3 14 4 13 4 13 5 12 6 11 7 10 8 9 V1 D1 V2 V2 D1 C1 5 12 6 11 7 10 8 9 D2 R1 D2 C2 R1 -15V maximum, -16V minimum +15V minimum, +16V maximum 10kΩ ±5% 1/4W C2 = 0.01µF minimum (per socket) or 0.1µF minimum (per row) D2 = 1N4002 (or equivalent) 100kHz 50% duty cycle; VIL = 0.8V max; VIH = 4.0V min. F0/2 F1/2 F2/2 D1 2 15 3 14 4 13 5 12 11 6 11 10 7 10 9 8 9 16 F2 2 15 3 14 4 13 5 12 6 7 8 C1 F1 V2 D1 R1 C1 V3 D1 R1 +15.5V, ±.0.5V -15.5V, ±0.5V 10kΩ, ±5% 0.1µF minimum (per socket) 1N4002 or equivalent (per board) 100kHz, ±10%; F1 = F0/2; F2 = F1/2, 50% duty cycle, VIL = 0.8V max.; VIH = 4.0V min. 4 C1 V2 R1 HS-0509RH STATIC BURN-IN TEST CIRCUIT V1 = V2 = V3 = R1 = C1 = D1 = V1 D1 R1 HS-0509RH DYNAMIC BURN-IN AND LIFE TEST CIRCUIT V2 = V3 = R1 = C1 = D1 = F0 = 5V minimum, 6V maximum -15V maximum, -16V minimum +15V minimum, +16V maximum 10kΩ ±5% 1/4W C2 = 0.01µF minimum (per socket) or 0.1µF minimum (per row) D2 = 1N4002 (or equivalent) 16 1 V3 V1 = V2 = V3 = R1 = C1 = D1 = 1 F0 C2 HS-0508RH STATIC BURN-IN TEST CIRCUIT HS-0508RH DYNAMIC BURN-IN AND LIFE TEST CIRCUIT V1 = V2 = R1 = C1 = D1 = F0 = F1 = F2 = F3 = V3 C1 +5.5V, ±0.5V +15.5V, ±0.5V -15.5V, ±0.5V 10kΩ, ±10% 0.1µF minimum (per socket) 1N4002 or equivalent (per board) C1 HS-0508RH, HS-0509RH Irradiation Circuits HS-0509RH +5V -15V +1V 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 R1 +15V +1V R2 R1 = R2 = 10kΩ ±5% HS-0508RH +5V -15V +1V 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 R1 R1 = 10kΩ ±5% 5 +15V +1V HS-0508RH, HS-0509RH Die Characteristics DIE DIMENSIONS: Backside Finish: 81.9mils x 90.2mils x 19mils Silicon INTERFACE MATERIALS: ASSEMBLY RELATED INFORMATION: Glassivation: Substrate Potential: Type: Nitride Thickness: 7kÅ ±0.7kÅ Unbiased (DI) ADDITIONAL INFORMATION: Top Metallization: Worst Case Current Density: Type: Al Thickness: 16kÅ ±2kÅ < 2.0 x 105 A/cm2 Transistor Count: Substrate: HS-0508RH HS-0509RH CMOS Dielectric Isolation 243 243 Metallization Mask Layout HS-0508RH EN A0 A1 A2 HS-0509RH GND EN A0 A1 GND -VSUP +VSUP -VSUP +VSUP IN 1 IN 5 IN 1A IN 1B IN 2 IN 6 IN 2A IN 2B IN 3 IN 3A IN 7 IN 4 OUT IN 8 IN 3B IN 4A OUT A OUT B IN 4B NOTE: Pad numbers correspond to DIP pin numbers only. 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