Application NOTES: www.pwrx.com BP7B – L-Series IPM Interface Circuit Reference Design Description: The BP7B is a complete isolated interface circuit for six and seven pack low and medium power LSeries IPMs. This circuit features the VLA606-01R opto-interface IC for isolation of control signals and isolated power supplies for the IPM’s built-in gate drive and protection circuits. The isolated interface helps to simplify prototype development and minimize design time by allowing direct connection of the IPM to logic level control circuits. Features: • Complete three-phase isolated interface circuit with brake control and fault feedback • 2500VRMS isolation for control power and signals • Standard AMP MTA .100” Input Signal and Control Power Connectors • Operates from a single 24VDC supply • Compact Size 4.0” x 2.5” (63mm x 102mm) Applications: BP7B is designed for use with Powerex L-Series six and seven pack IPMs: 50A-300A 600V and 25A150A 1200V. ¾ Use Powerex VLA106-24151 and VLA10624154 DC to DC converters for isolated control power. See Table 1 for requirements. Ordering Information: BP7B-LS is a kit containing a bare PCB with one VLA606-01R and four VLA106-24151 DC to DC converters (For use with L-Series IPMs in package A and B) BP7B-LB is a kit containing a bare PCB with one VLA606-01R opto-interface IC, three VLA106-24151 DC to DC converters and one VLA106-24154 DC to DC converter (For use with L-Series IPMs in package C) BP7B is a bare PCB only. Note: User must supply Optocouplers and passive components to fully populate the BP7B (See Table 2) 1 Table 1: L-Series IPM Line-Up and Interface Circuit Selection Part Num ber Voltage Curre nt Re com m ended Re fe rence Package (V) (A) DC to DC Conve rters Des ign PM50(#)L(*)060 50 PM75(#)L(*)060 75 PM100(#)L(*)060 100 PM150(#)L(*)060 150 PM200(#)LA060 600 200 PM300(#)LA060 300 PM450CLA060 450 PM600CLA060 600 PM25(#)L(*)120 25 PM50(#)L(*)120 50 PM75(#)L(*)120 75 PM100(#)LA120 100 PM150(#)LA120 Figure 1: L-Series IPMs 1200 150 PM200CLA120 200 PM300CLA120 300 PM450CLA120 450 A or B VLA106-24151 x 4pc. BP7B Package A C VLA106-24151 x 3pc. VLA106-24154 x 1pc. D VLA106-24151 x 6pc. A or B VLA106-24151 x 4pc. C VLA106-24151 x 3pc. VLA106-24154 x 1pc. D VLA106-24151 x 6pc. BP6A BP7B (*) Package Option: B=Solder pin, A=Screw terminal (#) Circuit Option: R=Six Pack+Brake, C=Six pack Example: PM75RLB120 is a 75A, 1200V six pack with brake in a solder pin package Package B BP6A Package C Overview: A significant advantage provided by the L-Series IPM’s builtin gate drive and protection circuits is that the entire family outlined in Table 1 requires only two different interface circuit designs. The standard interface circuit consists of opto-couplers to transfer control signals and isolated power supplies to power the IPM’s internal circuits. The two circuits are similar except that devices in packages A, B, and C have a common control ground for all three low side IGBTs. This permits use of a single low side supply so that only four isolated supplies are required. The Powerex BP7B reference design is an example of this circuit. The remaining large L-Series IPMs in Package D package D utilize separate control local shield plane islands on the low side to minimize ground bounce induced noise. As a result these devices require six isolated power supplies. Interface circuit details for these devices are available in the Powerex BP6A reference design application note. Isolated DC to DC Converters: In order to simplify the design and layout of the required control power supplies Powerex has introduced the VLA106-24151, VLA106-24154 isolated DC to DC converters shown in figure 2. Both DC to DC converters are designed to operate from a 24V DC supply and produce an isolated 15V DC output. The VLA106-24151 provides up to 100mA and the VLA106-24154 provides up to 300mA for control power. Both DC to DC converters use transformers to provide 2500VRMS isolation between the primary and secondary side. The BP7B board uses three VLA106-24151 DC to DC converters to provide high side control power for the L-Series IPMs. The low side control power can be supplied by either a VLA106-24151 or VLA106-24154. The higher current VLA106-24154 is only needed for low side control power on the package C IPMs when the current draw of the three low side gate drive circuits exceeds 100mA. Table 1 shows the recommended DC to DC converters for each L-Series IPM. 2 BP7B Circuit Explanation: +VL +WN +VN +UN BR +WP +VP +UP FO GND J2 IC6 VLA106-24154/VLA106-24151 40 39 38 37 36 35 34 33 32 VLA106-24154 IC12 + LED4 R1 FO WN VN UN BR VN1 VN C5 + J1 3 2 1 3 2 1 VLA106-24151 11 10 9 8 WP + A complete schematic of the 18 WFO LED3 17 BP7B interface circuit is shown in figure C VWPC 16 3 and the bill of materials is given in 15 Table 2. This circuit uses the VLA60601R to transfer logic level control signals 11 between the system controller and the 10 9 IPM. The internal optocouplers provide VVP1 8 galvanic isolation to completely separate VP + the controller from the high voltage in VFO 4 LED2 C2 the power circuit. The BP7B also VVPC 3 provides isolated control power supplies 2 1 to power the IPMs built-in gate drive and protection circuits. The six main IGBT on/off control VUP1 signals (UP,VP,WP,UN,VN,WN) are UP + transferred from the system controller to UFO LED1 C1 the IPM using the VLA606-01R. The VUPC IPM’s active low control inputs are J3 pulled high by the VLA606-01R. An on L-Series IPM signal is generated by turning on the Connector internal optocoupler to pull the IPM’s control input pin low. The brake IGBT control signal (BR) is transferred from the controller to the IPM using a low speed optocoupler (IC1). The active low brake input pin on the IPM is normally pulled high by R1. When the BR control line (Pin 6 of CN1) is pulled low, current flows in the LED of the brake isolation optocoupler turning on its output and pulling the IPM’s brake pin low to activate the brake IGBT. If the IPM being used does not have the brake option then IC1, R1, and R2 can be omitted. The IPM’s fault output signals are transferred back to the system controller using low speed optocoupled transistors internal to the VLA606-01R. During normal operation the fault feedback line (pin 9 of J2) is pulled high to the +VL supply by the 4.7K resistor R3. When a fault condition is detected by the IPM it will immediately turn off the involved IGBT and pull its fault output pin low. The IPM’s fault output has an open collector characteristic with an internal 1.5k ohm limiting resistor. Current flows from the +15V local isolated supply to the low speed optocoupler LED (inside the VLA606-01R) and then to the IPM’s fault pin. The optocoupler’s 3 2 1 VLA106-24151 11 10 9 8 3 +V LED5 C4 VWP1 R4 VLA106-24151 27 26 25 24 23 22 16 17 8 9 10 11 IC1 11 10 9 8 VLA606-01R Figure 2: Isolated DC to DC Converters for IPM Control Power R3 IC2 VLA106-24151 1 2 3 R2 IC5 IC4 IC3 Table 2: BP7B Reference Design Component Selection Characteristic 4.7KΩ, 0.25W 180Ω, 0.25W 4.7KΩ, 0.25W 1.8KΩ, 0.25W 39μF, 35V, 105C, Low imp. 150μF, 35V, 105C, Low imp. 560μF, 50V, 105C, Low imp. Super bright red LED Super bright green LED Slow Opto coupler NEC PS2501 2 position 0.1” right angle single row header 10 position 0.1” right angle single row header 2mm single row bottom entry header receptacle Powerex VLA606-01R Powerex VLA106-24151 Powerex VLA106-24151 or VLA106-24154 transistor turns on and its collector pulls the fault feedback line low to indicate a fault. If any of the IPM’s four fault output signals become active; pin 39 of the VLA606-01R will be pulled low. Slow optos are used because they offer the advantages of lower cost and higher current transfer ratios. High speed is not necessary because the IPM disables a faulted device and produces a fault signal for a minimum of 1ms. The BP7B also includes an LED in series with each fault output (LED1-LED4) to provide a quick visual indication when the IPM’s fault signal is active. This was included for trouble shooting purposes only so it can be replaced by a jumper without affecting the operation of the interface circuit. Isolated control power for the IPM is supplied by Powerex isolated DC to DC converters (IC3, IC4, IC5, IC6) as described above. Each power supply is decoupled at the IPM’s pins with a low impedance electrolytic capacitor (C1-C4). These capacitors must be low impedance/high ripple current types because they are required to supply the high current gate drive pulses to the IPM’s internal gate driving circuits. The DC to DC converters are powered from a single 24VDC supply connected at CN3. The 24VDC supply is decoupled by the electrolytic capacitor C5 to maintain a stable well filtered source for the DC to DC converters. The current draw on the 24V supply will range from about 75mA to 200mA depending on the module being driven and switching frequency. For a more accurate estimate it is necessary to use the IPM’s circuit current (ID) versus fC characteristic to obtain the current required by the IPM being used. The IPM current draw can then be adjusted using the DC to DC converter efficiency specification to arrive at the current draw on the 24V supply. Refer to the general IPM application notes for detailed information. A power indicator consisting of an LED (LED5) in series with current limiting resistor (R4) is provided to show that the 24VDC supply is present. Description Brake input pull-up Input current limiter (15mA@VL=5V) Fault signal pull-up Power Indicator Current limiter Control power decoupling capacitor Control power decoupling capacitor DC to DC input decoupling capacitor Fault indicator LED Control power LED Brake signal isolator 24VDC Control power connector Control signal connector IPM connector Hirose DF10-31S-2DSA Control and Fault signal isolator High side isolated DC/DC converter Low side isolated DC/DC converter - + J1 J2 GNDFOUP VP WP Br UNVN WN+VL FO WN VN UN BR VN1 VNC VWP1 WP WFO VWPC IPM Connector Designation R1 R2 R3 R4 C1, C2, C3 C4 C5 LED1, LED2, LED3, LED4 LED5 IC1 J1 J2 J3 IC2 IC3, IC4, IC5 IC6 VVP1 VP VFO VVPC VUP1 UP UFO VUPC J3 Figure 5: Interface Circuit PCB layout Figure 4: BP7B External Connections 4 Component Legend Component Side Top Side Controller Interface: 5 A typical controller interface for the BP7B is shown in figure 4. An on signal (IPM control input low) is generated by pulling the respective control input low (GND) using a CMOS buffer capable of sinking at least 16mA (74HC04 or similar). In the off state the buffer should actively pull the control input high to maintain good noise immunity. Open collector drive that allows the control input to float will degrade common mode noise immunity and is therefore not recommended. If the IPM’s built in protection is activated it will immediately shut down the gate drive to the affected IGBT and pull the associated FO pin low. This causes the VLA606 to pull the fault feedback signal (Pin 9 of J2) low. When a fault is detected by the IPM a fault signal with a minimum duration of 1ms is produced. Any signal on the fault line that is significantly shorter than 1ms can not be a legitimate fault and should be ignored by the controller. Therefore, for a robust noise immune design, it is recommended that an RC filter with a time constant of approximately 10us be added to the fault feedback as shown in figure 4. An active fault signal indicates that severe conditions have caused the IPM’s self protection to operate. The fault feedback signal should be used by the system controller to stop the operation of the circuit until the cause of the fault is identified and corrected. Repetitive fault operations may result in damage to the IPM. Printed Circuit Layout: Figure 5 shows the printed circuit layout of the BP7B interface circuit. The compact 63mm x 102mm circuit board with only 23 components provides a complete isolated seven channel driving circuit with short circuit, over temperature and under voltage protection. This clearly demonstrates the advantage of using LSeries Intelligent Power Modules. One important feature of this PCB is the use of separate shield plane islands for each of the isolated driving circuits, logic level interface, and control power supply. Four of the islands are tied to the common of the IPM’s isolated control power supplies (pins 1, 5, 9 and 13 of J3). The remaining two islands are connected at the logic ground (pin 10 of J2) and 24 VDC power supply ground (pin 2 of J1) respectively. This layout is designed to prevent undesirable coupling of noise between the control side and the floating gate drive channels. The BP7B PCB is designed to plug directly onto the control pins of the L-Series IPM. This configuration helps to maintain good noise immunity by providing minimal interconnection distance. More Information: For more information refer to the following documents available from the Powerex website: (1) L-Series IPM individual data sheets provide the detailed electrical characteristics of L-Series IPMs (2) Application Note – “General Considerations: IGBT & IPM modules”, Provides detailed information on power circuit design including bus bars, snubber circuits, and loss calculations. This document also includes heatsink mechanical requirements and proper mounting procedures. (3) Application Note – “Introduction to IPMs (Intelligent Power Modules)”, Provides detailed information regarding features, operational characteristics, and interface circuit requirements for Intelligent Power Modules. (4) BP6A technical data – provides interface circuit information for L-Series IPMs in the large “D” package. (5) VLA106-24151 and VLA106-24154 individual data sheets provide detailed electrical characteristics for these DC to DC converters. (6) Melcosim loss simulation software - provides quick power loss estimation for L-Series IPMs in three phase inverter applications. 6