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MENDE
L54050
RECOM
Data Sheet IS
June 11, 2007
ISL54048, ISL54049
Ultra Low ON-Resistance, +1.65V to +4.5V,
Single Supply, Dual SPST Analog Switch
The Intersil ISL54048 and ISL54049 devices are low
ON-resistance, low voltage, bidirectional, dual singlepole/single-throw (SPST) analog switches designed to
operate from a single +1.65V to +4.5V supply. Targeted
applications include battery powered equipment that benefit
from low rON (0.29) and fast switching speeds (tON = 40ns,
tOFF = 20ns). The digital logic input is 1.8V logic-compatible
when using a single +3V supply.
Cell phones, for example, often face ASIC functionality
limitations. The number of analog input or GPIO pins may be
limited and digital geometries are not well suited to analog
switch performance. This part may be used to “mux-in”
additional functionality while reducing ASIC design risk. The
ISL54048 and ISL54049 are offered in a small form factor
package, alleviating board space limitations.
The ISL54048 has two normally open (NO) SPST switches
and the ISL54049 has two normally closed (NC) SPST
switches.
FN6469.1
Features
• ON-Resistance (rON)
- V+ = +4.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.29
- V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.33
- V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.55
• rON Matching Between Channels . . . . . . . . . . . . . . . . . 0.06
• rON Flatness Across Signal Range . . . . . . . . . . . . . . . . 0.03
• Single Supply Operation . . . . . . . . . . . . . . . +1.65V to +4.5V
• Low Power Consumption (PD). . . . . . . . . . . . . . . <0.45W
• Fast Switching Action (V+ = +4.3V)
- tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns
- tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ns
• ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>8kV
• 1.8V Logic Compatible (+3V supply)
• Low ICC Current when VinH is not at the V+ Rail
• Available in 10 Ld 1.8mmx1.4mmx0.5mm TQFN
• Pb-free plus anneal available (RoHS compliant)
TABLE 1. FEATURES AT A GLANCE
ISL54048, ISL54049
Applications
• Battery powered, Handheld, and Portable Equipment
- Cellular/mobile Phones
- Pagers
- Laptops, Notebooks, Palmtops
Number of Switches
2
SW
SPST
4.3V rON
0.29
4.3V tON/tOFF
40ns/20ns
3V rON
0.33
3V tON/tOFF
50ns/27ns
1.8V rON
0.55
1.8V tON/tOFF
70ns/54ns
Package
10 Ld 1.8mmx1.4mmx0.5mm
TQFN
• Portable Test and Measurement
• Medical Equipment
• Audio and Video Switching
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
Ordering Information
PART NUMBER (Note)
PART MARKING TEMP. RANGE (°C)
PACKAGE (Pb-Free)
PKG. DWG. #
ISL54048IRUZ-T
B
-40 to +85
10 Ld 1.8x1.4x0.5 TQFN (0.40mm pitch)
Tape and Reel
L10.1.8x1.4A
ISL54049IRUZ-T
C
-40 to +85
10 Ld 1.8x1.4x0.5 TQFN (0.40mm pitch)
Tape and Reel
L10.1.8x1.4A
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL54048, ISL54049
Pinouts
(Note 1)
ISL54049
(10 LD TQFN)
TOP VIEW
ISL54048
(10 LD TQFN)
TOP VIEW
N.C.
GND
NC2
GND
7
6
7
6
IN2
8
5
N.C.
COM2
9
4
IN1
NO2
10
3
COM1
IN2
8
COM2
9
N.C.
10
1
2
1
2
V+
NO1
V+
N.C.
5
NC1
4
IN1
3
COM1
NOTE:
1. Switches Shown for Logic “0” Input.
Truth Table
LOGIC
ISL54048
ISL54049
0
OFF
ON
1
ON
OFF
NOTE:
Logic “0” 0.5V. Logic “1” 1.4V with a 3V supply.
Pin Descriptions
PIN
FUNCTION
V+
System Power Supply Input (+1.65V to +4.5V)
GND
Ground Connection
IN
Digital Control Input
COM
Analog Switch Common Pin
NOx
Analog Switch Normally Open Pin
NCx
Analog Switch Normally Closed Pin
NC
No Connect
2
FN6469.1
June 11, 2007
ISL54048, ISL54049
Absolute Maximum Ratings
Thermal Information
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V
Input Voltages
NO, NC, IN (Note 2). . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)
Output Voltages
COM (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)
Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . 300mA
Peak Current NO, NC, or COM
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . 500mA
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>8kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>500V
Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.4kV
Thermal Resistance (Typical)
JA (°C/W)
10 Ld TQFN Package (Note 3) . . . . . . . . . . . . . . .
143
Maximum Junction Temperature (Plastic Package). . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. Extended operation above the recommended
operating conditions could result in decreased reliability. The Absolute Maximum Ratings are stress only ratings and operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.
3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 3V Supply
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Notes 4, 8),
Unless Otherwise Specified.
PARAMETER
TEST CONDITIONS
TEMP
(°C)
MIN
(NOTE 5)
TYP
MAX
(NOTE 5) UNITS
Full
0
-
V+
V
25
-
0.30
-

Full
-
0.35
-

25
-
0.06
-

Full
-
0.08
-

25
-
0.03
-

Full
-
0.04
-

25
-100
-
100
nA
Full
-195
-
195
nA
25
-100
-
100
nA
Full
-195
-
195
nA
25
-
40
-
ns
Full
-
50
-
ns
25
-
20
-
ns
Full
-
30
-
ns
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON-Resistance, rON
V+ = 3.9V, ICOM = 100mA, VNO or VNC = 0V to V+,
(See Figure 4)
rON Matching Between Channels,
rON
V+ = 3.9V, ICOM = 100mA, VNO or VNC = Voltage at
max rON, (Note 8)
rON Flatness, rFLAT(ON)
V+ = 3.9V, ICOM = 100mA, VNO or VNC = 0V to V+,
(Note 6)
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 4.5V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V
COM ON Leakage Current,
ICOM(ON)
V+ = 4.5V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V,
3V, or floating
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 3.9V, VNO or VNC = 3.0V, RL = 50, CL = 35pF,
(See Figure 1)
Turn-OFF Time, tOFF
V+ = 3.9V, VNO or VNC = 3.0V, RL = 50, CL = 35pF,
(See Figure 1)
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0See Figure 2
25
-
170
-
pC
OFF Isolation
RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 3)
25
-
62
-
dB
Crosstalk (Channel-to-Channel)
RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 5)
25
-
-85
-
dB
Total Harmonic Distortion
f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600
25
-
0.005
-
%
3
FN6469.1
June 11, 2007
ISL54048, ISL54049
Electrical Specifications - 3V Supply
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Notes 4, 8),
Unless Otherwise Specified. (Continued)
TEMP
(°C)
MIN
(NOTE 5)
TYP
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 6)
25
-
62
-
pF
COM ON Capacitance, CCOM(ON)
25
-
176
-
pF
Full
1.65
4.5
V
25
-
-
0.1
A
Full
-
-
1
A
25
-
-
12
A
Input Voltage Low, VINL
Full
-
-
0.5
V
Input Voltage High, VINH
Full
1.6
-
-
V
Full
-0.5
-
0.5
A
PARAMETER
TEST CONDITIONS
f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 6)
MAX
(NOTE 5) UNITS
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current, I+
V+ = +4.5V, VIN = 0V or V+
Positive Supply Current, I+
V+ = +4.2V, VIN = 2.85V
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL
V+ = 4.5V, VIN = 0V or V+
Electrical Specifications - 3V Supply
PARAMETER
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 4, 8),
Unless Otherwise Specified.
TEST CONDITIONS
TEMP
(°C)
MIN
(NOTE 5)
TYP
MAX
(NOTE 5) UNITS
Full
0
-
V+
V
25
-
0.35
0.5

Full
-
-
0.7

25
-
0.06
0.07

ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON-Resistance, rON
V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+,
(See Figure 4)
rON Matching Between Channels,
rON
V+ = 2.7V, ICOM = 100mA, VNO or VNC = Voltage at
max rON, (Note 7)
rON Flatness, rFLAT(ON)
V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+,
(Note 6)
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 3.3V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V
COM ON Leakage Current,
ICOM(ON)
V = 3.3V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V, 3V,
or floating
Full
-
-
0.08

25
-
0.03
0.15

Full
-
-
0.15

25
-
0.9
-
nA
Full
-
30
-
nA
25
-
0.8
-
nA
Full
-
30
-
nA
DYNAMIC CHARACTERISTICS
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF,
(See Figure 1)
Turn-ON Time, tON
Turn-OFF Time, tOFF
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50, CL = 35pF,
(See Figure 1)
25
-
50
-
ns
Full
-
60
-
ns
25
-
27
-
ns
Full
-
35
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0See Figure 2)
25
-
94
-
pC
OFF Isolation
RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 3)
25
-
62
-
dB
Crosstalk (Channel-to-Channel)
RL = 50, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 5)
25
-
-85
-
dB
Total Harmonic Distortion
f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600
25
-
0.005
-
%
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 6)
25
-
65
-
pF
f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 6)
25
-
181
-
pF
COM ON Capacitance, CCOM(ON)
4
FN6469.1
June 11, 2007
ISL54048, ISL54049
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 4, 8),
Unless Otherwise Specified. (Continued)
TEMP
(°C)
MIN
(NOTE 5)
TYP
25
-
0.01
-
A
Full
-
0.52
-
A
Input Voltage Low, VINL
25
-
-
0.5
V
Input Voltage High, VINH
25
1.4
-
-
V
Full
-0.5
-
0.5
A
PARAMETER
TEST CONDITIONS
MAX
(NOTE 5) UNITS
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
V+ = +3.6V, VIN = 0V or V+
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL
V+ = 3.3V, VIN = 0V or V+
Electrical Specifications - 1.8V Supply
PARAMETER
Test Conditions: V+ = +1.65V to +2V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Notes 4, 8),
Unless Otherwise Specified.
TEST CONDITIONS
TEMP
(°C)
MIN
(NOTE 5)
TYP
MAX
(NOTE 5) UNITS
Full
0
-
V+
V
25
-
0.7
0.8

Full
-
-
0.85

25
-
70
-
ns
Full
-
80
-
ns
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
V+ = 1.65V, ICOM = 100mA, VNO or VNC = 0V to V+,
(See Figure 4)
ON-Resistance, rON
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 1.65V, VNO or VNC = 1.0V, RL =50, CL = 35pF,
(See Figure 1)
Turn-OFF Time, tOFF
V+ = 1.65V, VNO or VNC = 1.0V, RL =50, CL = 35pF,
(See Figure 1)
25
-
54
-
ns
Full
-
65
-
ns
25
-
42
-
pC
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 6)
25
-
70
-
pF
f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 6)
25
-
186
-
pF
Input Voltage Low, VINL
25
-
-
0.4
V
Input Voltage High, VINH
25
1.0
-
-
V
Full
-0.5
-
0.5
A
CL = 1.0nF, VG = 0V, RG = 0See Figure 2)
Charge Injection, Q
COM ON Capacitance, CCOM(ON)
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL
V+ = 2.0V, VIN = 0V or V+
NOTES:
4. VIN = input voltage to perform proper function.
5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
6. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
7. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON
value, between Nx1 and Nx2.
8. Parts are 100% tested at +25°C. Limits across full temperature range are guaranteed by design and correlation.
5
FN6469.1
June 11, 2007
ISL54048, ISL54049
Test Circuits and Waveforms
V+
LOGIC
INPUT
V+
tr < 5ns
tf < 5ns
50%
0V
tOFF
SWITCH
INPUT VNx1
SWITCH
INPUT
VOUT
NX1 OR NX2
COM
IN
VOUT
90%
SWITCH
OUTPUT
C
90%
LOGIC
INPUT
CL
35pF
RL
50
GND
0V
tON
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for all switches. CL includes fixture and stray
capacitance.
rL
V OUT = V (NO or NC) ---------------------------R L + r  ON 
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
V+
RG
SWITCH
OUTPUT
VOUT
C
NX1 OR NX2
VOUT
COM
VOUT
VG
GND
V+
OFF
CL
LOGIC
INPUT
ON
ON
LOGIC
INPUT
IN
0V
Repeat test for all switches.
Q = VOUT x CL
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
V+
C
V+
C
SIGNAL
GENERATOR
rON = V1/100mA
NX1 OR NX2
NX1 OR NX2
IN
0V or V+
VNX
100mA
IN
V1
0V or V+
COM
ANALYZER
GND
COM
RL
GND
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
FIGURE 3. OFF ISOLATION TEST CIRCUIT
6
Repeat test for all switches.
FIGURE 4. rON TEST CIRCUIT
FN6469.1
June 11, 2007
ISL54048, ISL54049
Test Circuits and Waveforms (Continued)
V+
V+
C
C
SIGNAL
GENERATOR
NX1 OR NX2
COM
50
NX1 OR NX2
IN1
IN
0V or V+
COM
ANALYZER
0V or V+
IMPEDANCE
ANALYZER
COM
NX1 OR NX2
N.C.
GND
GND
RL
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
FIGURE 5. CROSSTALK TEST CIRCUIT
Repeat test for all switches.
FIGURE 6. CAPACITANCE TEST CIRCUIT
Detailed Description
The ISL54048 and ISL54049 are bidirectional, dual single
pole/single throw (SPST) analog switches that offer precise
switching capability from a single 1.65V to 4.5V supply with
low on-resistance (0.29) and high speed operation
(tON = 40ns, tOFF = 20ns). The devices are especially well
suited for portable battery powered equipment due to their
low operating supply voltage (1.65V), low power
consumption (4.5µW max), low leakage currents (195nA max)
and the tiny µTQFN package. The ultra low ON-resistance
and rON flatness provide very low insertion loss and distortion
to applications that require signal reproduction.
External V+ Series Resistor
For improved ESD and latch-up immunity, Intersil
recommends adding a 100 resistor in series with the V+
power supply pin of the IC (see Figure 7).
During an overvoltage transient event, such as occurs during
system level IEC 61000 ESD testing, substrate currents can
be generated in the IC that can trigger parasitic SCR
structures to turn ON, creating a low impedance path from
the V+ power supply to ground. This will result in a
significant amount of current flow in the IC which can
potentially create a latch-up state or permanently damage
the IC. The external V+ resistor limits the current during this
over-stress situation and has been found to prevent latch-up
or destructive damage for many overvoltage transient
events.
Under normal operation the sub-microamp IDD current of the
IC produces an insignificant voltage drop across the 100
series resistor resulting in no impact to switch operation or
performance.
7
V+
OPTIONAL
PROTECTION
RESISTOR
C
100
NX
COMx
IN
GND
FIGURE 7. V+ SERIES RESISTOR FOR ENHANCED ESD AND
LATCH-UP IMMUNITY
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
Figure 8). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and the input signal
voltages must remain between V+ and GND.
If these conditions cannot be guaranteed, then precautions
must be implemented to prohibit the current and voltage at
the logic pin and signal pins from exceeding the maximum
ratings of the switch. The following two methods can be used
to provided additional protection to limit the current in the
event that the voltage at a signal pin or logic pin goes below
ground or above the V+ rail.
Logic inputs can be protected by adding a 1k resistor in
series with the logic input (see Figure 8). The resistor limits
the input current below the threshold that produces
FN6469.1
June 11, 2007
ISL54048, ISL54049
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low rON switch. Connecting schottky
diodes to the signal pins (as shown in Figure 8) will shunt the
fault current to the supply or to ground thereby protecting the
switch. These schottky diodes must be sized to handle the
expected fault current.
The ISL54048 and ISL54049 have been designed to
minimize the supply current whenever the digital input
voltage is not driven to the supply rails (0V to V+). For
example, driving the device with 2.85V logic (0V to 2.85V)
while operating with a 4.2V supply the device draws only
12µA of current (see Figure 16 for VIN = 2.85V).
Power-Supply Considerations
Frequency Performance
The ISL54048 and ISL54049 construction is typical of most
single supply CMOS analog switches, in that they have two
supply pins: V+ and GND. V+ and GND drive the internal
CMOS switches and set their analog voltage limits. Unlike
switches with a 4V maximum supply voltage, the ISL54048
and ISL54049 5.5V maximum supply voltage provides plenty
of room for the 10% tolerance of 4.3V supplies, as well as
room for overshoot and noise spikes.
In 50 systems, the ISL54048 and ISL54049 have a -3dB
bandwidth of 120MHz (see Figure 21). The frequency
response is very consistent over a wide V+ range, and for
varying analog signal levels.
The minimum recommended supply voltage is 1.65V. It is
important to note that the input signal range, switching times,
and ON-resistance degrade at lower supply voltages. Refer
to “Electrical Specifications” on page 3 and the Typical
Performance Curves on page 9 for details.
OPTIONAL
SCHOTTKY
DIODE
V+
OPTIONAL
PROTECTION
RESISTOR
Leakage Considerations
INX
VNX
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to its output. Off isolation is
the resistance to this feedthrough, while crosstalk indicates
the amount of feedthrough from one switch to another.
Figure 22 details the high off isolation and crosstalk rejection
provided by this part. At 100kHz, off isolation is about 62dB
in 50 systems, decreasing approximately 20dB per decade
as frequency increases. Higher load impedances decrease
off isolation and crosstalk rejection due to the voltage divider
action of the switch OFF impedance and the load
impedance.
VCOM
GND
OPTIONAL
SCHOTTKY
DIODE
FIGURE 8. OVERVOLTAGE PROTECTION
V+ and GND also power the internal logic and level shiftiers.
The level shiftiers convert the input logic levels to switched
V+ and GND signals to drive the analog switch gate
terminals.
This family of switches cannot be operated with bipolar
supplies because the input switching point becomes
negative in this configuration.
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND. One of
these diodes conducts if any analog signal exceeds V+ or
GND.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and V+ or GND.
Logic-Level Thresholds
This switch family are 1.8V logic compatible (0.5V and 1.4V)
over a supply range of 2.7V to 4.5V (see Figure 18). At 2.7V,
the VIL level is about 0.53V. This is still above the 1.8V logic
guaranteed low output maximum level of 0.5V, but noise
margin is reduced.
8
FN6469.1
June 11, 2007
ISL54048, ISL54049
Typical Performance Curves TA = +25°C, Unless Otherwise Specified
0.35
0.30
ICOM = 100mA
ICOM = 100mA
0.34
0.29
V+ = 2.7V
0.28
rON ()
rON ()
0.33
0.27
0.32
0.31
V+ = 3.9V
V+ = 3V
0.30
0.26
0.25
0.29
V+ = 4.3V
0
1
V+ = 4.5V
3
2
4
V+ = 3.3V
0.28
5
0
0.5
1.0
1.5
2.0
VCOM (V)
VCOM (V)
FIGURE 9. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
2.5
0.35
V+ = 4.3V
ICOM = 100mA
ICOM = 100mA
0.65
+85°C
V+ = 1.65V
0.30
rON ()
rON ()
0.55
0.50
V+ = 1.8V
0.45
+25°C
0.25
V+ = 2V
0.40
0.35
-40°C
0.30
0.20
0
0.5
1.0
VCOM (V)
1.5
0
2.0
FIGURE 11. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
0.40
2
3
VCOM (V)
4
0.40
5
V+ = 2.7V
ICOM = 100mA
+85°C
+85°C
0.35
rON ()
0.30
1
FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE
V+ = 3.3V
ICOM = 100mA
0.35
rON ()
3.5
FIGURE 10. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
0.70
0.60
3.0
+25°C
+25°C
0.30
0.25
-40°C
-40°C
0.20
0
0.5
1.0
1.5
2.0
VCOM (V)
2.5
3.0
3.5
FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE
9
0.25
0
0.5
1.0
1.5
VCOM (V)
2.0
2.5
3.0
FIGURE 14. ON-RESISTANCE vs SWITCH VOLTAGE
FN6469.1
June 11, 2007
ISL54048, ISL54049
Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)
0.60
0.55
V+ = 4.2V
SWEEPING BOTH LOGIC INPUTS
+25°C
150
0.50
-40°C
0.45
ION (µA)
rON ()
200
V+ = 1.8V
ICOM = 100mA
+85°C
0.40
100
0.35
50
0.30
0.25
0
0
0.5
1.0
VCOM (V)
1.5
1
2.0
FIGURE 15. ON-RESISTANCE vs SWITCH VOLTAGE
2
3
VIN1 AND VIN2 (V)
4
5
FIGURE 16. SUPPLY CURRENT vs VLOGIC VOLTAGE
200
1.1
1.0
150
VINH AND VINL (V)
0.9
Q (pC)
100
V+ = 4.3V
50
V+ = 1.8V
0
VINH
0.7
VINL
0.6
0.5
V+ = 3V
-50
0.8
0.4
-100
0
1
2
3
4
0.3
1.5
5
2.0
2.5
VCOM (V)
250
200
200
150
+85°C
150
+25°C
100
-40°C
25
1.0
1.5
100
2.5
3.0
V+ (V)
3.5
4.0
FIGURE 19. TURN-ON TIME vs SUPPLY VOLTAGE
10
4.5
4.0
4.5
+85°C
+25°C
50
2.0
3.5
FIGURE 18. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
tOFF (ns)
tON (ns)
FIGURE 17. CHARGE INJECTION vs SWITCH VOLTAGE
3.0
V+ (V)
0
1.0
-40°C
1.5
2.0
2.5
3.0
3.5
4.0
4.5
V+ (V)
FIGURE 20. TURN-OFF TIME vs SUPPLY VOLTAGE
FN6469.1
June 11, 2007
ISL54048, ISL54049
0
-20
0
PHASE
20
40
60
80
RL = 50
VIN = 0.2VP-P to 2VP-P
1M
10M
FREQUENCY (Hz)
100M
FIGURE 21. FREQUENCY RESPONSE
300M
CROSSTALK (dB)
GAIN
10
V+ = 4.3V
-20
20
-30
30
-40
40
-50
-60
50
ISOLATION
60
-70
70
-80
80
CROSSTALK
-90
90
-100
-110
1k
OFF ISOLATION (dB)
-10
V+ = 3.0V
PHASE (°)
NORMALIZED GAIN (dB)
Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)
100
10k
100k
1M
10M
110
100M 500M
FREQUENCY (Hz)
FIGURE 22. CROSSTALK AND OFF ISOLATION
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
114
PROCESS:
Submicron CMOS
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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11
FN6469.1
June 11, 2007
ISL54048, ISL54049
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
D
6
INDEX AREA
2X
A
L10.1.8x1.4A
B
N
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC
PACKAGE
MILLIMETERS
E
SYMBOL
0.10 C
1
2X
2
0.10 C
TOP VIEW
C
A
0.05 C
SIDE VIEW
(DATUM A)
PIN #1 ID
1
2
NX L
NX b 5
10X
0.10 M C A B
0.05 M C
L1
5
(DATUM B)
7
MAX
NOTES
0.50
0.55
-
A1
-
-
0.05
-
0.127 REF
-
b
0.15
0.20
0.25
5
D
1.75
1.80
1.85
-
E
1.35
1.40
1.45
-
e
A1
NOMINAL
0.45
A3
0.10 C
SEATING PLANE
MIN
A
0.40 BSC
-
L
0.35
0.40
0.45
L1
0.45
0.50
0.55
-
N
10
2
Nd
2
3
Ne
3
3

0
-
12
4
Rev. 3 6/06
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
e
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
BOTTOM VIEW
4. All dimensions are in millimeters. Angles are in degrees.
NX (b)
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
CL
(A1)
5
L
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
SECTION "C-C"
e
8. Maximum allowable burrs is 0.076mm in all directions.
TERMINAL TIP
C C
9. JEDEC Reference MO-255.
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
2.20
1.00
0.60
1.00
0.50
1.80
0.40
0.20
0.20
0.40
10 LAND PATTERN
12
FN6469.1
June 11, 2007