INTERSIL ISL54050

ISL54050
®
Data Sheet
March 28, 2007
Ultra Low ON-Resistance, +1.65V to +4.5V,
Single Supply, Dual SPDT Analog Switch
The Intersil ISL54050 device is a low ON-resistance, low
voltage, bidirectional, dual single-pole/double-throw (SPDT)
analog switch designed to operate from a single +1.65V to
+4.5V supply. Targeted applications include battery powered
equipment that benefit from low rON (0.29Ω) and fast
switching speeds (tON = 40ns, tOFF = 20ns). The digital logic
input is 1.8V logic-compatible when using a single +3V supply.
FN6356.1
Features
• Pb-Free Plus Anneal Available (RoHS Compliant)
• Pin Compatible Replacement for the NLAS5223 and
NLAS5223L
• ON Resistance (rON)
- V+ = +4.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.29Ω
- V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.33Ω
- V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.55Ω
• RON Matching Between Channels . . . . . . . . . . . . . . . . 0.06Ω
Cell phones, for example, often face ASIC functionality
limitations. The number of analog input or GPIO pins may be
limited and digital geometries are not well suited to analog
switch performance. This part may be used to “mux-in”
additional functionality while reducing ASIC design risk. The
ISL54050 is offered in small form factor package, alleviating
board space limitations.
• Single Supply Operation . . . . . . . . . . . . . . . +1.65V to +4.5V
The ISL54050 is a committed dual single-pole/double-throw
(SPDT) that consist of two normally open (NO) and two
normally closed (NC) switches. This configuration can be
used as a dual 2-to-1 multiplexer. The ISL54050 is pin
compatible with the NLAS5223 and NLAS5223L.
• ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>8kV
TABLE 1. FEATURES AT A GLANCE
• Low Power Consumption (PD). . . . . . . . . . . . . . . <0.45µW
• Fast Switching Action (V+ = +4.3V)
- tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns
- tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ns
• Break-before-Make
• 1.8V Logic Compatible (+3V supply)
• Low ICC Current when VinH is not at the V+ Rail
ISL54050
• Available in 10 Ld 1.8mmx1.4mmx0.5mm µTQFN
Number of Switches
2
SW
SPDT or 2-1 MUX
4.3V RON
0.29Ω
4.3V tON/tOFF
40ns/20ns
3V RON
0.33Ω
3V tON/tOFF
50ns/27ns
1.8V rON
0.55Ω
1.8V tON/tOFF
70ns/54ns
Package
10 Ld 1.8mmx1.4mmx0.5mm µTQFN
Applications
• Battery powered, Handheld, and Portable Equipment
- Cellular/mobile Phones
- Pagers
- Laptops, Notebooks, Palmtops
• Portable Test and Measurement
• Medical Equipment
• Audio and Video Switching
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
1
• RON Flatness Across Signal Range . . . . . . . . . . . . . . . 0.03Ω
Ordering Information
PART NUMBER
PART
(Note)
MARKING
ISL54050IRUZ-T A
TEMP.
RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
-40 to +85 10 Ld µTQFN L10.1.8x1.4A
Tape and Reel
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both
SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pbfree requirements of IPC/JEDEC J STD-020C.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL54050
Pinout
Pin Descriptions
(Note 1)
ISL54050
(10 LD µTQFN)
TOP VIEW
IN2
NC2
GND
7
6
8
PIN
V+
5
NC1
9
NO2
10
4
3
1
2
V+
NO1
IN1
System Power Supply Input (+1.65V to +4.5V)
GND
Ground Connection
IN
Digital Control Input
COM
COM2
FUNCTION
Analog Switch Common Pin
NO
Analog Switch Normally Open Pin
NC
Analog Switch Normally Closed Pin
COM1
NOTE:
1. Switches Shown for Logic “0” Input.
Truth Table
NOTE:
LOGIC
NC1 and NC2
NO1 and NO2
0
ON
OFF
1
OFF
ON
Logic “0” ≤0.5V. Logic “1” ≥1.4V with a 3V supply.
2
FN6356.1
March 28, 2007
ISL54050
Absolute Maximum Ratings
Thermal Information
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 5.5V
Input Voltages
NO, NC, IN (Note 2). . . . . . . . . . . . . . . . . . . . -0.5V to ((V+) + 0.5V)
Output Voltages
COM (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to ((V+) + 0.5V)
Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . ±300mA
Peak Current NO, NC, or COM
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . ±500mA
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . .>8kV
Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . .>500V
Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . . >1.4kV
Thermal Resistance (Typical)
θJA (°C/W)
10 Ld μTQFN Package (Note 3) . . . . . . . . . . . . . . .
143
Maximum Junction Temperature (Plastic Package). . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C
(Lead Tips Only)
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range
ISL54050IRUZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. Extended operation above the recommended
operating conditions could result in decreased reliability. The Absolute Maximum Ratings are stress only ratings and operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.
3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 4.3V Supply
PARAMETER
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Note 4),
unless otherwise specified
TEST CONDITIONS
TEMP
(°C)
(NOTE 5)
MIN
Full
0
TYP
(NOTE 5)
MAX
UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON-Resistance, rON
V+ = 3.9V, ICOM = 100mA, VNO or VNC = 0V to V+,
(See Figure 5)
rON Matching Between Channels,
ΔrON
V+ = 3.9V, ICOM = 100mA, VNO or VNC = Voltage at
max rON, (Note 7)
rON Flatness, rFLAT(ON)
V+ = 3.9V, ICOM = 100mA, VNO or VNC = 0V to V+,
(Note 6)
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 4.5V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V
COM ON Leakage Current,
ICOM(ON)
V+ = 4.5V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V,
3V or floating
V
V+
25
0.30
Ω
Full
0.35
Ω
25
0.06
Ω
Full
0.08
Ω
25
0.03
Ω
Full
0.04
Ω
25
-100
100
nA
Full
-195
195
nA
25
-100
100
nA
Full
-195
195
nA
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 3.9V, VNO or VNC = 3.0V, RL =50Ω, CL = 35pF,
(See Figure 1)
Turn-OFF Time, tOFF
V+ = 3.9V, VNO or VNC = 3.0V, RL =50Ω, CL = 35pF,
(See Figure 1)
25
40
ns
Full
50
ns
25
20
ns
Full
30
ns
Break-Before-Make Time Delay, tD
V+ = 4.5V, VNO or VNC = 3.0V, RL =50Ω, CL = 35pF,
(See Figure 3)
Full
8
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω, See Figure 2
25
170
pC
OFF Isolation
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 4)
25
62
dB
3
FN6356.1
March 28, 2007
ISL54050
Electrical Specifications - 4.3V Supply
PARAMETER
Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VINH = 1.6V, VINL = 0.5V (Note 4),
unless otherwise specified (Continued)
TEST CONDITIONS
TEMP
(°C)
(NOTE 5)
MIN
TYP
(NOTE 5)
MAX
UNITS
Crosstalk (Channel-to-Channel)
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 6)
25
-85
dB
Total Harmonic Distortion
f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600Ω
25
0.005
%
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
25
62
pF
f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
25
176
pF
COM ON Capacitance, CCOM(ON)
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Full
4.5
V
25
0.1
µA
Full
1
µA
25
12
µA
Input Voltage Low, VINL
Full
0.5
V
Input Voltage High, VINH
Full
1.6
-
V
Full
-0.5
0.5
µA
Positive Supply Current, I+
V+ = +4.5V, VIN = 0V or V+
Positive Supply Current, I+
V+ = +4.2V, VIN = 2.85V
1.65
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL
V+ = 4.5V, VIN = 0V or V+
NOTES:
4. VIN = input voltage to perform proper function.
5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
6. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
7. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON
value, between NC1 and NC2 or between NO1 and NO2.
Electrical Specifications - 3V Supply
PARAMETER
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 4),
unless otherwise specified
TEST CONDITIONS
TEMP
(°C)
(NOTE 5)
MIN
Full
0
TYP
(NOTE 5)
MAX
UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+,
(See Figure 5)
ON-Resistance, rON
rON Matching Between Channels,
ΔrON
V+ = 2.7V, ICOM = 100mA, VNO or VNC = Voltage at
max rON, (Note 7)
rON Flatness, rFLAT(ON)
V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+,
(Note 6)
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 3.3V, VCOM = 0.3V, 3V, VNO or VNC = 3V, 0.3V
COM ON Leakage Current,
ICOM(ON)
V+ = 3.3V, VCOM = 0.3V, 3V, or VNO or VNC = 0.3V, 3V,
or floating
25
V+
V
0.5
Ω
0.7
Ω
0.06
0.07
Ω
0.08
Ω
0.03
0.15
Ω
0.15
Ω
0.35
Full
25
Full
25
Full
25
0.9
nA
Full
30
nA
25
0.8
nA
Full
30
nA
DYNAMIC CHARACTERISTICS
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF,
(See Figure 1)
Turn-ON Time, tON
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF,
(See Figure 1)
Turn-OFF Time, tOFF
4
25
50
ns
Full
60
ns
25
27
ns
Full
35
ns
FN6356.1
March 28, 2007
ISL54050
Electrical Specifications - 3V Supply
PARAMETER
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Note 4),
unless otherwise specified (Continued)
TEST CONDITIONS
TEMP
(°C)
(NOTE 5)
MIN
TYP
(NOTE 5)
MAX
UNITS
Break-Before-Make Time Delay, tD
V+ = 3.3V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF,
(See Figure 3)
Full
9
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2)
25
94
pC
OFF Isolation
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 4)
25
62
dB
Crosstalk (Channel-to-Channel)
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS,
(See Figure 6)
25
-85
dB
Total Harmonic Distortion
f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 600Ω
25
0.005
%
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
25
65
pF
f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
25
181
pF
25
0.01
μA
Full
0.52
μA
COM ON Capacitance, CCOM(ON)
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
V+ = +3.6V, VIN = 0V or V+
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
25
Input Voltage High, VINH
25
1.4
Full
-0.5
Input Current, IINH, IINL
V+ = 3.3V, VIN = 0V or V+
Electrical Specifications - 1.8V Supply
PARAMETER
0.5
V
V
μA
0.5
Test Conditions: V+ = +1.65V to +2V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Note 4),
unless otherwise specified
TEST CONDITIONS
TEMP
(°C)
(NOTE 5)
MIN
Full
0
TYP
(NOTE 5)
MAX
UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
V+ = 1.65V, ICOM = 100mA, VNO or VNC = 0V to V+,
(See Figure 5)
ON-Resistance, rON
25
0.7
Full
V+
V
0.8
Ω
0.85
Ω
DYNAMIC CHARACTERISTICS
V+ = 1.65V, VNO or VNC = 1.0V, RL =50Ω, CL = 35pF,
(See Figure 1)
Turn-ON Time, tON
V+ = 1.65V, VNO or VNC = 1.0V, RL =50Ω, CL = 35pF,
(See Figure 1)
Turn-OFF Time, tOFF
25
70
ns
Full
80
ns
25
54
ns
Full
65
ns
Break-Before-Make Time Delay, td
V+ = 2.0V, VNO or VNC = 1.0V, RL =50Ω, CL = 35pF,
(See Figure 3)
Full
10
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2)
25
42
pC
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
25
70
pF
f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7)
25
186
pF
COM ON Capacitance, CCOM(ON)
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
25
Input Voltage High, VINH
25
1.0
Full
-0.5
Input Current, IINH, IINL
V+ = 2.0V, VIN = 0V or V+
5
0.4
V
V
0.5
μA
FN6356.1
March 28, 2007
ISL54050
Test Circuits and Waveforms
V+
V+
LOGIC
INPUT
tr < 5ns
tf < 5ns
50%
C
0V
tOFF
SWITCH
INPUT VNO
SWITCH
INPUT
COM
IN
VOUT
90%
SWITCH
OUTPUT
VOUT
NO or NC
90%
LOGIC
INPUT
CL
35pF
RL
50Ω
GND
0V
tON
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for all switches. CL includes fixture and stray
capacitance.
RL
V OUT = V (NO or NC) ---------------------------R L + r ( ON )
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
V+
SWITCH
OUTPUT
VOUT
RG
ΔVOUT
V+
LOGIC
INPUT
ON
ON
C
VG
VOUT
COM
NO or NC
GND
IN
CL
OFF
0V
LOGIC
INPUT
Q = ΔVOUT x CL
Repeat test for all switches.
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
V+
C
V+
LOGIC
INPUT
VNX
0V
NO
VOUT
COM
NC
SWITCH
OUTPUT
VOUT
90%
LOGIC
INPUT
0V
tD
FIGURE 3A. MEASUREMENT POINTS
CL
35pF
RL
50Ω
IN
GND
Repeat test for all switches. CL includes fixture and stray
capacitance.
FIGURE 3B. TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
6
FN6356.1
March 28, 2007
ISL54050
Test Circuits and Waveforms (Continued)
V+
C
V+
C
SIGNAL
GENERATOR
rON = V1/100mA
NO or NC
NO or NC
IN
VNX
0V or V+
100mA
IN
V1
0V or V+
COM
ANALYZER
GND
COM
RL
GND
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
Repeat test for all switches.
FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. RON TEST CIRCUIT
V+
C
V+
C
SIGNAL
GENERATOR
NO or NC
COM
50Ω
NO or NC
IN1
IN
0V or V+
0V or V+
IMPEDANCE
ANALYZER
NC or NO
COM
ANALYZER
COM
N.C.
GND
RL
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
FIGURE 6. CROSSTALK TEST CIRCUIT
Detailed Description
The ISL54050 is a bidirectional, dual single pole/double
throw (SPDT) analog switch that offers precise switching
capability from a single 1.65V to 4.5V supply with low
on-resistance (0.29Ω) and high speed operation
(tON = 40ns, tOFF = 20ns). The device is especially well
suited for portable battery powered equipment due to its low
operating supply voltage (1.65V), low power consumption
(4.5μW max), low leakage currents (195nA max), and the tiny
μTQFN package. The ultra low on-resistance and rON
flatness provide very low insertion loss and distortion to
applications that require signal reproduction.
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
7
GND
Repeat test for all switches.
FIGURE 7. CAPACITANCE TEST CIRCUIT
ESD protection diodes from the pin to V+ and to GND (see
Figure 8). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and the input signal
voltages must remain between V+ and GND.
If these conditions cannot be guaranteed, then precautions
must be implemented to prohibit the current and voltage at
the logic pin and signal pins from exceeding the maximum
ratings of the switch. The following two methods can be used
to provided additional protection to limit the current in the
event that the voltage at a signal pin or logic pin goes below
ground or above the V+ rail.
Logic inputs can be protected by adding a 1kΩ resistor in
series with the logic input (see Figure 8). The resistor limits
the input current below the threshold that produces
permanent damage, and the sub-microamp input current
FN6356.1
March 28, 2007
ISL54050
produces an insignificant voltage drop during normal
operation.
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low RON switch. Connecting schottky
diodes to the signal pins as shown in Figure 8 will shunt the
fault current to the supply or to ground thereby protecting the
switch. These schottky diodes must be sized to handle the
expected fault current.
OPTIONAL
SCHOTTKY
DIODE
The ISL54050 has been designed to minimize the supply
current whenever the digital input voltage is not driven to the
supply rails (0V to V+). For example, driving the device with
2.85V logic (0V to 2.85V) while operating with a 4.2V supply,
the device draws only 12μA of current (see Figure 16 for
VIN = 2.85V).
Frequency Performance
In 50Ω systems, the ISL54050 has a -3dB bandwidth of
120MHz (see Figure 21). The frequency response is very
consistent over a wide V+ range and for varying analog
signal levels.
V+
OPTIONAL
PROTECTION
RESISTOR
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
INX
VNX
VCOM
GND
OPTIONAL
SCHOTTKY
DIODE
FIGURE 8. OVERVOLTAGE PROTECTION
Power-Supply Considerations
The ISL54050 construction is typical of most single supply
CMOS analog switches, in that they have two supply pins:
V+ and GND. V+ and GND drive the internal CMOS
switches and set their analog voltage limits. Unlike switches
with a 4V maximum supply voltage, the ISL54050 5.5V
maximum supply voltage provides plenty of room for the
10% tolerance of 4.3V supplies, as well as room for
overshoot and noise spikes.
The minimum recommended supply voltage is 1.65V. It is
important to note that the input signal range, switching times,
and on-resistance degrade at lower supply voltages. Refer
to the Electrical Specification tables and “Typical
Performance Curves” on page 9 for details.
V+ and GND also power the internal logic and level shifters.
The level shifters convert the input logic levels to switched
V+ and GND signals to drive the analog switch gate
terminals.
This family of switches cannot be operated with bipolar
supplies, because the input switching point becomes
negative in this configuration.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to its output. Off isolation is
the resistance to this feedthrough, while crosstalk indicates
the amount of feedthrough from one switch to another.
Figure 22 details the high off isolation and crosstalk rejection
provided by this part. At 100kHz, off isolation is about 62dB
in 50Ω systems, decreasing approximately 20dB per decade
as frequency increases. Higher load impedances decrease
off isolation and crosstalk rejection due to the voltage divider
action of the switch OFF impedance and the load
impedance.
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND. One of
these diodes conducts if any analog signal exceeds V+ or
GND.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the
analog-signal-path leakage current. All analog leakage
current flows between each pin and one of the supply
terminals, not to the other switch terminal. This is why both
sides of a given switch can show leakage currents of the
same or opposite polarity. There is no connection between
the analog signal paths and V+ or GND.
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.5V and 1.4V)
over a supply range of 2.7V to 4.5V (see Figure 16). At 2.7V
the VIL level is about 0.53V. This is still above the 1.8V
CMOS guaranteed low output maximum level of 0.5V, but
noise margin is reduced.
8
FN6356.1
March 28, 2007
ISL54050
Typical Performance Curves TA = +25°C, Unless Otherwise Specified
0.35
0.30
ICOM = 100mA
ICOM = 100mA
0.34
0.29
0.28
rON (Ω)
rON (Ω)
0.33
0.27
V+ = 2.7V
0.32
0.31
V+ = 3.9V
V+ = 3V
0.30
0.26
0.25
V+ = 4.3V
0.29
V+ = 4.5V
0
1
2
V+ = 3.3V
0.28
3
4
5
0
0.5
1.0
1.5
2.0
VCOM (V)
VCOM (V)
FIGURE 9. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
2.5
0.35
ICOM = 100mA
V+ = 4.3V
ICOM = 100mA
0.65
V+ = 1.65V
rON (Ω)
rON (Ω)
+85°C
0.30
0.55
V+ = 1.8V
0.50
3.5
FIGURE 10. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
0.70
0.60
3.0
+25°C
0.45
0.25
V+ = 2V
0.40
0.35
-40°C
0.30
0.20
0
0.5
1.0
1.5
2.0
0
VCOM (V)
FIGURE 11. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
0.40
5
V+ = 2.7V
ICOM = 100mA
+85°C
0.35
rON (Ω)
rON (Ω)
4
0.40
+85°C
0.30
2
3
VCOM (V)
FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE
V+ = 3.3V
ICOM = 100mA
0.35
1
+25°C
+25°C
0.30
0.25
0.20
-40°C
0
0.5
1.0
-40°C
1.5
2.0
VCOM (V)
2.5
3.0
3.5
FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE
9
0.25
0
0.5
1.0
1.5
VCOM (V)
2.0
2.5
3.0
FIGURE 14. ON-RESISTANCE vs SWITCH VOLTAGE
FN6356.1
March 28, 2007
ISL54050
Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)
0.60
0.55
V+ = 4.2V
SWEEPING BOTH LOGIC INPUTS
+25°C
150
0.50
-40°C
0.45
iON (μA)
rON (Ω)
200
V+ = 1.8V
ICOM = 100mA
+85°C
0.40
0.35
100
50
0.30
0.25
0
0
0.5
1.0
VCOM (V)
1.5
1
2.0
FIGURE 15. ON-RESISTANCE vs SWITCH VOLTAGE
2
3
VIN1 AND VIN2 (V)
4
5
FIGURE 16. SUPPLY CURRENT vs VLOGIC VOLTAGE
200
1.1
VINH
1.0
150
0.9
VINH AND VINL (V)
Q (pC)
100
V+ = 4.3V
50
V+ = 1.8V
0
V+ = 3V
-50
-100
0.8
0.7
0.6
0.5
VINL
0.4
0
1
2
3
4
0.3
1.5
5
2.0
2.5
VCOM (V)
250
200
200
150
+85°C
150
+25°C
100
-40°C
25
1.0
1.5
100
2.5
3.0
V+ (V)
3.5
4.0
FIGURE 19. TURN-ON TIME vs SUPPLY VOLTAGE
10
4.5
4.0
4.5
+85°C
+25°C
50
2.0
3.5
FIGURE 18. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
tOFF (ns)
tON (ns)
FIGURE 17. CHARGE INJECTION vs SWITCH VOLTAGE
3.0
V+ (V)
0
1.0
-40°C
1.5
2.0
2.5
3.0
V+ (V)
3.5
4.0
4.5
FIGURE 20. TURN-OFF TIME vs SUPPLY VOLTAGE
FN6356.1
March 28, 2007
ISL54050
-10
V+ = 3V
0
GAIN
0
PHASE
40
60
80
RL = 50Ω
VIN = 0.2VP-P to 2VP-P
1
PHASE (°)
20
100
10
100
FREQUENCY (MHz)
FIGURE 21. FREQUENCY RESPONSE
600
CROSSTALK (dB)
-20
10
V+ = 4.3V
-20
20
-30
30
-40
40
-50
-60
50
ISOLATION
-70
70
-80
80
CROSSTALK
-90
-100
-110
1k
60
OFF ISOLATION (dB)
NORMALIZED GAIN (dB)
Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)
90
100
10k
100k
1M
10M
FREQUENCY (kHz)
110
100M500M
FIGURE 22. CROSSTALK AND OFF ISOLATION
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
114
PROCESS:
Submicron CMOS
11
FN6356.1
March 28, 2007
ISL54050
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
D
6
INDEX AREA
A
L10.1.8x1.4A
B
N
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC
PACKAGE
MILLIMETERS
E
SYMBOL
2X
MIN
NOMINAL
MAX
NOTES
0.10 C
1
2X
2
0.10 C
TOP VIEW
0.45
0.50
0.55
-
A1
-
-
0.05
-
A3
0.10 C
C
A
0.05 C
A
0.127 REF
0.15
0.20
0.25
5
D
1.75
1.80
1.85
-
E
1.35
1.40
1.45
-
e
SEATING PLANE
A1
SIDE VIEW
(DATUM A)
PIN #1 ID
NX L
1
NX b 5
10X
0.10 M C A B
0.05 M C
2
L1
5
(DATUM B)
7
-
b
0.40 BSC
-
L
0.35
0.40
0.45
L1
0.45
0.50
0.55
-
N
10
2
Nd
2
3
Ne
3
3
θ
0
-
12
4
Rev. 3 6/06
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
e
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
BOTTOM VIEW
4. All dimensions are in millimeters. Angles are in degrees.
NX (b)
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
CL
(A1)
5
L
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
SECTION "C-C"
e
8. Maximum allowable burrs is 0.076mm in all directions.
TERMINAL TIP
C C
2.20
1.00
0.60
1.00
9. JEDEC Reference MO-255.
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
0.50
1.80
0.40
0.20
0.20
0.40
10 LAND PATTERN
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12
FN6356.1
March 28, 2007