DATASHEET

DATASHEET
Low-Voltage, Dual Supply, SPST, High Performance
Analog Switches
ISL43112, ISL43113
Features
The Intersil ISL43112 and ISL43113 are precision, high
performance analog switches designed to operate from ±1.5V
to ±6V supplies. These devices are fully specified for 10%
tolerance ±5V and ±3.3V supplies and feature supply and
leakage currents much lower than those of other single SPST
switches. Turn-on and turn-off times are also improved.
• Fully specified at VS = ±5V and ±3.3V for 10% tolerances
Targeted applications include battery powered equipment that
benefit from the devices’ low power consumption (250µW),
sub-nanoamp leakage currents and fast switching speeds
(tON = 40ns, tOFF = 25ns). The small SOT-23 packages and
timing that delivers break-before-make operation, make this
family ideal for custom multiplexer applications. Additionally,
excellent rON flatness maintains signal fidelity over the whole
input range, while micro packaging alleviates board space
limitations. All these benefits combine to make Intersil’s
newest line of low-voltage switches ideal solutions for “Next
Generation” designs.
• Charge injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7pC
The ISL4311x are Single-Pole/Single-Throw (SPST) switches, with
the ISL43112 being Normally Open (NO) and the ISL43113 being
Normally Closed (NC).
• RoHS Compliant
Table 1 summarizes the performance of this family. For single
supply versions, see the ISL43110, ISL43111 datasheet.
• Battery powered, handheld, and portable equipment
- Cellular/mobile phones, pagers
- Laptops, notebooks, palmtops, PDA’s
TABLE 1. FEATURES AT A GLANCE
FEATURES
ISL43112
ISL43113
Number of Switches
1
1
Configuration
NO
NC
±4.5V rON
15Ω
15Ω
±4.5V tON / tOFF
42ns/25ns
42ns/25ns
±3V rON
20Ω
20Ω
±3V tON / tOFF
58ns/37ns
58ns/37ns
Packages
8 Ld SOIC, 5 Ld SOT-23
Related Literature
• TB363,“Guidelines for Handling and Processing Moisture
Sensitive Surface Mount Devices (SMDs)”
December 11, 2015
FN6029.3
1
• Available in SOT-23 packaging
• Dual supply operation. . . . . . . . . . . . . . . . . . . . . . . . . ±1.5V to ±6V
• ON-resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Ω
• rON flatness. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Ω
• Low leakage current (maximum at 85°C) 5nA (off leakage)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20nA (on leakage)
• Fast switching action
- tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns
- tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns
• Break-before-make operation at VS = ±5V
• Minimum 2000V ESD protection per Method 3015.7
• CMOS logic compatible
Applications
• Communications systems
- Radios
- PBX, PABX
• Test equipment
- Logic and spectrum analyzers
- Portable meters, DVM, DMM
• Medical equipment
- Ultrasound, MRI, CAT SCAN
- Electrocardiograph, blood analyzer
• Audio and video switching
• General purpose circuits
- Low voltage DACs and ADCs
- Sample and hold circuits
- Digital filters
- Operational amplifier gain switching networks
- High frequency analog switching
- High-speed multiplexing
- Integrator reset circuits
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2002, 2004, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL43112, ISL43113
Pin Configurations
(Note 1)
ISL43112
(5 LD SOT-23)
TOP VIEW
ISL43112
(8LD SOIC)
TOP VIEW
COM 1
8 NO
N.C.
2
7 V-
N.C.
3
6 IN
V+
4
5 N.C.
NO
2
4 IN
V- 3
ISL43113
(5 LD SOT-23)
TOP VIEW
ISL43113
(8LD SOIC)
TOP VIEW
COM 1
5 V+
COM 1
8 NC
N.C.
2
7 V-
N.C.
3
6 IN
V+
4
5 N.C.
5 V+
COM 1
NC
2
4 IN
V- 3
NOTE:
1. Switches Shown for Logic “0” Input.
Pin Descriptions
PIN
FUNCTION
V+
System Positive Power Supply Input (+1.5V to +6V)
V-
System Negative Power Supply Input (-1.5V to -6V)
IN
CMOS Compatible Digital Control Input
COM
Analog Switch Common Pin
NO
Analog Switch Normally Open Pin
NC
Analog Switch Normally Closed Pin
N.C.
No Internal Connection
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Truth Table
LOGIC
ISL43112
ISL43113
0
OFF
ON
1
ON
OFF
NOTE: Logic “0”  1.5V; Logic “1” 3.5V at VS = 5V
FN6029.3
December 11, 2015
ISL43112, ISL43113
Ordering Information
PART NUMBER
(Notes 3, 4)
PART MARKING
TEMP.
RANGE (°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL43112IBZ
ISL431 12IBZ
-40 to +85
8 Ld SOIC
M8.15
ISL43112IBZ-T (Note 2)
ISL431 12IBZ
-40 to +85
8 Ld SOIC
M8.15
ISL43112IHZ-T (Note 2)
112Z (Note 5)
-40 to +85
5 Ld SOT-23
P5.064
ISL43113IBZ
ISL431 13IBZ
-40 to +85
8 Ld SOIC
M8.15
ISL43113IBZ-T (Note 2)
ISL431 13IBZ
-40 to +85
8 Ld SOIC
M8.15
ISL43113IHZ-T (Note 2)
113Z (Note 5)
-40 to +85
5 Ld SOT-23
P5.064
NOTES:
2. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see product information page for ISL43112, ISL43113. For more information on MSL, please see tech
brief TB363.
5. The part marking is located on the bottom of the part.
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ISL43112, ISL43113
Absolute Maximum Ratings
Thermal Information
V+ to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 15V
Input Voltages
IN (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ((V-) - 0.3V) to ((V+) + 0.3V)
NO, NC (Note 6). . . . . . . . . . . . . . . . . . . . . . . . . . ((V-) - 0.3V) to ((V+) + 0.3V)
Output Voltages
COM (Note 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . ((V-) - 0.3V) to ((V+) + 0.3V)
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Peak Current NO, NC, or COM
(Pulsed 1ms, 10% Duty Cycle, Max). . . . . . . . . . . . . . . . . . . . . . . . . 30mA
ESD Rating (Per MIL-STD-883 Method 3015) . . . . . . . . . . . . . . . . . . . . >2kV
Thermal Resistance (Typical, Note 7)
JA (°C/W)
5 Ld SOT-23 Package. . . . . . . . . . . . . . . . . . . . . . . . . . . .
225
8 Ld SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
170
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . . 150°C
Moisture Sensitivity (See Technical Brief TB363)
All Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1
Maximum Storage Temperature Range. . . . . . . . . . . . . . . . . . -65°C to 150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Operating Conditions
Temperature Range ISL4311XIX . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
6. Signals on NO, NC, COM, or IN exceeding V+ or V- are clamped by internal diodes. Limit forward diode current to maximum current ratings.
7. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
±5V Supply: Test Conditions: VSUPPLY = ±4.5V to ±5.5V, VINH = 3.5V, VINL = 1.5V (Note 8),
unless otherwise specified.Boldface limits apply across the operating temperature range, -40°C to +85°C.
TEMP
(°C)
MIN
(Note 9)
TYP
MAX
(Note 9)
UNIT
Full
V-
-
V+
V
+25
-
15
20
Ω
Full
-
-
25
Ω
+25
-
5
6
Ω
Full
-
-
8
Ω
VS = ±5.5V, VCOM = ±4.5V, VNO or VNC = +4.5V, Note 10
+25
-1
0.01
1
nA
Full
-5
-
5
nA
COM OFF Leakage Current, ICOM(OFF) VS = ±5.5V, VCOM = ±4.5V, VNO or VNC = +4.5V, Note 10
+25
-1
0.01
1
nA
Full
-5
-
5
nA
+25
-2
0.01
2
nA
Full
-20
-
20
nA
Input Voltage High, VINH
Full
(V+) - 1.5
-
V+
V
Input Voltage Low, VINL
Full
V-
-
(V+) - 3.5
V
VS = ±5.5V, VIN = 0V or V+
Full
-0.5
-
0.5
µA
Turn-ON Time, tON
VNO or VNC = 3V, RL = 300Ω, CL = 35pF,
VIN = 0 to V+, see Figure 1
+25
-
42
70
ns
Full
-
46
85
ns
Turn-OFF Time, tOFF
VNO or VNC = 3V, RL = 300Ω, CL = 35pF,
VIN = 0 to V+, see Figure 1
+25
-
25
45
ns
Full
-
27
50
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω, see Figure 2
+25
-
7
20
pC
OFF Isolation
RL = 50Ω, CL = 15pF, f = 100kHz, see Figure 3
+25
-
>90
-
dB
Power Supply Rejection Ratio
RL = 50Ω, CL = 5pF, f = 1MHz
+25
-
58
-
dB
NO or NC OFF Capacitance, COFF
f = 1MHz, VNO or VNC = VCOM = 0V, see Figure 5
+25
-
13
-
pF
COM OFF Capacitance, CCOM(OFF)
f = 1MHz, VNO or VNC = VCOM = 0V, see Figure 5
+25
-
13
-
pF
COM ON Capacitance, CCOM(ON)
f = 1MHz, VNO or VNC = VCOM = 0V, see Figure 5
+25
-
30
-
pF
PARAMETER
TEST CONDITIONS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON-Resistance, rON
VS = ±4.5V, ICOM = 1.0mA, VCOM = 3V, see Figure 4
rON Flatness, rFLAT(ON)
VS = ±4.5V, ICOM = 1.0mA, VCOM = -3V, 0V, 3V
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
COM ON Leakage Current, ICOM(ON)
VS = ±5.5V, VCOM = VNO or VNC = ±4.5V, Note 10
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL
DYNAMIC CHARACTERISTICS
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ISL43112, ISL43113
Electrical Specifications
±5V Supply: Test Conditions: VSUPPLY = ±4.5V to ±5.5V, VINH = 3.5V, VINL = 1.5V (Note 8),
unless otherwise specified.Boldface limits apply across the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
TEST CONDITIONS
TEMP
(°C)
MIN
(Note 9)
TYP
MAX
(Note 9)
UNIT
Full
±1.5
-
±6
V
+25
-
15
25
µA
Full
-
22
50
µA
+25
-25
-15
-
µA
Full
-50
-22
-
µA
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current, I+
VS = ±5.5V, VIN = 0V or V+, Switch On or Off
Negative Supply Current, I-
VS = ±5.5V, VIN = 0V or V+, Switch On or Off
NOTES:
8. VIN = Input voltage to perform proper function.
9. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this datasheet.
10. Leakage parameter is 100% tested at high temperature and established by correlation at +25°C.
Electrical Specifications
±3.3V supply test conditions: VSUPPLY = ±3.0V to ±3.6V, VINH = V+, VINL = 0V (Note 8),
unless otherwise specified. Boldface limits apply across the operating temperature range, -40°C to +85°C.
TEMP
(°C)
MIN
(Note 9)
TYP
MAX
(Note 9)
UNIT
Full
V-
-
V+
V
+25
-
20
30
Ω
Full
-
25
40
Ω
+25
-
4
8
Ω
Full
-
5
10
Ω
+25
-1
-
1
nA
Full
-5
-
5
nA
+25
-1
-
1
nA
Full
-5
-
5
nA
+25
-2
-
2
nA
Full
-20
-
20
nA
Input Voltage High, VINH
Full
2.0
1.6
-
V
Input Voltage Low, VINL
Full
-
0.9
0.6
V
VS = ±3.6V, VIN = V- or V+
Full
-0.5
-
0.5
µA
VNO or VNC = 2V, RL = 300Ω, CL = 35pF, VIN = 0.4V to
2.4V
+25
-
58
100
ns
Full
-
62
110
ns
VNO or VNC = 2V, RL = 300Ω, CL = 35pF, VIN = 0.4V to
2.4V
+25
-
37
65
ns
Full
-
40
75
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω
+25
-
5
12
pC
OFF Isolation
RL = 50Ω, CL = 15pF, f = 100kHz
+25
-
>90
-
dB
Power Supply Rejection Ratio
RL = 50Ω, CL = 5pF, f = 1MHz
+25
-
55
-
dB
NO or NC OFF Capacitance, COFF
f = 1MHz, VNO or VNC = VCOM = 0V
+25
-
13
-
pF
COM OFF Capacitance, CCOM(OFF)
f = 1MHz, VNO or VNC = VCOM = 0V
+25
-
13
-
pF
PARAMETER
TEST CONDITIONS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON-Resistance, rON
VS = ±3V, ICOM = 1.0mA, VCOM = 2V
rON Flatness, rFLAT(ON)
VS = ±3V, ICOM = 1.0mA, VCOM = -1.5V, 0V, 1.5V
VS = ±3.3V, VCOM = 2V, VNO or VNC = +2V, Note 10
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
COM OFF Leakage Current, ICOM(OFF) VS = ±3.3V, VCOM = 2V, VNO or VNC = +2V, Note 10
COM ON Leakage Current, ICOM(ON)
VS = ±3.3V, VCOM = VNO or VNC = ±2V, Note 10
DIGITAL INPUT CHARACTERISTICS
Input Current, IINH, IINL
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
Turn-OFF Time, tOFF
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FN6029.3
December 11, 2015
ISL43112, ISL43113
Electrical Specifications
±3.3V supply test conditions: VSUPPLY = ±3.0V to ±3.6V, VINH = V+, VINL = 0V (Note 8),
unless otherwise specified. Boldface limits apply across the operating temperature range, -40°C to +85°C. (Continued)
TEMP
(°C)
MIN
(Note 9)
TYP
MAX
(Note 9)
UNIT
f = 1MHz, VNO or VNC = VCOM = 0V
+25
-
30
-
pF
VS = ±3.6V, VIN = V- or V+, Switch On or Off
+25
-
10
25
µA
Full
-
15
50
µA
+25
-25
-10
-
µA
Full
-50
-15
-
µA
PARAMETER
TEST CONDITIONS
COM ON Capacitance, CCOM(ON)
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
Negative Supply Current, I-
VS = ±3.6V, VIN = V- or V+, Switch On or Off
Test Circuits and Waveforms
V+
tr < 20ns
tf < 20ns
V+
LOGIC
INPUT
50%
0V
tOFF
SWITCH
INPUT
SWITCH
INPUT
VOUT
VOUT
NO or NC
COM
IN
90%
SWITCH
OUTPUT
C
90%
0V
tON
C
Logic input waveform is inverted for switches that have the opposite
logic sense.
CL
35pF
RL
300Ω
LOGIC
INPUT
V-
CL includes fixture and stray capacitance.
V OUT = V
FIGURE 1A. MEASUREMENT POINTS
RL
-----------------------------(NO or NC) R + R
L
 ON 
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
V+
SWITCH
OUTPUT
VOUT
LOGIC
INPUT
RG
VOUT
ON
ON
OFF
NO or NC
VG
VOUT
COM
IN
CL
LOGIC
INPUT
C
Q = VOUT x CL
C
V-
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
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ISL43112, ISL43113
Test Circuits and Waveforms (Continued)
V+
V+
C
C
rON = V1/1mA
SIGNAL
GENERATOR
COM
NO or NC
VCOM
IN
1mA
V- or V+
IN
V1
VINL or VINH
COM
ANALYZER
NO or NC
RL
C
C
V-
V-
FIGURE 3. OFF-ISOLATION TEST CIRCUIT
FIGURE 4. rON TEST CIRCUIT
V+
NO or NC
V- or V+
IN
IMPEDANCE
ANALYZER
COM
V-
FIGURE 5. CAPACITANCE TEST CIRCUIT
Detailed Description
The ISL43112 and ISL43113 analog switches offer precise
switching capability from ±1.5V to ±6V supplies with low
On-resistance (15Ω) and high-speed operation (tON = 40ns,
tOFF = 25ns). The devices are especially well suited to portable
battery powered equipment thanks to the low operating supply
voltage (±1.5V), low power consumption (250µW), low leakage
currents (2nA max) and the tiny SOT-23 packaging. High frequency
applications also benefit from the wide bandwidth, and the very
high off isolation.
Supply Sequencing And Overvoltage
Protection
As with any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to V- (see Figure 6).
To prevent forward biasing these diodes, V+ and V- must be
applied before any input signals, and input signal voltages must
remain between V+ and V-. If these conditions cannot be
guaranteed, then one of the following two protection methods
should be employed.
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Logic inputs can easily be protected by adding a 1kΩ resistor in
series with the input (see Figure 6).
OPTIONAL PROTECTION
DIODE
V+
OPTIONAL
PROTECTION
RESISTOR
IN
VNO or NC
VCOM
VOPTIONAL PROTECTION
DIODE
FIGURE 6. OVERVOLTAGE PROTECTION
The resistor limits the input current below the threshold that
produces permanent damage, and the sub-microamp input
current produces an insignificant voltage drop during normal
operation.
FN6029.3
December 11, 2015
ISL43112, ISL43113
Adding a series resistor to the switch input defeats the purpose
of using a low rON switch, so two small signal diodes can be
added in series with the supply pins to provide overvoltage
protection for all pins (see Figure 6). These additional diodes
limit the analog signal from 1V below V+ to 1V above V-. The low
leakage current performance is unaffected by this approach, but
the switch resistance may increase, especially at low supply
voltages.
Power-Supply Considerations
The ISL4311x construction is typical of most CMOS analog
switches, except that there are only two supply pins: V+ and V-.
The power supplies need not be symmetrical for useful
operation. As long as the total supply voltage (V+ to V-, including
supply tolerances, overshoot, and noise spikes) is less than the
15V maximum supply rating, and the digital input switching point
remains reasonable (see “Logic-Level Thresholds” section), the
ISL43112, ISL43113 function well. The 15V maximum supply
rating provides the designer of 12V systems much greater
flexibility than switches with a 13V maximum supply voltage.
The minimum recommended supply voltage is ±1.5V. It is
important to note that the input signal range, switching times
and On-resistance degrade at lower supply voltages, and the
digital input VIL becomes negative at VS ±2V. Refer to the
“Typical Performance Curves” for details.
V+ and V- power the internal CMOS switches and set their analog
voltage limits. These supplies also power the internal logic and
level shifters. The level shifters convert the input logic levels to
switched V+ and V- signals to drive the analog switch gate
terminals.
This family of switches is not recommended for single supply
applications. For single supply, similar performance, pin
compatible, TTL compatible versions of these switches, see the
ISL43110, ISL43111 datasheet.
High-Frequency Performance
In 5Ωsystems, signal response is reasonably flat to 30MHz,
with a -3dB bandwidth of nearly 400MHz (see Figure 15).
Figure 15 also illustrates that the frequency response is very
consistent over a wide V+ range, and for varying analog signal
levels.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal feedthrough
from a switch’s input to its output. OFF Isolation is the resistance
to this feedthrough. Figure 16 details the high OFF Isolation
provided by this family. At 10MHz, OFF Isolation is about 50dB in
50Ωsystems, decreasing approximately 20dB per decade as
frequency increases. Higher load impedances decrease OFF
Isolation due to the voltage divider action of the switch OFF
Impedance and the load impedance.
Leakage Considerations
Reverse ESD protection diodes are internally connected between
each analog-signal pin and both V+ and V-. One of these diodes
conducts if any analog signal exceeds V+ or V-.
Virtually, all the analog leakage current comes from the ESD
diodes to V+ or V-. Although the ESD diodes on a given signal pin
are identical and therefore fairly well balanced, they are reverse
biased differently. Each is biased by either V+ or V- and the
analog signal. This means their leakages will vary as the signal
varies. The difference in the two diode leakages to the V+ and Vpins constitutes the analog-signal path leakage current. All
analog leakage current flows between each pin and one of the
supply terminals, not to the other switch terminal. This is why
both sides of a given switch can show leakage currents of the
same or opposite polarity. There is no connection between the
analog-signal paths and V+ or V-.
Logic-Level Thresholds
Due to the lack of a GND pin, the switching point of the digital
input is referenced predominantly to V+. The digital input is
CMOS compatible at ±5V supplies, and is TTL compatible for
±3.3V supplies. For other supply combinations refer to Figures 13
and 14.
The switching point has a very low temperature sensitivity, and
changes by only 100mV from +85°C to -40°C, regardless of
supply voltage.
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December 11, 2015
ISL43112, ISL43113
Typical Performance Curves
TA = +25°C, VIH = V+, VIL = 0V, unless otherwise specified.
150
50
I
= 1mA
45 COM
40
35
30
25
20
30
+85°C
25
+25°C
20
-40°C
15
10
30
25
+85°C
20
15
-40°C
10
VCOM = (V+) -1V
-40°C
ICOM = 1mA
125
75
50
+25°C
+85°C
25
0
rON ()
rON ()
100
-40°C
1
2
3
4
5
6
5
-5
VS (±V)
FIGURE 7. ON-RESISTANCE vs SUPPLY VOLTAGE
-3
+85°C
+25°C
-40°C
VS = ±3.3V
VS = ±5V
+25°C
-2
-1
0
1
VCOM (V)
2
3
4
5
FIGURE 8. ON-RESISTANCE vs SWITCH VOLTAGE
40
RL = 50Ω
VS = ±5V
30
-4
VS = ±1.5V
0
10
VS = ±1.5V to ±5.5V, SWITCH OFF
20
20
PSRR (dB)
Q (pC)
10
0
VS = ±1.5V
-10
VS = ±3.3V
-20
30
40
VS = ±5.5V, SWITCH ON
50
60
VS = ±1.5V, SWITCH ON
70
-30
80
-40
-5
-4
-3
-2
0
-1
1
2
3
4
5
0.3
1
10
VCOM (V)
FIGURE 9. CHARGE INJECTION vs SWITCH VOLTAGE
1000
FIGURE 10. PSRR vs FREQUENCY
80
120
VCOM = (V+) -1V
100
VCOM = (V+) -1V
VIN = 0 to V+
RL = 300Ω
+85°C
100
VIN = 0 to V+
RL = 300Ω
70
+85°C
60
tOFF (ns)
90
tON (ns)
100
FREQUENCY (MHz)
80
70
+25°C
60
+25°C
40
30
-40°C
50
50
-40°C
20
40
10
30
1
2
3
4
5
VS (±V)
FIGURE 11. TURN-ON TIME vs SUPPLY VOLTAGE
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9
6
1
2
3
4
5
6
VS (±V)
FIGURE 12. TURN-OFF TIME vs SUPPLY VOLTAGE
FN6029.3
December 11, 2015
ISL43112, ISL43113
Typical Performance Curves
TA = +25°C, VIH = V+, VIL = 0V, unless otherwise specified. (Continued)
4
3.5
-40°C to +85°C
VINH
3
V+ = 5V
3
2
1.5
VINH AND VINL (V)
VINH AND VINL (V)
2.5
VINH
1
0.5
VINH
V+ = 5V
VINL
2
V+ = 3.3V
VINH
V+ = 3.3V
VINL
1
0
-0.5
VINL
1
2
3
4
5
0
-5
6
VS (±V)
-2
-1
0
VS = ±1.5V to ±5.5V
20 RL = 50Ω
GAIN
-3
30
-6
40
PHASE
45
90
RL = 50Ω
VIN = 0.2VP-P to 2VP-P (VS = ±1.5V)
VIN = 0.2VP-P to 4VP-P (VS = ±3.3V)
VIN = 0.2VP-P to 5VP-P (VS = ±5.5V)
135
PHASE (°)
0
1
V- (V)
10
VS = ±1.5V to ±5.5V
0
-3
FIGURE 14. DIGITAL SWITCHING POINT vs NEGATIVE SUPPLY
VOLTAGE
180
10
100
OFF ISOLATION (dB)
NORMALIZED GAIN (dB)
FIGURE 13. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
-4
50
60
70
80
90
100
110
1k
600
10k
100k
FREQUENCY (MHz)
1M
10M
100M 500M
FREQUENCY (Hz)
FIGURE 15. FREQUENCY RESPONSE
FIGURE 16. OFF ISOLATION
25
Die Characteristics
20
SUBSTRATE POTENTIAL (POWERED UP):
ICC (A)
V-
-40°C
15
+25°C
TRANSISTOR COUNT:
ISL43112: 55
ISL43113: 55
10
+85°C
PROCESS:
5
Si Gate CMOS
0
1
2
3
4
5
6
VS (±V)
FIGURE 17. SUPPLY CURRENT vs SUPPLY VOLTAGE
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FN6029.3
December 11, 2015
ISL43112, ISL43113
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
December 11, 2015
FN6029.3
CHANGE
Applied new Intersil standards to throughout datasheet.
Updated the ordering information table by removing obsolete products, adding notes, and updating the part
marking.
Added the Revision History and About Intersil sections
Updated POD M8.15 to the latest revision the changes are as follows:
-Remove “u” symbol from drawing (overlaps the “a” on Side View).
-Updated to new POD format by removing table and moving dimensions onto drawing and adding land
pattern
-Changed in Typical Recommended Land Pattern the following:
2.41(0.095) to 2.20(0.087)
0.76 (0.030) to 0.60(0.023)
0.200 to 5.20(0.205)
-In Note 1 changed “1982” to “1994”
Updated POD P5.064 to the latest revision the changes are as follows:
-Converted to new format. Moved dimensions from table onto drawing and added land pattern)
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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11
FN6029.3
December 11, 2015
ISL43112, ISL43113
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
1.27 (0.050)
0.40 (0.016)
INDEX
6.20 (0.244)
5.80 (0.228)
AREA
0.50 (0.20)
x 45°
0.25 (0.01)
4.00 (0.157)
3.80 (0.150)
1
2
8°
0°
3
0.25 (0.010)
0.19 (0.008)
SIDE VIEW “B”
TOP VIEW
2.20 (0.087)
SEATING PLANE
5.00 (0.197)
4.80 (0.189)
1.75 (0.069)
1.35 (0.053)
1
8
2
7
0.60 (0.023)
1.27 (0.050)
3
6
4
5
-C-
1.27 (0.050)
0.51(0.020)
0.33(0.013)
SIDE VIEW “A
0.25(0.010)
0.10(0.004)
5.20(0.205)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
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12
FN6029.3
December 11, 2015
ISL43112, ISL43113
Package Outline Drawing
P5.064
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
Rev 3, 4/11
8°
0°
3.00 3
2.80
(1.90)
5
0.22
0.08 5
4
3.00
2.60
1.70
1.50
3
2
(0.95)
SEE DETAIL X
0.50
0.30
0.20 (0.008) M C
TOP VIEW
END VIEW
0.25
0.10
0.10 MIN
1.30
0.90
1.45 SEATING
0.90 PLANE
C
GAUGE PLANE
SEATING
PLANE
4
0.55
0.35
C
0.15
0.00
0.10 (0.004) C
(0.60)
SIDE VIEW
8°
0°
(0.25)
DETAIL "X"
5x (0.60)
5x (1.2)
5
4
(2.4)
NOTES:
1. Dimensioning and tolerance per ASME Y14.5M-1994.
3
2. Package conforms to EIAJ SC-74 and JEDEC MO178AA.
3. Package length and width are exclusive of mold flash, protrusions,
or gate burrs.
4. Footlength measured at reference to gauge plane.
5. Lead thickness applies to the flat section of the lead between
0.08mm and 0.15mm from the lead tip.
(2x 0.95)
6. Controlling dimension: MILLIMETER.
Dimensions in ( ) for reference only.
(1.90)
TYPICAL RECOMMENDED LAND PATTERN
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13
FN6029.3
December 11, 2015