Regenerating HSYNC from Corrupted SOG or CSYNC during VSYNC ® Technical Brief June 9, 2008 TB476.0 By Rudy Berneike and David Laing Introduction Recovering from HSYNC loss in LCD monitors caused by poor signal coding implementation is important to maintaining good video imagery on many LCD monitors. outputs with an external PLL to regenerate the missing HSYNC during the VSYNC time. This will result in a usable image on the monitor and will also support multi video modes. ISL59885 CSYNC OUTPUT Problem ISL59885 VSYNC OUTPUT It is not uncommon to experience corruption of HSYNC in a Sync On Green (SOG) signal during Vertical retrace. Low cost SOG sources use AND gates to remove the HSYNC or a XOR gate to invert the HSYNC during the VSYNC time. This implantation can cause the HSYNC to be missing or be out of sync with the source. Also, not all monitors have adequate phase lock loop recovery time to recover from such corrupted HSYNC signals. Such PLLs trying to recover the corrupted HSYNC will generate distortion at the top of the LCD displays or not sync at all, causing a loss of the entire image. The PLL in some CCD displays have such high loop gain and slow lock ability that they have a very hard time stabilizing in a short time with the replacement HSYNC pulses (even with low error) so they will show a very small amount of jitter at the top 10% to 20% of the screen. Without the replacement HSYNC pulses, the display is very badly corrupted and not useful. A much more complex design using a VCXO for the each video format would be needed. This technical brief presents a simple circuit that supports SOG for game and computer video signals plus regenerate any corrupted or an entire loss of HSYNC during Vertical retrace. Technical Brief 474 has a SOG design with true HSYNC timing if you have control of the SOG sources yet; if you do not have control of the SOG input, this circuit will regenerate HSYNC during VSYNC pulse time regardless of the state of the incoming HSYNC. PLL HSYNC OUTPUT W/ SOG INPUT FIGURE 1. ISL59885 HSYNC OUTPUT WITH SOG INPUT Using this sync separator, we can detect the HSYNC including a High Definition HSYNC as well as normal NTSC/PAL. The ISL59885 extracts video sync timing information from both standard and non-standard video. To make use of this sync extractor, we first need to terminate the input cable using a 75Ω resistor to ground. Next, we need to filter out the chroma by using a simple RC filter on the input. Since HD has a no chroma signal, we can simply switch out the second capacitor in parallel when HD is detected to change the filter characteristics for HD. The ISL59885 will now output HSYNC from the source and be referred to as ‘source HSYNC’ in this document. SOG VIDEO INPUT CHROMA FILTER P1 SYNC TIP REF 1.6V CLAMP ISL59885 0.1µF 100Ω 75Ω COMPOSITE VIDEO IN 100pF SLICE 1.67V 470pF GND C SYNC C SYNC CSET 0.1µF REF GEN SYNC TIP 70MV SLICE H SYNC 2H ELIMINATOR HD DETECTOR MMBT3904 10kΩ FIGURE 2. HSYNC DETECTION Basic Circuit This circuitry will be the source for all the HSYNC inputs to the monitor. First, we need to detect and phase lock to a correct HSYNC. Next, will be the detection of a corrupted or lost HSYNC and re-synchronize HSYNC to a non-corrupted HSYNC. Finally we will need to remove HSYNC from the incoming SOG and forward only the green video information to the monitor. We need to compare a reference HSYNC with the incoming source HSYNC to determine if the incoming HSYNC is valid. To do so, we need to generate the reference HSYNC. The most efficient design would center on using a Phase Lock Loop that would synchronize to the correct HSYNC from the source. Detecting HSYNC Phase Lock Intersil offers a simple solution to the HSYNC detector in the ISL59885. We selected the ISL59885 due to it’s multi video mode capability. With normal inputs, the ISL59885 will generate the VSYNC and CSYNC outputs. When we have missing input HSYNC, such as with SOG, the LCD monitor may not properly sync. We can use the HSYNC or the CSYNC We selected a simple low power, low cost digital PLL (the HC4046) to be the basic source for the HSYNC substitution. This PLL needs to have a wide lock range to support a wide range of video HSYNC rates from 16kHz to 64kHz (standard NTSC to HDTV). A wide locking range will cause the PLL to have a jitter that is too large to support a clean video HSYNC 1 Determine the Status of HSYNC CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Technical Brief 476 for much longer than the VSYNC interval. Using the PLL oscillator running at a high rate (say 32x that of the HSYNC), we can use a digital divider to help reduce the jitter by a factor of the divider, in this case by 32. This will keep the display PLL in lock with only a small error during the VSYNC time when there is no active video. It will also keep the monitor’s on-board PLL in a stable region. Another issue to consider is the external PLL cannot sync to a corrupted source HSYNC. We will need to open the PLL control loop and allow the PLL to coast for the non-active video time, while maintaining a proper HSYNC to the monitor. If we can NAND the Q and delay Q’, the NAND gate output can be used to open the PLL loop via a switch. The coast time should be about three valid HSYNC times (the number of HSYNC during the VSYNC sync window). At the same time, select PLL HSYNC pulses to drive the monitor. We selected the PLL output to be 32x the desired HSYNC. 32x HSYNC is within the normal operational range of the PLL and large enough to take advantage of the inherent reduction of the HSYNC jitter. By using a simple digital counter, the HC4040 (12 stage divider), we can divide down the PLL oscillator to the correct HSYNC frequency and also divide any jitter by the same 32x. We can delay Q’ to the NAND-Gate by using a series 10kΩ with a 0.047µF capacitor to ground. This RC ramp would delay Q’ from going low for about 300µs. The output of the NAND gate drives a simple analog switch. Delaying the Q’ transition will open the switch, ISL43110, and keep the PLL from trying to synchronize to the false HSYNC signal and let the PLL coast for the same 300µs. Before 300µs is over, the input source HSYNC would typically be valid again and the PLL will return to run in a synchronized mode. If the input source HSYNC is not valid within 300µs then the PLL will be forced to go back to the synchronized mode and start to re-sync lock on the next HSYNC. The PLL generated HSYNC will be referred to as the PLL HSYNC for the remainder of this document. Detection Circuit We now need to develop a detection circuit, which will compare the PLL HSYNC with the ISL59885 source HSYNC and indicate the status of the source HSYNC. We can use a simple digital approach to the problem by using a basic D-flip/flop with the source HSYNC driving the D input and the PLL HSYNC driving the clock. If the reference HSYNC is high at the start of the PLL HSYNC rising edge, the flip/flop Q output will go high on the rising edge of the PLL’s HSYNC, thus indicating a missing/corrupt source HSYNC pulse. A subtle issue, but none the less important, is the timing relationship of these signals. The ISL59885’s source HSYNC is delayed into the PLL to allow the detection circuitry to determination of the status of HSYNC and the selection circuit to select the correct HSYNC. The delays have to support the setup and hold times for the D-flip/flop to avoid a race condition. To bound the delays you have to remember that the longer the HSYNC delay, the more you have left side blanking of the screen. However, if you have too little delay, you have more chance you have of a race condition and false HSYNC detection. The ISL59885 was selected because it support multi video HSYNC rates. We can use the CSYNC output as it is a comparator output of both HSYNC and VSYNC. Now, all we need is a pulse former on the CSYNC output to extract the HSYNC portion of the input. Otherwise CSYNC output will stay low during the VSYNC, time and give a false HSYNC response. HC00 C SYNC 180pF PLL Hsync ~120ns Delay 470pF 1kΩ 10k 1kΩ 7 6 14 3 Q11 Q0 CP MR 10 11 120pF 39pF Q4 ~180ns Delay +5V SN74HC4040B 12-Stage Counter 220pF C SYNC Phase Comparator 1 Q VCO Phase Comparator 2 12 R1 100k 9 5 Q Phase Comparator 3 10kΩ SN74LVG2G74DCTR 10kΩ 1uF D HC00 13 0.047uF CD74HC4046AM Phase Lock Loop 10k ~60ns ISL43111 0.1uF 500Ω 10MΩ 2 FIGURE 3. PLL HSYNC TB476.0 June 9, 2008 Technical Brief 476 Delay Computation HSYNC Selector Circuitry The source HSYNC delay needs to be greater than the time it takes for the PLL to go into the coast mode and take into account other propagation delays as well. This would be the sum of the delays: At the time we place the PLL in coast mode, we need to select the PLL HSYNC output as the HSYNC input to the monitor. DETECTION CIRCUITRY • 74HC00 - Nand-Gate ~20ns C SYNC FROM EL59885 10kΩ HSYNC OUT 470pF 1kΩ HC 00 H C 00 HC00 180pF • 74HC74 - D flip/flop propagation delay ~45ns ~180ns DELAY 10kΩ HC 00 HC 00 H C 00 PLL CIRCUITRY • CD4040 and CD4046 – not an issue since the VCO phase comparator will force the input such that the output will be phase synchronous with the delayed HSYNC. 470pF S N 74H C 4040B 1 2 -S T A G E COUNTER Q11 11 One remaining timing issue is the detection flip/flop setup and hold time. In our design, we use the source HSYNC as the D input and the reference HSYNC as the clock. We need to delay the clock by the setup and hold time after applying the source HSYNC. Q4 10 The sum would be about 145ns, but we should add a safeguard to insure that we allow for any other parasitic delays. A 25% buffer would support our needs. Thus, the total delay of HSYNC is about 180ns delay. A simple series 1kΩ resistor and 180pF capacitor to ground into a logic inverter will give us about 180ns delay or about 5 to 6 pixel widths on the left side of the monitor. This is adequate time to allow for the propagation and to allow the detection circuitry to respond and select the proper HSYNC source but not impact the video image. This is the delayed source HSYNC signal. Q0 CP MR • ISL43110 – Switch turn-on/off time ~80ns +5V 220pF C SYNC FROM EL59885 10k ~60ns Q D HC 00 0 .0 4 7 µ F 10kΩ Q FIGURE 4. FALSE HSYNC DETECTOR We use the same signal which places the PLL in coast mode to select the counter output as the replacement HSYNC. The simple arrangement of NAND gates is used to make the selection and proper polarity for HSYNC. Since HSYNC has a defined pulse width, using a series capacitor to couple the HSYNC into the NAND gate will properly pulse shape the signal. We use a series 470pF capacitor and 10kΩ to ground to set the proper pulse width to about 3µs. Remember, connecting the delayed PLL HSYNC to the Comp IN of the HC4040 and the reference HSYNC into the SIG IN, will force the VCO of the PLL to be in phase at the input to the PLL. For correct timing, the PLL HSYNC needs to be delayed by only enough to compensate for the setup and hold of the D flip/flop. Delaying the PLL Q4 (PLL HSYNC) by 120ns and delaying the clock source HSYNC by 180ns, (180ns - 120ns = 60ns) will compensate for the setup and hold time for the D-flip/flop. Using an RC 100Ω serial and 120pF to ground will generate the necessary delay. Controlling the PLL loop when running in coast mode will require a heavily dampened feedback network supports the pre-open loop HSYNC. A loop filter of a series 10kΩ resistor and 1µF capacitor to ground with a 0.1µF capacitor in parallel will keep PLL at the proper frequency while in coast mode. The PLL was not designed to operate in coast mode so a 10mΩ resistor in parallel to the loop filter has to be added to ensure the PLL will relock with very low jitter after coast mode. We selected the loop VCO to be 32x that of the HSYNC to give the PLL a wide enough operational range to support HSYNC modes from 16kHz, 32kHz and 64kHz, and to reduce jitter. 3 TB476.0 June 9, 2008 Technical Brief 476 RED OUT Red BLUE OUT Blue COMPOSITE VIDEO IN CHROMA FILTER SOG VIDEO INPUT SYNC TIP REF 1.6V C SYNC CLAMP ISL59885 0.1uF 100Ω 75Ω ~180ns Delay COMPOSITE SYNC SLICE 1.67V 470pF GND V SYNC OUT C SYNC 100pF 470pF 1kΩ H SYNC SWITCH HC00 H SYNC REF GEN 0.1uF SYNC TIP 70mV SLICE H SYNC OUT HC00 CSET HC00 180pF HC00 HC00 10kΩ V SYNC ~3us PULSE WIDTH HC00 HD DETECTOR 10kΩ 470pF 10kΩ HI-DEF OUT 2N3904 H SYNC OUT DELAYED ~180ns LOW – MISSING OR CORRUPT H SYNC ~120ns DELAY FROM HC4040 Q4 120pF 39pF 6 7 14 V SYNC OUT ~120ns DELAY 1kΩ 3 PHASE COMPARATOR 2 11 13 Q11 VCO Q4 Q0 CP MR 10 11 PHASE COMPARATOR 1 SN74HC4040 12-STAGE COUNTER +5V R1 100k CD74HC4046 PHASE LOCK LOOP 5 C SYNC DETECTOR PHASE COMPARATOR 3 220pF 9 10kΩ ISL43110 ~60ns C SYNC 3 Hsync Times ~300us 10k Q D HC00 Q 0.1uF 1uF 10MΩ 0.047uF 500Ω 10kΩ SN74LVG2G74DCTR FIGURE 5. COMPLETE HSYNC CIRCUITRY 4 TB476.0 June 9, 2008 Technical Brief 476 Summary IS L 5 9 8 8 5 C S Y N C O U T P U T IS L 5 9 8 8 5 V S Y N C O U T P U T P L L H S Y N C O U T P U T W / S O G IN P U T P L L IN J E C T E D H S Y N C F IN A L H S Y N C O U T P U T FIGURE 6. CORRECTED HSYNC OUTPUT The replacement HSYNC is generated by the PLL HSYNC sync’ed to a delayed version of the source HSYNC. When the incoming SOG or HSYNC is lost or corrupted during vertical retrace, the PLL will run open loop and continue to supply a valid HSYNC. When a valid source HSYNC is detected, this external PLL will resynchronize to the source HSYNC and the detector will switch the HSYNC output back to the source HSYNC. By using a heavy damping in the feedback, the PLL drift will be greatly reduced if not eliminated for the short time duration needed. Thus, even a low cost monitor’s PLL will be able to track the re-sync to the source’s HSYNC with little to no impact on the active video region of the monitor. Additional Comments Concerning Digital Sync SOG Sync If, at the HSYNC switch input, you short the 470pF capacitor from Q4 to the NAND gate and open/removing the 10k resistor, the HSYNC will be a CSYNC output which can be used for SOG sync source with valid HSYNC in VSYNC time. The HSYNC pulse during the VSYNC will be on half the length of the HSYNC time and easily decoded with a sync separator. CSYNC (Digital SYNC Input) You might have a logic 5V level CSYNC with a bad HSYNC signal applied to the input of the sync separator. CSYNC could over-drive the input to the ISL59885. If so, it will become necessary to reduce the CSYNC input signal level. This can be done simply by using a 1kΩ resistor in series with the input 75Ω resistor to reduce load on the source and attenuate the input to the sync separator. this will result in a strong green tint on the screen image. This can be corrected by removing the CSYNC portion on the SOG so that only the green video signal goes to the LCD. This can be easily done with an ISL4089 as it will DC-restore the SOG video back porch near ground to within 10mV and clip off the CSYNC portion of the SOG signal to this 10mV offset. Thus, no unwanted green tint is visible (see Figure 7). 1kΩ VCC 1kΩ ISL4089 SOG VIDEO INPUT + 0.1µF P1 + C SYNC FROM EL59885 - 75Ω P2 GREEN VIDEO OUTPUT NC 200pF 10kΩ 1.25µs FIGURE 7. RECOVERING GREEN VIDEO FROM SOG We selected the ISL59885 as the sync separator to cover a wide variety of video sync rates. The problem is the ISL59885 outputs do not have a back porch. Therefore, we have to create the back porch such that the ISL4089 knows when to do the DC restore. This is easy to do by using a RC network (a series 200pF and 10kΩ to ground) to form a 1.25µs plus from the ISL59885 CSYNC output. The NAND gate inverts this pulse to form a 1.25µs pulse back porch for the ISL4089 DC restore. Remove CSYNC from SOG Failing to remove CSYNC from SOG will shift the Green level up by the CSYNC negative level. On an LCD RGB display, Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 5 TB476.0 June 9, 2008 Schematic and PCB Layout 6 Technical Brief 476 TB476.0 June 9, 2008 FIGURE 8. COMPLETE SCHEMATIC Schematic and PCB Layout (Continued) 7 Technical Brief 476 FIGURE 9. PCB LAYOUT TB476.0 June 9, 2008