DATASHEET

ISL43231
DUCT
TE PRO MENT PART
E
L
O
S
OB
PLACE
Data
Sheet
October 28, 2010
DED RE 53
N
E
M
M
RECO
ISL840
Low-Voltage, Single and Dual Supply,
Triple SPDT Analog Switch
Features
The Intersil ISL43231 device is a precision, bidirectional,
analog switch configured as a a triple single pole/double throw
(SPDT) switch, designed to operate from a single +2V to
+12V supply or from a 2V to 6V supply. The device has an
inhibit and inhibit bar pin to simultaneously open all signal
paths. The device also has a latch bar pin to lock in the last
switch address.
The ISL43231 is a committed triple SPDT, which is perfect for
use in 2-to-1 multiplexer applications. Table 1 summarizes the
performance of this part.
39
5V tON/tOFF
32ns/18ns
12V RON
32
12V tON/tOFF
23ns/15ns
5V RON
65
5V tON/tOFF
38ns/19ns
3.3V RON
125
3.3V tON/tOFF
70ns/32ns
Package
20 Ld 4x4 QFN
• RON Matching Between Channels, VS = 5V. . . . . . . . . <2
• Low Charge Injection, VS = 5V . . . . . . . . . . . . . . . . . 0.3pC
• Fast Switching Action (VS = +5V)
- tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38ns
- tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19ns
• Guaranteed Max Off-leakage . . . . . . . . . . . . . . . . . . . 2.5nA
• Break-Before-Make
• TTL, CMOS Compatible
Applications
• Battery Powered, Handheld, and Portable Equipment
• Communications Systems
- Radios
- Telecom Infrastructure
- ADSL, VDSL Modems
• Test Equipment
- Medical Ultrasound
- Magnetic Resonance Image
- CT and PET Scanners (MRI)
- ATE
- Electrocardiograph
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Audio and Video Signal Routing
• Application Note AN557 “Recommended Test Procedures
for Analog Switches”
• Application Note AN520 “CMOS Analog Multiplexers and
Switches; Specifications and Application Considerations.”
• Application Note AN1034 “Analog Switch and Multiplexer
Applications”
1
• ON-resistance (RON), VS = +3V . . . . . . . . . . . . . . . 135
• Pb-Free (RoHS Compliant)
TABLE 1. FEATURES AT A GLANCE
5V RON
• ON-resistance (RON) Max, VS = 4.5V . . . . . . . . . . . 50
• Dual Supply Operation . . . . . . . . . . . . . . . . . . . . . 2V to 6V
All digital inputs have 0.8V to 2.4V logic thresholds, ensuring
TTL/CMOS logic compatibility when using a single +3.3V or
+5V supply or dual 5V supplies.
TRIPLE SPDT
• Specified at 3.3V, 5V, 5V, and 12V Supplies for 10%
Tolerances
• Single Supply Operation. . . . . . . . . . . . . . . . . . . +2V to +12V
ON-resistance of 39 with a 5V supply and 125 with a
+3.3V supply. Each switch can handle rail-to-rail analog
signals. The off-leakage current is only 2.5nA at +85°C.
CONFIGURATION
FN6054.3
• Various Circuits
- +3V/+5V DACs and ADCs
- Sample and Hold Circuits
- Operational Amplifier Gain Switching Networks
- High Frequency Analog Switching
- High Speed Multiplexing
- Integrator Reset Circuits
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2003, 2004, 2006, 2010. All Rights Reserved
ISL43231
Pinout
NCB
NOB
N.C.
+V
COMB
ISL43231
(20 LD QFN)
TOP VIEW
20
19
18
17
16
2
14 NOC
NCA
3
13 NCC
EN
4
12 ADDC
EN
5
11 ADDB
7
8
9
Truth Table
10
ADDA
6
LE
COMA
N.C.
15 COMC
GND
1
-V
NOA
Pin Descriptions
ISL43231
LE
EN
EN
0
1
0
X
X
X
0
X
X
X
X
1
X
PIN
ADDC ADDB ADDA
FUNCTION
SWITCH ON
V+
Positive Power Supply Input
X
Last Switches
Selected
V-
Negative Power Supply Input. Connect to GND for
Single Supply Configurations.
X
X
NONE
GND
X
X
NONE
EN
Digital Control Input. Connect to GND for Normal
Operation. Connect to V+ to turn all switches off.
EN
Digital Control Input. Connect to V+ for Normal
Operation. Connect to GND to turn all switches off.
LE
Digital Control Input. Connect to +V for Normal
Operation. Connect to GND to latch the last switch state.
Ground Connection
1
1
0
X
X
0
NCA
1
1
0
X
X
1
NOA
1
1
0
X
0
X
NCB
1
1
0
X
1
X
NOB
1
1
0
0
X
X
NCC
COM
1
1
0
1
X
X
NOC
NO
Analog Switch Normally Open Pin
NC
Analog Switch Normally Closed Pin
NOTE: Logic “0” 0.8V. Logic “1” 2.4V, with V+ between 2.7V and
10V.
X = Don’t Care.
Analog Switch Common Pin
ADD
Address Input Pin
N.C.
No Internal Connection
Ordering Information
PART
NUMBER
(Note)
PART
MARKING
ISL43231IRZ* 43 231IRZ
TEMP.
RANGE
(°C)
PACKAGE
(Pb-free)
-40 to +85 20 Ld QFN
PKG.
DWG. #
L20.4x4
*Add “-T” suffix for tape and reel. Please refer to TB347 for details
on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN6054.3
October 28, 2010
ISL43231
Absolute Maximum Ratings
Thermal Information
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to15V
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to15V
V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15V to 0.3V
Input Voltages
LE, EN, EN, NO, NC, ADD (Note 1). . . ((V-) -0.3) to ((V+) + 0.3V)
Output Voltages
COM (Note 1) . . . . . . . . . . . . . . . . . . . . ((V-) -0.3) to ((V+) + 0.3V)
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . 30mA
Peak Current NO, NC, or COM
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . 100mA
ESD Rating
HBM ( Per Mil-STD-883, Method 3015.7) . . . . . . . . . . . . . >2.5kV
Thermal Resistance (Typical, Notes 2, 3)
JA (°C/W)
JC (°C/W)
20 Ld 4x4 QFN Package . . . . . . . . . . .
45
8
Maximum Junction Temperature (Plastic Package). . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . -65°C to 150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. Signals on NC, NO, COM, ADD, EN, EN, or LE exceeding V+ or V- are clamped by internal diodes. Limit forward diode current to maximum
current ratings.
2. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications - 5V Supply
PARAMETER
Test Conditions: VSUPPLY = 4.5V to 5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4),
Unless Otherwise Specified. Boldface limits apply over the operating temperature range,
-40°C to +85°C.
TEST CONDITIONS
TEMP
MIN
(°C) (Notes 5, 9)
TYP
MAX
(Notes 5, 9) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
Full
V-
-
V+
V
25
-
44
50

Full
-
-
80

25
-
1.3
4

Full
-
-
6

25
-
7.5
9

Full
-
-
12

25
-
0.002
-
nA
Full
-2.5
-
2.5
nA
25
-
0.002
-
nA
Full
-2.5
-
2.5
nA
25
-
0.002
-
nA
Full
-2.5
-
2.5
nA
Input Voltage High, VINH, VADDH
Full
2.4
-
-
V
Input Voltage Low, VINL, VADDL
Full
-
-
0.8
V
VS = 4.5V, ICOM = 2mA, VNO or VNC = 3V
(See Figure 7)
ON Resistance, RON
RON Matching Between Channels,
RON
VS = 4.5V, ICOM = 2mA, VNO or VNC = 3V (Note 6)
RON Flatness, RFLAT(ON)
VS = 4.5V, ICOM = 2mA, VNO or VNC = 3V, 0V
(Note 7)
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
VS = 5.5V, VCOM = 4.5V, VNO or VNC = +4.5V
(Note 7)
COM OFF Leakage Current,
ICOM(OFF)
VS = 5.5V, VCOM = 4.5V, VNO or VNC = +4.5V
(Note 7)
COM ON Leakage Current,
ICOM(ON)
VS = 5.5V, VCOM = VNO or VNC = 4.5V (Note 7)
DIGITAL INPUT CHARACTERISTICS
Input Current, IADDH, IADDL, IENH,
IENL
VS = 5.5V, VINH, VADD = 0V or V+
Full
-0.5
-
0.5
µA
Input Current, IENH, ILEH
VS = 5.5V, VINH, VADD = 0V or V+
Full
-1.5
-
1.5
µA
Input Current, IENL, ILEL
VS = 5.5V, VINH, VADD = 0V or V+
Full
-4
-
4
µA
3
FN6054.3
October 28, 2010
ISL43231
Electrical Specifications - 5V Supply
Test Conditions: VSUPPLY = 4.5V to 5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4),
Unless Otherwise Specified. Boldface limits apply over the operating temperature range,
-40°C to +85°C. (Continued)
PARAMETER
TEST CONDITIONS
TEMP
MIN
(°C) (Notes 5, 9)
TYP
MAX
(Notes 5, 9) UNITS
DYNAMIC CHARACTERISTICS
VS = 4.5V, VNO or VNC = 3V, RL = 300, CL = 35pF,
VIN = 0 to 3 (See Figure 1)
Enable Turn-ON Time, tON
VS = 4.5V, VNO or VNC = 3V, RL = 300, CL = 35pF,
VIN = 0 to 3 (See Figure 1)
Enable Turn-OFF Time, tOFF
Address Transition Time, tTRANS
VS = 4.5V, VNO or VNC = 3V, RL = 300, CL = 35pF,
VIN = 0 to 3 (See Figure 1)
25
-
35
-
ns
Full
-
45
-
ns
25
-
22
-
ns
Full
-
27
-
ns
25
-
43
-
ns
Full
-
53
-
ns
Break-Before-Make Time, tBBM
VS = 5.5V, VNO or VNC = 3V, RL = 300, CL = 35pF,
VIN = 0 to 3V (See Figure 3)
Full
-
7
-
ns
Latch Setup Time, tS
(See Figure 4)
25
-
25
-
ns
Full
-
35
-
ns
25
-
0
-
ns
Full
-
0
-
ns
25
-
15
-
ns
Full
-
25
-
ns
Latch Hold Time, tH
(See Figure 4)
Latch Pulse Width, tWPW
(See Figure 4)
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0 (See Figure 2)
25
-
0.3
-
pC
NO/NC OFF Capacitance, COFF
f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 8)
25
-
3
-
pF
COM OFF Capacitance, COFF
f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 8)
25
-
9
-
pF
COM ON Capacitance, CCOM(ON)
f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 8)
25
-
14
-
pF
OFF Isolation
RL = 50, CL = 15pF, f = 100kHz,
VNOx or VNCx = 1VRMS (See Figures 5, 7 and 20)
25
-
92
-
dB
25
-
<-110
-
dB
25
-
-105
-
dB
Full
2
-
6
V
Full
-7
-
7
µA
Full
-1
-
1
µA
Crosstalk (Note 8)
All Hostile Crosstalk (Note 8)
POWER SUPPLY CHARACTERISTICS
Power Supply Range
VS = 5.5V, VINH, VADD = 0V or V+, Switch On or Off
Positive Supply Current, I+
Negative Supply Current, INOTES:
4. VIN = Input logic voltage to configure the device in a given state.
5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
6. RON = RON (MAX) - RON (MIN).
7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
8. Between any two switches.
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
4
FN6054.3
October 28, 2010
ISL43231
Electrical Specifications +12V Supply
PARAMETER
Test Conditions: V+ = +10.8V to +13.2V, GND = 0V, VINH = 4V, VINL = 0.8V (Note 4),
Unless Otherwise Specified. Boldface limits apply over the operating temperature
range, -40°C to +85°C.
TEST CONDITIONS
TEMP
MIN
(°C) (Notes 5, 9)
TYP
MAX
(Notes 5, 9) UNITS
ANALOG SWITCH CHARACTERISTICS
Full
0
-
V+
V
25
-
37
45

Full
-
-
55

25
-
1.2
2

Full
-
-
2

25
-
5
7

Full
-
-
7

25
-
0.002
-
nA
Full
-2.5
-
2.5
nA
25
-
0.002
-
nA
Full
-2.5
-
2.5
nA
25
-
0.002
-
nA
Full
-2.5
-
2.5
nA
Input Voltage High, VINH, VADDH
Full
3.7
3.3
-
V
Input Voltage Low, VINL, VADDL
Full
-
2.7
0.8
V
Analog Signal Range, VANALOG
ON-resistance, RON
V+ = 10.8V, ICOM = 1.0mA, VNO or VNC = 9V
(See Figure 6)
RON Matching Between Channels,
RON
V+ = 10.8V, ICOM = 1.0mA, VNO or VNC = 9V (Note 6)
RON Flatness, RFLAT(ON)
V+ = 10.8V, ICOM = 1.0mA, VNO or VNC = 3V, 6V, 9V
(Note 7)
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 13.2V, VCOM = 1V, 12V, VNO or VNC = 12V, 1V
(Note 8)
COM OFF Leakage Current,
ICOM(OFF)
V+ = 13.2V, VCOM = 12V, 1V, VNO or VNC = 1V, 12V
(Note 8)
COM ON Leakage Current,
ICOM(ON)
V = 13.2V, VCOM = 1V, 12V, VNO or VNC = 1V, 12V, or
floating (Note 8)
DIGITAL INPUT CHARACTERISTICS
Input Current, IADDH, IADDL, IENH,
IENL
V+ = 13.2V, VINH, VADD = 0V or V+
Full
-0.5
-
0.5
µA
Input Current, IENH, ILEH
V+ = 13.2V, VINH, VADD = 0V or V+
Full
-1.5
-
1.5
µA
Input Current, IENL, ILEL
V+ = 13.2V, VINH, VADD = 0V or V+
Full
-4
-
4
µA
V+ = 10.8V, VNO or VNC = 10V, RL = 300, CL = 35pF,
VIN = 0 to 4 (See Figure 1)
25
-
24
-
ns
Full
-
29
-
ns
25
-
15
-
ns
Full
-
20
-
ns
25
-
27
-
ns
Full
-
32
-
ns
DYNAMIC CHARACTERISTICS
Enable Turn-ON Time, tON
V+ = 10.8V, VNO or VNC = 10V, RL = 300, CL = 35pF,
VIN = 0 to 4 (See Figure 1)
Enable Turn-OFF Time, tOFF
Address Transition Time, tTRANS
V+ = 10.8V, VNO or VNC = 10V, RL = 300, CL = 35pF,
VIN = 0 to 4 (See Figure 1)
Break-Before-Make Time Delay, tD
V+ = 13.2V, RL = 300, CL = 35pF, VNO or VNC = 10V,
VIN = 0 to 4 (See Figure 3)
Full
-
5
-
ns
Latch Setup Time, tS
(See Figure 4)
25
-
25
-
ns
Full
-
35
-
ns
25
-
0
-
ns
Full
-
0
-
ns
25
-
15
-
ns
Full
-
25
-
ns
25
-
2.7
-
pC
Latch Hold Time, tH
(See Figure 4)
Latch Pulse Width, tWPW
(See Figure 4)
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0 (See Figure 2)
5
FN6054.3
October 28, 2010
ISL43231
Electrical Specifications +12V Supply
PARAMETER
Test Conditions: V+ = +10.8V to +13.2V, GND = 0V, VINH = 4V, VINL = 0.8V (Note 4),
Unless Otherwise Specified. Boldface limits apply over the operating temperature
range, -40°C to +85°C. (Continued)
TEST CONDITIONS
OFF Isolation
RL = 50, CL = 15pF, f = 100kHz,
VNOx or VNCx= 1VRMS (See Figures 5, 7 and 20)
TEMP
MIN
(°C) (Notes 5, 9)
TYP
MAX
(Notes 5, 9) UNITS
25
-
92
-
dB
25
-
<-110
-
dB
All Hostile Crosstalk (Note 8)
25
-
-105
-
dB
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 8)
25
-
3
-
pF
COM OFF Capacitance,
CCOM(OFF)
f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 8)
25
-
9
-
pF
COM ON Capacitance, CCOM(ON)
f = 1MHz, VNO or VNC = VCOM = 0V (See Figure 8)
25
-
14
-
pF
Full
2
-
12
V
Full
-7
-
7
µA
Crosstalk (Note 8)
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current, I+
V+ = 13.2V, VINH, VADD = 0V or V+, all channels on or
off
Electrical Specifications 5V Supply
PARAMETER
Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4),
Unless Otherwise Specified. Boldface limits apply over the operating temperature range,
-40°C to +85°C.
TEST CONDITIONS
TEMP
MIN
(°C) (Notes 5, 9)
TYP
MAX
(Notes 5, 9) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
Full
0
-
V+
V
25
-
81
90

Full
-
-
120

25
-
2.2
4

Full
-
-
6

25
-
11.5
17

Full
-
-
24

25
-
0.002
-
nA
Full
-2.5
-
2.5
nA
25
-
0.002
-
nA
Full
-2.5
-
2.5
nA
25
-
0.002
-
nA
Full
-2.5
-
2.5
nA
Input Voltage High, VINH, VADDH
Full
2.4
-
-
V
Input Voltage Low, VINL, VADDL
Full
-
-
0.8
V
ON-resistance, RON
V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 3.5V
(See Figure 6)
RON Matching Between Channels,
RON
V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 3V (Note 6)
RON Flatness, RFLAT(ON)
V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 1V, 2V, 3V
(Note 7)
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 5.5V, VCOM = 1V, 4.5V, VNO or VNC = 4.5V, 1V
(Note 8)
COM OFF Leakage Current,
ICOM(OFF)
V+ = 5.5V, VCOM = 1V, 4.5V, VNO or VNC = 4.5V, 1V
(Note 8)
COM ON Leakage Current,
ICOM(ON)
V+ = 5.5V, VCOM = VNO or VNC = 4.5V (Note 8)
DIGITAL INPUT CHARACTERISTICS
Input Current, IADDH, IADDL, IENH,
IENL
V+ = 5.5V, VINH, VADD = 0V or V+
Full
-0.5
-
0.5
A
Input Current, IENH, ILEH
V+ = 5.5V, VINH, VADD = 0V or V+
Full
-1.5
-
1.5
A
Input Current, IENL, ILEL
V+ = 5.5V, VINH, VADD = 0V or V+
Full
-4
-
4
A
V+ = 4.5V, VNO or VNC = 3V, RL = 300, CL = 35pF,
VIN = 0 to 3V (See Figure 1)
25
-
43
-
ns
Full
-
53
-
ns
DYNAMIC CHARACTERISTICS
Enable Turn-ON Time, tON
6
FN6054.3
October 28, 2010
ISL43231
Electrical Specifications 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4),
Unless Otherwise Specified. Boldface limits apply over the operating temperature range,
-40°C to +85°C. (Continued)
PARAMETER
TEST CONDITIONS
Enable Turn-OFF Time, tOFF
V+ = 4.5V, VNO or VNC = 3V, RL = 300, CL = 35pF,
VIN = 0 to 3V (See Figure 1)
Address Transition Time, tTRANS
V+ = 4.5V, VNO or VNC = 3V, RL = 300, CL = 35pF,
VIN = 0 to 3V (See Figure 1)
TEMP
MIN
(°C) (Notes 5, 9)
TYP
MAX
(Notes 5, 9) UNITS
25
-
20
-
ns
Full
-
25
-
ns
25
-
51
-
ns
Full
-
56
-
ns
Break-Before-Make Time, tBBM
V+ = 5.5V, VNO or VNC = 3V, RL = 300, CL = 35pF,
VIN = 0 to 3V (See Figure 3)
Full
-
9
-
ns
Latch Setup Time, tS
(See Figure 4)
25
-
25
-
ns
Full
-
35
-
ns
25
-
0
-
ns
Full
-
0
-
ns
25
-
15
-
ns
Full
-
25
-
ns
Latch Hold Time, tH
(See Figure 4)
Latch Pulse Width, tWPW
(See Figure 4)
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0See Figure 2)
25
-
0.6
-
pC
OFF Isolation
RL = 50, CL = 15pF, f = 100kHz,
VNOx or VNCx= 1VRMS (See Figures 5, 7 and 20)
25
-
92
-
dB
25
-
<-110
-
dB
25
-
-105
-
dB
Full
2
-
12
V
Full
-7
-
7
A
Crosstalk (Note 8)
All Hostile Crosstalk (Note 8)
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current, I+
V+ = 5.5V, V- = 0V, VINH, VADD = 0V or V+,
Switch On or Off
Electrical Specifications 3.3V Supply
PARAMETER
Test Conditions: V+ = +3.0V to +3.6V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4),
Unless Otherwise Specified. Boldface limits apply over the operating temperature
range, -40°C to +85°C.
TEST CONDITIONS
TEMP
MIN
(°C) (Notes 5, 9)
TYP
MAX
(Notes 5, 9) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON Resistance, RON
V+ = 3.0V, ICOM = 1.0mA, VNO or VNC = 1.5V
(See Figure 6)
RON Matching Between Channels,
RON
V+ = 3.0V, ICOM = 1.0mA, VNO or VNC = 1.5V (Note 6)
RON Flatness, RFLAT(ON)
V+ = 3.0V, ICOM = 1.0mA, VNO or VNC = 0.5V, 1V, 2V
(Note 7)
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 3.6V, VCOM = 0V, 4.5V, VNO or VNC = 3V, 1V
(Note 8)
COM OFF Leakage Current,
ICOM(OFF)
V+ = 3.6V, VCOM = 0V, 4.5V, VNO or VNC = 3V, 1V
(Note 8)
COM ON Leakage Current,
ICOM(ON)
V+ = 3.6V, VCOM = VNO or VNC = 3V (Note 8)
7
Full
0
-
V+
V
25
-
135
-

Full
-
155
-

25
-
3.4
-

Full
-
5.4
-

25
-
34
-

Full
-
44
-

25
-
0.002
-
nA
Full
-2.5
-
2.5
nA
25
-
0.002
-
nA
Full
-2.5
-
2.5
nA
25
-
0.002
-
nA
Full
-2.5
-
2.5
nA
FN6054.3
October 28, 2010
ISL43231
Electrical Specifications 3.3V Supply
PARAMETER
Test Conditions: V+ = +3.0V to +3.6V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4),
Unless Otherwise Specified. Boldface limits apply over the operating temperature
range, -40°C to +85°C. (Continued)
TEST CONDITIONS
TEMP
MIN
(°C) (Notes 5, 9)
TYP
MAX
(Notes 5, 9) UNITS
DIGITAL INPUT CHARACTERISTICS
Input Voltage High, VINH, VADDH
Full
2.4
-
-
V
Input Voltage Low, VINL, VADDL
Full
-
-
0.8
V
Input Current, IADDH, IADDL, IENH,
IENL
V+ = 3.6V, VINH, VADD = 0V or V+
Full
-0.5
-
0.5
A
Input Current, IENH, ILEH
V+ = 3.6V, VINH, VADD = 0V or V+
Full
-1.5
-
1.5
A
Input Current, IENL, ILEL
V+ = 3.6V, VINH, VADD = 0V or V+
Full
-4
-
4
A
V+ = 3.0V, VNO or VNC = 1.5V, RL = 300, CL = 35pF,
VIN = 0 to 3V (See Figure 1)
25
-
82
-
ns
Full
-
102
-
ns
25
-
37
-
ns
Full
-
47
-
ns
25
-
96
-
ns
Full
-
121
-
ns
DYNAMIC CHARACTERISTICS
Enable Turn-ON Time, tON
V+ = 3.0V, VNO or VNC = 1.5V, RL = 300, CL = 35pF,
VIN = 0 to 3V (See Figure 1)
Enable Turn-OFF Time, tOFF
Address Transition Time, tTRANS
V+ = 3.0V, VNO or VNC = 1.5V, RL = 300, CL = 35pF,
VIN = 0 to 3V (See Figure 1)
Break-Before-Make Time, tBBM
V+ = 3.6V, VNO or VNC = 1.5V, RL = 300, CL = 35pF,
VIN = 0 to 3V (See Figure 3)
Full
-
13
-
ns
Latch Setup Time, tS
(See Figure 4)
25
-
50
-
ns
Full
-
60
-
ns
25
-
0
-
ns
Full
-
0
-
ns
25
-
30
-
ns
Full
-
40
-
ns
Latch Hold Time, tH
(See Figure 4)
Latch Pulse Width, tWPW
(See Figure 4)
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0See Figure 2)
25
-
0.3
-
pC
OFF Isolation
RL = 50, CL = 15pF, f = 100kHz,
VNOx or VNCx= 1VRMS (See Figures 5, 7 and 20)
25
-
92
-
dB
25
-
<-110
-
dB
25
-
-105
-
dB
Full
2
-
12
V
Full
-7
-
7
A
Crosstalk, Note 8
All Hostile Crosstalk, Note 8
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current, I+
V+ = 3.6V, V- = 0V, VINH, VADD = 0V or V+,
Switch On or Off
8
FN6054.3
October 28, 2010
ISL43231
Test Circuits and Waveforms
3V
LOGIC
INPUT
V+
tr < 20ns
tf < 20ns
50%
V-
C
C
C
0V
EN, LE
tON
VNCX
SWITCH
OUTPUT
90%
V+
VOUT
90%
EN
VOUT
COMX
NOX
ADDX
GND
tOFF
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for other switches. CL includes fixture and stray
capacitance.
RL
-----------------------------V OUT = V
(NO or NC) R + R
L
 ON 
FIGURE 1B. ENABLE tON / tOFF TEST CIRCUIT
FIGURE 1A. ENABLE tON / tOFF MEASUREMENT POINTS
3V
tr < 20ns
tf < 20ns
50%
CL
35pF
RL
300
LOGIC
INPUT
0V
LOGIC
INPUT
NCX
V+
C
V-
C
C
0V
tTRANS
NCX EN, LE
V+
V-
VOUT
VNCX
NOX
C
90%
ADDX
SWITCH
OUTPUT
VOUT
COMX
EN
GND
LOGIC
INPUT
10%
VNOX
CL
35pF
RL
300
0V
tTRANS
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for other switches. CL includes fixture and stray
capacitance.
RL
-----------------------------V OUT = V
(NO or NC) R + R
L
 ON 
FIGURE 1D. ADDRESS tTRANS TEST CIRCUIT
FIGURE 1C. ADDRESS tTRANS MEASUREMENT POINTS
FIGURE 1. SWITCHING TIMES
V+
V-
C
C
3V
LOGIC
INPUT
OFF
OFF
ON
RG
0V
VOUT
EN, LE
NOX or NCX
COMX
0
SWITCH
OUTPUT
VOUT
VOUT
ADDX
VG
GND
EN
LOGIC
INPUT
Q = VOUT x CL
FIGURE 2A. Q MEASUREMENT POINTS
CL
1nF
Repeat test for other switches.
FIGURE 2B. Q TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
9
FN6054.3
October 28, 2010
ISL43231
Test Circuits and Waveforms
(Continued)
V+
tr < 20ns
tf < 20ns
3V
LOGIC
INPUT
V-
C
C
C
0V
EN, LE
80%
0V
CL
35pF
RL
300
NCX, NOX
V+
SWITCH
OUTPUT
VOUT
VOUT
COMX
ADDX
LOGIC
INPUT
tBBM
GND
EN
Repeat test for other switches. CL includes fixture and stray
capacitance.
FIGURE 3A. tBBM MEASUREMENT POINTS
FIGURE 3B. tBBM TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
tr < 20ns
tf < 20ns
tMPW
LOGIC
INPUT
LE
V+
3V
50%
0V
50%
V-
C
C
50%
tH
tS
tH
LOGIC
INPUT
ADDX
C
3V
50%
50%
LOGIC
INPUT
EN
NCX
ADDX
NOX
LE
COMX
GND EN
V+
VOUT
RL
300
0V
tON, tOFF
VNCX
SWITCH
OUTPUT
0V
LOGIC
INPUT
CL
35pF
90%
VOUT
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for other switches. CL includes fixture and stray
capacitance.
RL
V OUT = V (NO or NC) -----------------------------R L + R  ON 
FIGURE 4B. LATCH tS, tH, tMPW TEST CIRCUIT
FIGURE 4A. LATCH tS, tH, tMPW MEASUREMENT POINTS
FIGURE 4. LATCH SETUP AND HOLD TIMES
V+
SIGNAL
GENERATOR
V-
C
V+
C
RON = V1/1mA
EN, LE
V-
C
C
EN, LE
NO or NC
NO or NC
VNX
0V or V+
ADDX
ANALYZER
COM
0V or V+
GND
EN
1mA
0V or V+
V1
ADDX
COM
GND
EN
RL
FIGURE 5. OFF ISOLATION TEST CIRCUIT
10
FIGURE 6. RON TEST CIRCUIT
FN6054.3
October 28, 2010
ISL43231
Test Circuits and Waveforms
V+
C
(Continued)
V-
EN, LE
SIGNAL
GENERATOR
NOA or NCA
0V or V+
V+
C
50
NO or NC
0V or V+
ADDX
COMB
C
EN, LE
COMA
ADDX
IMPEDANCE
ANALYZER
NOB or NCB
ANALYZER
V-
C
GND
N.C.
COM
GND
EN
EN
RL
FIGURE 7. CROSSTALK TEST CIRCUIT
Detailed Description
The ISL43231 analog switch offers a precise switching
capability from a bipolar 2V to 6V or a single 2V to 12V
supply with low ON-resistance (39) and high speed
operation (tON = 38ns, tOFF = 19ns) with dual 5V supplies.
It has an inhibit and inhibit bar pin to simultaneously open all
signal paths. It also has a latch bar pin to lock in the last
switch address.
The device is especially well suited for applications using
±5V supplies. With ±5V supplies, the performance (RON,
Leakage, Charge Injection, etc.) is best in class.
High frequency applications also benefit from the wide
bandwidth, and the very high off isolation and crosstalk
rejection.
Supply Sequencing And Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to V- (see
Figure 9). To prevent forward biasing these diodes, V+ and
V- must be applied before any input signals, and input signal
voltages must remain between V+ and V-. If these conditions
cannot be guaranteed, then one of the following two
protection methods should be employed.
FIGURE 8. CAPACITANCE TEST CIRCUIT
diodes can be added in series with the supply pins to provide
overvoltage protection for all pins (see Figure 9). These
additional diodes limit the analog signal from 1V below V+ to
1V above V-. The low leakage current performance is
unaffected by this approach, but the switch resistance may
increase, especially at low supply voltages.
OPTIONAL
PROTECTION
RESISTOR
FOR LOGIC
INPUTS
1k
OPTIONAL PROTECTION
DIODE
V+
LOGIC
VNO or NC
VCOM
VOPTIONAL PROTECTION
DIODE
FIGURE 9. INPUT OVERVOLTAGE PROTECTION
Power-Supply Considerations
Logic inputs can easily be protected by adding a 1k
resistor in series with the input (see Figure 9). The resistor
limits the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
The ISL43231 construction is typical of most CMOS analog
switches, in that they have three supply pins: V+, V-, and
GND. V+ and V- drive the internal CMOS switches and set
their analog voltage limits, so there are no connections
between the analog signal path and GND. Unlike switches
with a 13V maximum supply voltage, the ISL43231 15V
maximum supply voltage provides plenty of room for the
10% tolerance of 12V supplies (6V or 12V single supply),
as well as room for overshoot and noise spikes.
This method is not applicable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low RON switch, so two small signal
This switch device performs equally well when operated with
bipolar or single voltage supplies. The minimum
recommended supply voltage is 2V or 2V. It is important to
11
FN6054.3
October 28, 2010
ISL43231
note that the input signal range, switching times, and onresistance degrade at lower supply voltages. Refer to the
electrical specification tables and Typical Performance
Curves for details.
V+ and GND power the internal logic (thus setting the digital
switching point) and level shifters. The level shifters convert
the logic levels to switched V+ and V- signals to drive the
analog switch gate terminals.
Logic-Level Thresholds
V+ and GND power the internal logic stages, so V- has no
affect on logic thresholds. This switch family is TTL
compatible (0.8V and 2.4V) over a V+ supply range of 2.7V
to 10V. At 12V the VIH level is about 3.3V. This is still below
the CMOS guaranteed high output minimum level of 4V, but
noise margin is reduced. For best results with a 12V supply,
use a logic family that provides a VOH greater than 4V.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
High-Frequency Performance
In 50 systems, signal response is reasonably flat even past
100MHz (see Figures 18 and 19). Figures 18 and 19 also
illustrates that the frequency response is very consistent
over varying analog signal levels.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal feed
through from a switch’s input to its output. Off Isolation is the
resistance to this feed through, while Crosstalk indicates the
amount of feed through from one switch to another.
Figure 20 details the high Off Isolation and Crosstalk
rejection provided by this family. At 10MHz, Off Isolation is
about 55dB in 50 systems, decreasing approximately 20dB
per decade as frequency increases. Higher load
impedances decrease Off Isolation and Crosstalk rejection
due to the voltage divider action of the switch OFF
impedance and the load impedance.
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and V-. One
of these diodes conducts if any analog signal exceeds V+
or V-.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or V-. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or V- and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and V- pins constitutes the analog-signalpath leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and GND.
Typical Performance Curves TA = 25°C, Unless Otherwise Specified
70
VCOM = (V+) - 1V
ICOM = 1mA
V- = -5V
60
+85°C
40
+25°C
30
-40°C
20
400
RON ()
RON ()
50
V- = 0V
300
200
+85°C
+25°C
50
100
3
VS =2V
+85°C
+25°C
-40°C
VS =3V
+85°C
+25°C
-40°C
VS =5V
+85°C
+25°C
30
2
ICOM = 1mA
40
-40°C
0
120
110
100
90
80
70
60
50
90
80
70
60
50
40
30
60
4
5
6
7
V+ (V)
8
9
10
11
FIGURE 10. ON-RESISTANCE vs SUPPLY VOLTAGE
12
12
20
-40°C
-5
-4
-3
-2
-1
1
0
VCOM (V)
2
3
4
5
FIGURE 11. ON-RESISTANCE vs SWITCH VOLTAGE
FN6054.3
October 28, 2010
ISL43231
Typical Performance Curves TA = 25°C, Unless Otherwise Specified (Continued)
V+ = 12V
V- = 0V
55
175
150
+85°C
125
100
+25°C
75
160
140
120
100
80
60
100
90
80
70
60
50
40
60
ICOM = 1mA
-40°C
45
+85°C
+25°C
V+ = 3.3V
-40°C
V- = 0V
+85°C
40
35
+25°C
30
V+ = 5V
+85°C
V- = 0V
25
+25°C
-40°C
-40°C
1
0
3
2
20
5
4
0
2
4
6
VCOM (V)
+25°C
200
100
tOFF (ns)
-40°C
V- = 0V
200
+85°C
150
50
0
100
V- = 0V
80
+85°C
+25°C
40
20
-40°C
2
+85°C
-40°C
60
+25°C
100
+25°C
50
+85°C
0
250
+25°C
100
+25°C
3
4
VCOM = (V+) - 1V
V- = -5V
-40°C
150
-40°C
300
tON (ns)
12
FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE
VCOM = (V+) - 1V
V- = -5V
400
5
6
7
8
9
10
11
0
12
-40°C
2
3
4
5
6
8
7
10
9
11
12
V+ (V)
V+ (V)
FIGURE 14. ENABLE TURN - ON TIME vs SUPPLY VOLTAGE
300
FIGURE 15. ENABLE TURN - OFF TIME vs SUPPLY VOLTAGE
250
VCOM = (V+) - 1V
VCOM = (V+) - 1V
V- = 0V
250
200
tRANS (ns)
200
tRANS (ns)
10
200
500
150
100
150
100
+25°C
+25°C
+85°C
50
+85°C
50
-40°C
-40°C
0
8
VCOM (V)
FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE
0
ICOM = 1mA
50
V+ = 2.7V
V- = 0V
RON ()
RON ()
225
200
0
2
3
4
5
6
7
8
9
10
11
12
V+ (V)
FIGURE 16. ADDRESS TRANS TIME vs SINGLE SUPPLY
VOLTAGE
13
13
2
3
4
5
6
V (V)
FIGURE 17. ADDRESS TRANS TIME vs DUAL SUPPLY
VOLTAGE
FN6054.3
October 28, 2010
ISL43231
VIN = 0.2VP-P to 5VP-P
GAIN
0
-3
0
PHASE
45
90
135
180
VS = 3V
GAIN
0
-3
10
100
0
PHASE
45
90
135
180
RL = 50
RL = 50
1
VIN = 0.2VP-P to 4VP-P
3
1
600
10
600
FIGURE 19. FREQUENCY RESPONSE
FIGURE 18. FREQUENCY RESPONSE
-10
3
10
V+ = 3V to 12V or
-20 VS = 2V to 5V
RL = 50
-30
20
2
30
40
-50
50
-60
60
ISOLATION
-70
70
CROSSTALK
80
1
-90
90
-100
100
V+ = 3.3V
V- = 0V
V+ = 12V
V- = 0V
0
Q (pC)
-40
OFF ISOLATION (dB)
CROSSTALK (dB)
100
FREQUENCY (MHz)
FREQUENCY (MHz)
-80
PHASE (DEGREES)
NORMALIZED GAIN (dB)
VS = 5V
3
PHASE (DEGREES)
NORMALIZED GAIN (dB)
Typical Performance Curves TA = 25°C, Unless Otherwise Specified (Continued)
V+ = 5V
V- = 0V
-1
VS =5V
-2
-3
ALL HOSTILE CROSSTALK
-110
1k
10k
100k
1M
10M
110
100M 500M
FREQUENCY (Hz)
FIGURE 20. CROSSTALK AND OFF ISOLATION
-4
-5.0
-2.5
0
2.5
5.0
7.5
10.0
12
VCOM (V)
FIGURE 21. CHARGE INJECTION vs SWITCH VOLTAGE
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
VTRANSISTOR COUNT:
193
PROCESS:
Si Gate CMOS
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
14
FN6054.3
October 28, 2010
ISL43231
Package Outline Drawing
L20.4x4
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 3, 11/06
4X
4.00
2.0
16X 0.50
A
B
16
6
PIN #1 INDEX AREA
20
6
PIN 1
INDEX AREA
1
15
4.00
2 . 10 ± 0 . 15
11
5
0.15
(4X)
6
10
0.10 M C A B
4 0.25 +0.05 / -0.07
TOP VIEW
20X 0.6 +0.15 / -0.25
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 ± 0 . 1
C
BASE PLANE
( 3. 6 TYP )
(
SEATING PLANE
0.08 C
( 20X 0 . 5 )
2. 10 )
SIDE VIEW
( 20X 0 . 25 )
C
0 . 2 REF
5
0 . 00 MIN.
0 . 05 MAX.
( 20X 0 . 8)
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
15
FN6054.3
October 28, 2010