ISL84051, ISL84052, ISL84053 ® Data Sheet November 2003 FN6047.3 Low-Voltage, Single and Dual Supply, 8 to 1 Multiplexer, Dual 4 to 1 Multiplexer and a Triple SPDT Analog Switches Features The Intersil ISL84051, ISL84052, ISL84053 devices are precision, bidirectional, analog switches configured as a 8 channel multiplexer/demultiplexer (ISL84051), a dual differential 4 channel multiplexer/demultiplexer (ISL84052) and a triple single pole/double throw (SPDT) switch (ISL84053) designed to operate from a single +2V to +12V supply or from a ±2V to ±6V supply. All devices have an inhibit pin to simultaneously open all signal paths. • Pin Compatible with MAX4581, MAX4582, MAX4583 and with Industry Standard 74HC4051, 74HC4052 and 74HC4053 ON resistance is 60Ω with a ±5V supply and 125Ω with a single +5V supply. Each switch can handle rail to rail analog signals. The off-leakage current is only 0.1nA at +25oC or 5nA at +85oC with a ±5V supply. All digital inputs have 0.8V to 2.4V logic thresholds, ensuring TTL/CMOS logic compatibility when using a single +3.3V and +5V supply or dual ±5V supplies. The ISL84051 is a 8 to 1 multiplexer device. The ISL84052 is a dual 4 to 1 multiplexer device. The ISL84053 is a committed triple SPDT, which is perfect for use in 2-to-1 multiplexer applications. • Drop-in Replacements for MAX4051/A, MAX4052/A and MAX4053/A • ON Resistance (RON) Max, VS = ±5V . . . . . . . . . . . 100Ω • ON Resistance (RON) Max, VS = +3V . . . . . . . . . . . 525Ω • RON Matching Between Channels . . . . . . . . . . . . . . . . . <6Ω • Low Charge Injection . . . . . . . . . . . . . . . . . . . . . 10pC (Max) • Single Supply Operation. . . . . . . . . . . . . . . . . . . +2V to +12V • Dual Supply Operation . . . . . . . . . . . . . . . . . . . . . . ±2V to ±6 • Fast Switching Action (VS = +5V) - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60ns • Guaranteed Max Off-leakage @ VS = ±5V. . . . . . . . . . 5nA • Guaranteed Break-Before-Make • TTL, CMOS Compatible Applications Table 1 summarizes the performance of this family. • Portable Equipment TABLE 1. FEATURES AT A GLANCE ISL84051 ISL84052 ISL84053 8:1 Mux DUAL 4:1 Mux TRIPLE SPDT 60Ω 60Ω 60Ω 50ns/40ns 50ns/40ns 50ns/40ns 125Ω 125Ω 125Ω 90ns/60ns 90ns/60ns 90ns/60ns 250Ω 250Ω 250Ω 3V tON/tOFF 180ns/100ns 180ns/100ns 180ns/100ns Packages 16 Ld SOIC, 16 Ld SSOP CONFIGURATION ±5V RON ±5V tON/tOFF 5V RON 5V tON/tOFF 3V RON • Test Equipment - Medical Ultrasound - Magnetic Resonance Image - CT and PET Scanners (MRI) - ATE - Electrocardiograph • Audio and Video Signal Routing Related Literature • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” • Application Note AN557 “Recommended Test Procedures for Analog Switches” 1 • Communications Systems - Radios - Telecom Infrastructure - ADSL, VDSL Modems • Various Circuits - +3V/+5V DACs and ADCs - Sample and Hold Circuits - Operational Amplifier Gain Switching Networks - High Frequency Analog Switching - High Speed Multiplexing - Integrator Reset Circuits CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL84051, ISL84052, ISL84053 Pinouts ISL84051 (SOIC, SSOP) TOP VIEW NO1 1 16 V+ ISL84052 (SOIC, SSOP) TOP VIEW NO0B 1 16 V+ NO3 2 15 NO2 NO1B 2 15 NO1A COM 3 14 NO4 COMB 3 14 NO2A NO7 4 13 NO0 NO3B 4 13 COMA NO5 5 12 NO6 NO2B 5 12 NO0A 11 NO3A 11 ADDC INH 6 V- 7 10 ADDB V- 7 GND 8 9 ADDA GND 8 INH 6 LOGIC LOGIC 10 ADDB 9 ADDA ISL84053 (SOIC, SSOP) TOP VIEW NOB 1 16 V+ NCB 2 15 COMB NOA 3 14 COMC COMA 4 13 NOC NCA 5 12 NCC INH 6 11 ADDC V- 7 10 ADDB GND 8 9 ADDA NOTE: 1. Switches Shown for Logic “0” Inputs. Pin Description Ordering Information PART NO. PIN TEMP. RANGE (oC) PACKAGE PKG. DWG. # FUNCTION V+ Positive Power Supply Input V- Negative Power Supply Input. Connect to GND for Single Supply Configurations. ISL84051IB -40 to 85 16 Ld SOIC M16.15 ISL84051IA -40 to 85 16 Ld SSOP M16.15A ISL84052IB -40 to 85 16 Ld SOIC M16.15 GND Ground Connection ISL84052IA -40 to 85 16 Ld SSOP M16.15A INH ISL84053IB -40 to 85 16 Ld SOIC M16.15 Digital Control Input. Connect to GND for Normal Operation. Connect to V+ to turn all switches off. ISL84053IA -40 to 85 16 Ld SSOP M16.15A NOTE: Most surface mount devices are available on tape and reel; add “-T” to suffix. COM NO Analog Switch Normally Open Pin NC Analog Switch Normally Closed Pin ADD 2 Analog Switch Common Pin Address Input Pin ISL84051, ISL84052, ISL84053 Truth Tables ISL84053 ISL84051 ADDC ADDB ADDA SWITCH ON ADDC ADDB ADDA SWITCH ON INH INH 1 X X X None 1 X X X None 0 X X 0 NCA 0 0 0 0 NO0 0 X X 1 NOA 0 0 0 1 NO1 0 X 0 X NCB 0 0 1 0 NO2 0 X 1 X NOB 0 0 1 1 NO3 0 0 X X NCC 0 1 0 0 NO4 0 1 X X NOC 0 1 0 1 NO5 0 1 1 0 NO6 0 1 1 1 NO7 ISL84052 INH ADDB ADDA SWITCH ON 1 X X None 0 0 0 NO0 0 0 1 NO1 0 1 0 NO2 0 1 1 NO3 3 NOTE: Logic “0” ≤0.8V. Logic “1” ≥2.4V, with V+ between 2.7V and 10V. X = Don’t Care. ISL84051, ISL84052, ISL84053 Absolute Maximum Ratings Thermal Information V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V V- to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15 to 0.3V Input Voltages INH, NO, NC, ADD (Note 2) . . . . . . . . . ((V-)-0.3) to ((V+) + 0.3V) Output Voltages COM (Note 2) . . . . . . . . . . . . . . . . . . . . ((V-)-0.3) to ((V+) + 0.3V) Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . ±30mA Peak Current NO, NC, or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . ±100mA ESD Rating HBM (Per MIL-STD-883, Method 3015.7) . . . . . . . . . . . . . . >2kV Thermal Resistance (Typical, Note 3) θJA (oC/W) 16 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . 115 16 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . . 160 Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC Maximum Storage Temperature Range. . . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (Lead Tips Only) Operating Conditions Temperature Range ISL8405XIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 2. Signals on NC, NO, COM, ADD, or INH exceeding V+ or V- are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications: ±5V Supply Test Conditions: VSUPPLY = ±4.5V to ±5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified TEMP (oC) (NOTE 5) MIN TYP Full V- - V+ V 25 - 60 100 Ω Full - - 125 Ω 25 - - 6 Ω Full - - 12 Ω 25 - - 10 Ω Full - - 15 Ω 25 -0.1 0.002 0.1 nA Full -5 - 5 nA 25 -0.1 0.002 0.1 nA Full -5 - 5 nA 25 -0.1 0.002 0.1 nA Full -2.5 - 2.5 nA 25 -0.1 0.002 0.1 nA Full -5 - 5 nA 25 -0.1 0.002 0.1 nA Full -2.5 - 2.5 nA Input Voltage High, VINH, VADDH Full 2.4 - - V Input Voltage Low, VINL, VADDL Full - - 0.8 V Full -1 0.03 1 µA PARAMETER TEST CONDITIONS (NOTE 5) MAX UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG VS = ±5V, ICOM = 1mA, VNO or VNC = ±3V, (See Figure 5) ON Resistance, RON RON Matching Between Channels, ∆RON VS = ±5V, ICOM = 1mA, VNO or VNC = ±3V, (Note 6) RON Flatness, RFLAT(ON) VS = ±5V, ICOM = 1mA, VNO or VNC = ±3V, 0V, (Note 7) NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) VS = ±5.5V, VCOM = ±4.5V, VNO or VNC = +4.5V, (Note 8) COM OFF Leakage Current, ICOM(OFF), (ISL84051) VS = ±5.5V, VCOM = ±4.5V, VNO or VNC = +4.5V, (Note 8) COM OFF Leakage Current, ICOM(OFF), (ISL84052, ISL84053) VS = ±5.5V, VCOM = ±4.5V, VNO or VNC = +4.5V, (Note 8) COM ON Leakage Current, ICOM(ON), (ISL84051) VS = ±5.5V, VCOM = VNO or VNC = ±4.5V, (Note 8) COM ON Leakage Current, ICOM(ON), (ISL84052, ISL84053) VS = ±5.5V, VCOM = VNO or VNC = ±4.5V, (Note 8) DIGITAL INPUT CHARACTERISTICS VS = ±5.5V, VINH, VADD = 0V or V+ Input Current, IINH, IINL, IADDH, IADDL 4 ISL84051, ISL84052, ISL84053 Electrical Specifications: ±5V Supply PARAMETER Test Conditions: VSUPPLY = ±4.5V to ±5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified (Continued) TEST CONDITIONS TEMP (oC) (NOTE 5) MIN TYP 25 - 50 175 ns Full - - 225 ns 25 - 40 150 ns Full - - 200 ns (NOTE 5) MAX UNITS DYNAMIC CHARACTERISTICS VS = ±4.5V, VNO or VNC = ±3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3, (See Figure 1) Inhibit Turn-ON Time, tON VS = ±4.5V, VNO or VNC = ±3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3, (See Figure 1) Inhibit Turn-OFF Time, tOFF Address Transition Time, tTRANS VS = ±4.5V, VNO or VNC = ±3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3, (See Figure 1) 25 - 75 250 ns Break-Before-Make Time, tBBM VS = ±5.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, (See Figure 3) 25 2 10 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2) 25 - 2 10 pC NO/NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7) 25 - 3 - pF COM OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7) ISL84051 25 - 21 - pF ISL84052 25 - 12 - pF ISL84053 25 - 9 - pF ISL84051 25 - 26 - pF ISL84052 25 - 18 - pF ISL84053 25 - 14 - pF 25 - <90 - dB 25 - <-90 - dB Full ±2 - ±6 V 25 -1 0.1 1 µA Full -10 - 10 µA 25 -1 0.1 1 µA Full -10 - 10 µA COM ON Capacitance, CCOM(ON) OFF Isolation f = 1MHz, VNO or VNC = VCOM = 0V, (See Figure 7) RL = 50Ω, CL = 15pF, f = 100kHz, VNO or VNC = 1VRMS, (See Figures 4 and 6) Crosstalk, (Note 9) (ISL84052, ISL84053 only) POWER SUPPLY CHARACTERISTICS Power Supply Range VS = ±5.5V, VINH, VADD = 0V or V+, Switch On or Off Positive Supply Current, I+ Negative Supply Current, I- NOTES: 4. VIN = Input voltage to perform proper function. 5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. ∆RON = RON (MAX) - RON (MIN). 7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 8. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at 25oC. 9. Between any two switches. 5 ISL84051, ISL84052, ISL84053 Electrical Specifications: 5V Supply Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified TEMP (oC) MIN (NOTE 5) TYP Full 0 - V+ V 25 - 125 225 Ω Full - - 280 Ω 25 -1 0.002 1 nA Full -10 - 10 nA 25 -1 0.002 1 nA Full -10 - 10 nA 25 -1 0.002 1 nA Full -5 - 5 nA 25 -1 0.002 1 nA Full -10 - 10 nA Input Voltage High, VINH, VADDH Full 2.4 - - V Input Voltage Low, VINL, VADDL Full - - 0.8 V V+ = 5.5V, VINH, VADD = 0V or V+ Full -1 0.03 1 µA V+ = 4.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, (See Figure 1) 25 - 90 200 ns Full - - 275 ns 25 - 60 125 ns Full - - 175 ns PARAMETER TEST CONDITIONS MAX (NOTE 5) UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON V+ = 5V, ICOM = 1.0mA, VNO or VNC = 3.5V, (See Figure 5) NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 5.5V, VCOM = 0V, 4.5V, VNO or VNC = 4.5V, 0V, (Note 8) COM OFF Leakage Current, ICOM(OFF), (ISL84051) V+ = 5.5V, VCOM = 0V, 4.5V, VNO or VNC = 4.5V, 0V, (Note 8) COM OFF Leakage Current, ICOM(OFF), (ISL84052, ISL84053) V+ = 5.5V, VCOM = 0V, 4.5V, VNO or VNC = 4.5V, 0V, (Note 8) COM ON Leakage Current, ICOM(ON) V+ = 5.5V, VCOM = VNO or VNC = 4.5V, (Note 8) DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL, IADDH, IADDL DYNAMIC CHARACTERISTICS Inhibit Turn-ON Time, tON V+ = 4.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, (See Figure 1) Inhibit Turn-OFF Time, tOFF Break-Before-Make Time, tBBM V+ = 5.5V, VNO or VNC = 3V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, (See Figure 3) 25 - 30 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2) 25 - 2 10 pC OFF Isolation RL = 50Ω, CL = 15pF, f = 100kHz, VNO or VNC = 1VRMS, (See Figures 4 and 6) 25 - <90 - dB 25 - <-90 - dB Full 2 - 12 V 25 -1 - 1 µA Full -10 - 10 µA Crosstalk, (Note 9) (ISL84052, ISL840533 only) POWER SUPPLY CHARACTERISTICS Power Supply Range V+ = 5.5V, V- = 0V, VINH, VADD = 0V or V+, Switch On or Off Positive Supply Current, I+ 6 ISL84051, ISL84052, ISL84053 Electrical Specifications: 3.3V Supply Test Conditions: V+ = +3.0V to +3.6V, V- = GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 4), Unless Otherwise Specified TEMP (oC) MIN (NOTE 5) TYP Full 0 - V+ V 25 - 250 525 Ω Full - - 700 Ω 25 -1 0.002 1 nA Full -10 - 10 nA 25 -1 0.002 1 nA Full -10 - 10 nA 25 -1 0.002 1 nA Full -5 - 5 nA 25 -1 0.002 1 nA Full -10 - 10 nA Input Voltage High, VINH, VADDH Full 2.4 - - V Input Voltage Low, VINL, VADDL Full - - 0.8 V V+ = 3.6V, VINH, VADD = 0V or V+ Full -1 0.03 1 µA V+ = 3V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, (See Figure 1) 25 - 180 600 ns Full - - 700 ns 25 - 100 300 ns Full - - 400 ns PARAMETER TEST CONDITIONS MAX (NOTE 5) UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON V+ = 3V, ICOM = 1.0mA, VNO or VNC = 1.5V NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 3.6V, VCOM = 0V, 3V, VNO or VNC = 3V, 0V, (Note 8) COM OFF Leakage Current, ICOM(OFF), (ISL84051) V+ = 3.6V, VCOM = 0V, 3V, VNO or VNC = 3V, 0V, (Note 8) COM OFF Leakage Current, ICOM(OFF), (ISL84052, ISL84053) V+ = 3.6V, VCOM = 0V, 3V, VNO or VNC = 3V, 0V, (Note 8) COM ON Leakage Current, ICOM(ON) V+ = 3.6V, VCOM = VNO or VNC = 3V, (Note 8) DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL, IADDH, IADDL DYNAMIC CHARACTERISTICS Inhibit Turn-ON Time, tON V+ = 3V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, (See Figure 1) Inhibit Turn-OFF Time, tOFF Break-Before-Make Time, tBBM V+ = 3.6V, VNO or VNC = 1.5V, RL = 300Ω, CL = 35pF, VIN = 0 to 3V, (See Figure 3) 25 - 90 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2) 25 - 1 10 pC OFF Isolation RL = 50Ω, CL = 15pF, f = 100kHz, VNO or VNC = 1VRMS, (See Figures 4 and 6) 25 - <90 - dB 25 - <-90 - dB Full 2 - 12 V 25 -1 - 1 µA Full -10 - 10 µA Crosstalk, (Note 9) (ISL84052, ISL84053 only) POWER SUPPLY CHARACTERISTICS Power Supply Range V+ = 3.6V, V- = 0V, VINH, VADD = 0V or V+, Switch On or Off Positive Supply Current, I+ 7 ISL84051, ISL84052, ISL84053 Test Circuits and Waveforms C V+ V+ V- C NO0 C ISL84051 NO1-NO7 VOUT COM INH GND ADDA-C LOGIC INPUT C 3V LOGIC INPUT V+ V- C RL 300Ω CL 35pF C tr < 20ns tf < 20ns 50% V+ NO0 ISL84052 0V NO1-NO3 tON VOUT COM INH 90% SWITCH OUTPUT VOUT 90% GND ADDA-B LOGIC INPUT RL 300Ω CL 35pF 0V tOFF Logic input waveform is inverted for switches that have the opposite logic sense. V+ C V+ NCX NOX C V- C ISL84053 COMX VOUT INH GND ADDX LOGIC INPUT RL 300Ω Repeat test for other switches. CL includes fixture and stray capacitance. RL V OUT = V (NO or NC) -----------------------------R L + R ( ON ) FIGURE 1A. INHIBIT tON /tOFF MEASUREMENT POINTS 8 FIGURE 1B. INHIBIT tON /tOFF TEST CIRCUIT CL 35pF ISL84051, ISL84052, ISL84053 Test Circuits and Waveforms (Continued) C V+ V- V+ V- C NO0 ISL84051 NO7 C C VOUT COM NO1-NO6 ADDA-C GND INH RL 300Ω LOGIC INPUT C 3V LOGIC INPUT 50% V+ tTRANS V- VOUT NO0 C ISL84052 NO3 C SWITCH OUTPUT V- C tr < 20ns tf < 20ns 0V VNOX V+ CL 35pF ADDA-B GND 90% VOUT COM NO1-NO2 INH RL 300Ω LOGIC INPUT 0V CL 35pF 10% VNOX V+ C tTRANS Logic input waveform is inverted for switches that have the opposite logic sense. V+ V- NCX V- C ISL84053 NOX COMX C ADDX LOGIC INPUT C GND VOUT INH RL 300Ω Repeat test for other switches. CL includes fixture and stray capacitance. RL -----------------------------V OUT = V (NO or NC) R + R L ( ON ) FIGURE 1C. ADDRESS tTRANS MEASUREMENT POINTS FIGURE 1D. ADDRESS tTRANS TEST CIRCUIT FIGURE 1. SWITCHING TIMES (Continued) 9 CL 35pF ISL84051, ISL84052, ISL84053 Test Circuits and Waveforms (Continued) V+ V- C C 3V VOUT RG OFF OFF LOGIC INPUT ON COM NO or NC 0V 0Ω ADDX SWITCH OUTPUT VOUT VG ∆VOUT GND INH LOGIC INPUT CL 1nF Q = ∆VOUT x CL Repeat test for other switches. FIGURE 2B. Q TEST CIRCUIT FIGURE 2A. Q MEASUREMENT POINTS FIGURE 2. CHARGE INJECTION V+ C V- C VOUT NO0-NO7 V+ C COM RL 300Ω ADDA-C CL 35pF ISL84051 LOGIC INPUT GND tr < 20ns tf < 20ns 3V V+ C LOGIC INPUT INH V- C C 0V COM RL 300Ω ADDA-B 80% SWITCH OUTPUT VOUT VOUT NO0-NO3 V+ CL 35pF ISL84052 LOGIC INPUT 0V tBBM GND V+ C V- C NCX C VOUT NOX V+ INH COMX ISL84053 RL 300Ω ADDX GND LOGIC INPUT INH Repeat test for other switches. CL includes fixture and stray capacitance. FIGURE 3A. tBBM MEASUREMENT POINTS FIGURE 3B. tBBM TEST CIRCUIT FIGURE 3. BREAK-BEFORE-MAKE TIME 10 CL 35pF ISL84051, ISL84052, ISL84053 Test Circuits and Waveforms V+ (Continued) V- C V+ V- C C C RON = V1/1mA SIGNAL GENERATOR NO or NC NO or NC VNX 1mA 0V or V+ ADDX 0V or V+ ANALYZER COM ADDX COM INH GND 0V or V+ V1 GND INH RL FIGURE 5. RON TEST CIRCUIT FIGURE 4. OFF ISOLATION TEST CIRCUIT V+ SIGNAL GENERATOR V- C V+ C 50Ω NOA or NCA V- C NO or NC COMA ISL84052/3 0V or V+ ADDX NOB or NCB COMB ADDX IMPEDANCE ANALYZER 0V or V+ ANALYZER GND C N.C. COM GND INH INH RL FIGURE 6. CROSSTALK TEST CIRCUIT 11 FIGURE 7. CAPACITANCE TEST CIRCUIT ISL84051, ISL84052, ISL84053 Detailed Description Power-Supply Considerations The ISL84051, ISL84052, ISL84053 analog switches offer precise switching capability from a bipolar ±2V to ±6V or a single 2V to 12V supply with low on-resistance (60Ω) and high speed operation (tON = 50ns, tOFF = 40ns). The devices are especially well suited to portable battery powered equipment thanks to the low operating supply voltage (2V), low power consumption (3µW), low leakage currents (5nA max). High frequency applications also benefit from the wide bandwidth, and the very high off isolation and crosstalk rejection. The ISL8405X construction is typical of most CMOS analog switches, in that they have three supply pins: V+, V-, and GND. V+ and V- drive the internal CMOS switches and set their analog voltage limits, so there are no connections between the analog signal path and GND. Unlike switches with a 13V maximum supply voltage, the ISL8405X 15V maximum supply voltage provides plenty of room for the 10% tolerance of 12V supplies (±6V or 12V single supply), as well as room for overshoot and noise spikes. Supply Sequencing And Overvoltage Protection With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to V- (see Figure 8). To prevent forward biasing these diodes, V+ and V- must be applied before any input signals, and input signal voltages must remain between V+ and V-. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1kΩ resistor in series with the input (see Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. This method is not applicable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low RON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see Figure 8). These additional diodes limit the analog signal from 1V below V+ to 1V above V-. The low leakage current performance is unaffected by this approach, but the switch resistance may increase, especially at low supply voltages. OPTIONAL PROTECTION RESISTOR FOR LOGIC INPUTS OPTIONAL PROTECTION DIODE V+ 1kΩ LOGIC VNO OR NC VCOM VOPTIONAL PROTECTION DIODE FIGURE 8. INPUT OVERVOLTAGE PROTECTION 12 This family of switches performs equally well when operated with bipolar or single voltage supplies. The minimum recommended supply voltage is 2V or ±2V. It is important to note that the input signal range, switching times, and onresistance degrade at lower supply voltages. Refer to the electrical specification tables and Typical Performance curves for details. V+ and GND power the internal logic (thus setting the digital switching point) and level shifters. The level shifters convert the logic levels to switched V+ and V- signals to drive the analog switch gate terminals. Logic-Level Thresholds V+ and GND power the internal logic stages, so V- has no affect on logic thresholds. This switch family is TTL compatible (0.8V and 2.4V) over a V+ supply range of 2.7V to 10V. At 12V the VIH level is about 3.5V. This is still below the CMOS guaranteed high output minimum level of 4V, but noise margin is reduced. For best results with a 12V supply, use a logic family that provides a VOH greater than 4V. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation. High-Frequency Performance In 50Ω systems, signal response is reasonably flat even past 100MHz (see Figure 17). Figure 17 also illustrates that the frequency response is very consistent over varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feed through from a switch’s input to its output. Off Isolation is the resistance to this feed through, while Crosstalk indicates the amount of feed through from one switch to another. Figure 18 details the high Off Isolation and Crosstalk rejection provided by this family. At 10MHz, Off Isolation is about 55dB in 50Ω systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease Off Isolation and Crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance. ISL84051, ISL84052, ISL84053 Leakage Considerations Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and V-. One of these diodes conducts if any analog signal exceeds V+ or V-. Virtually all the analog leakage current comes from the ESD diodes to V+ or V-. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or V- and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and V- pins constitutes the analog-signalpath leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and GND. Typical Performance Curves TA = 25oC, Unless Otherwise Specified 225 200 70 VCOM = (V+) - 1V ICOM = 1mA V- = -5V 60 175 150 85oC 40 25oC 30 -40oC 20 400 V- = 0V 300 200 85oC 100 0 25oC -40oC 2 3 4 5 6 7 V+ (V) 8 9 10 11 50 85oC 85oC V+ = 5V 25oC V+ = 3.3V -40oC V- = 0V V- = 0V 25oC -40oC 1 3 2 VCOM (V) 4 5 FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE 2 VS = ±2V 85oC V+ = 2.7V V- = 0V -40oC 0 25oC 1 -40oC 0 VS = ±3V 85oC Q (pC) RON (Ω) ICOM = 1mA 25oC 75 160 140 120 100 80 60 100 90 80 70 60 50 40 12 FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE 120 110 100 90 80 70 60 50 90 80 70 60 50 40 30 60 85oC 125 100 RON (Ω) RON (Ω) 50 ICOM = 1mA 25oC -40oC -1 VS = ±5V VS = ±5V 85oC 25oC V+ = 5V V- = 0V -2 40 30 -40oC -3 -5 20 -5 -4 -3 -2 -1 0 1 2 3 4 VCOM (V) FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE 13 5 -2.5 0 VCOM (V) 2.5 FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE 5 ISL84051, ISL84052, ISL84053 Typical Performance Curves TA = 25oC, Unless Otherwise Specified (Continued) 200 500 400 -40oC 150 25oC 300 200 tOFF (ns) -40oC 0 250 V- = 0V 200 85oC 150 100 0 100 V- = 0V 85oC 80 25oC 40 -40oC 20 -40oC 0 0 2 85oC -40oC 60 25oC 50 25oC 50 85oC 3 4 5 6 7 8 9 10 11 12 2 3 4 6 5 V+ (V) 300 12 11 250 VCOM = (V+) - 1V V- = 0V 200 tRANS (ns) 200 150 100 150 100 25oC 25oC 85oC 85oC 50 50 -40oC -40oC 0 0 2 3 4 5 6 7 8 9 10 11 2 13 12 3 4 5 6 V± (V) V+ (V) FIGURE 15. ADDRESS TRANS TIME vs SINGLE SUPPLY VOLTAGE FIGURE 16. ADDRESS TRANS TIME vs DUAL SUPPLY VOLTAGE -10 VS = ±5V 3 ISL84053 GAIN 0 -3 ISL84053 ISL84051 ISL84052 0 45 90 135 180 RL = 50Ω 10 100 FREQUENCY (MHz) FIGURE 17. FREQUENCY RESPONSE 14 600 PHASE (DEGREES) ISL84052 CROSSTALK (dB) ISL84051 PHASE 10 V+ = 3V to 12V or -20 VS = ±2V to ±5V RL = 50Ω -30 VIN = 0.2VP-P to 5VP-P 20 30 -40 40 -50 50 -60 60 ISOLATION -70 70 -80 80 CROSSTALK -90 90 -100 100 -110 1k 10k 100k 1M 10M 110 100M 500M FREQUENCY (Hz) FIGURE 18. CROSSTALK AND OFF ISOLATION OFF ISOLATION (dB) tRANS (ns) 10 9 FIGURE 14. INHIBIT TURN - OFF TIME vs SUPPLY VOLTAGE VCOM = (V+) - 1V 250 NORMALIZED GAIN (dB) 8 7 V+ (V) FIGURE 13. INHIBIT TURN - ON TIME vs SUPPLY VOLTAGE 1 VCOM = (V+) - 1V V- = -5V 25oC 100 25oC 100 tON (ns) -40oC VCOM = (V+) - 1V V- = -5V ISL84051, ISL84052, ISL84053 Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: ISL84051: 193 ISL84052: 193 ISL84053: 193 PROCESS: Si Gate CMOS 15 ISL84051, ISL84052, ISL84053 Small Outline Plastic Packages (SOIC) M16.15 (JEDEC MS-012-AC ISSUE C) 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE N INCHES INDEX AREA H 0.25(0.010) M B M SYMBOL E -B- 1 2 3 L SEATING PLANE -A- h x 45o A D -C- e B 0.25(0.010) M C 0.10(0.004) C A M B S MILLIMETERS MAX MIN MAX NOTES A 0.053 0.069 1.35 1.75 - A1 0.004 0.010 0.10 0.25 - B 0.014 0.019 0.35 0.49 9 C 0.007 0.010 0.19 0.25 - D 0.386 0.394 9.80 10.00 3 E 0.150 0.157 3.80 4.00 4 e µα A1 MIN 0.050 BSC 1.27 BSC - H 0.228 0.244 5.80 6.20 - h 0.010 0.020 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 8o 0o N α 16 0o 16 7 8o Rev. 1 02/02 NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 16 ISL84051, ISL84052, ISL84053 Shrink Small Outline Plastic Packages (SSOP) M16.15A N INDEX AREA H 0.25(0.010) M 16 LEAD SHRINK NARROW BODY SMALL OUTLINE PLASTIC PACKAGE B M E 1 2 INCHES GAUGE PLANE -B- SYMBOL 3 0.25 0.010 SEATING PLANE -A- h x 45o A D -C- e α A2 A1 B 0.17(0.007) M L C 0.10(0.004) C A M B S NOTES: MIN MIN MAX NOTES A 0.061 0.068 1.55 1.73 - A1 0.004 0.0098 0.102 0.249 - A2 0.055 0.061 1.40 1.55 - B 0.008 0.012 0.20 0.31 9 C 0.0075 0.0098 0.191 0.249 - D 0.189 0.196 4.80 4.98 3 E 0.150 0.157 3.81 3.99 4 e 0.025 BSC 0.635 BSC - H 0.230 0.244 5.84 6.20 - h 0.010 0.016 0.25 0.41 5 L 0.016 0.035 0.41 0.89 6 N 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. MILLIMETERS MAX α 16 0o 16 8o 0o 7 8o 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. Rev. 1 2/02 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of “B” dimension at maximum material condition. 10. Controlling dimension: INCHES. Converted millimeter dimensions are not necessarily exact. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 17