ISL14011 ® Data Sheet January 30, 2007 Low Jitter Clock Generators for Set-Top Box The ISL14011 series of devices are general purpose integrated Clock Synthesizers and Generators suited for consumer applications such as Set-top Box, and various other consumer applications. The selectable reference input accepts 30MHz signal either from crystal or an external source. It is specified to operate with a nominal 3.3V supply and is offered in 16 Ld QFN package. Contact Factory for other output frequency options. ISL14011IRZ* PART MARKING TEMP. RANGE (°C) 11IZ Features • LVTTL Outputs • Selectable Crystal or Ref. Clock for Inputs • Period Jitter ~50ps RMS • Single Supply; 3.3V nominal • Extended Temperature Range: -40°C to +85°C • Available in small foot print package - 16 Ld QFN 3mmx3mm • Pb-Free plus anneal available (RoHS Compliant) Applications Ordering Information PART NUMBER FN6427.0 -40 to +85 PACKAGE 16 Ld QFN PKG. DWG. # L16.3x3 • Set-Top Boxes Pinout ISL14011 (16 LD QFN) TOP VIEW NC VCC CLK4 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. VCC *Add "-T" suffix for tape and reel. 16 15 14 13 VCC 1 4 LVTTL 1 25, 30, 24, 27 16 Ld QFN 10 CLK2 GND 4 9 5 6 7 8 CLK1 30MHz X2 3 GND ISL14011 11 CLK3 NC NUMBER OF OUTPUT PART INPUT OPTIONS FREQUENCY OUTPUTS FREQUENCY PACKAGE X1 2 GND Selection Table 12 NC NC CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL14011 Functional Block Diagram CLK1 OSC. M1 PHASE FREQ DET. VCO1 CLK2 30MHz CRYSTAL N1 CLK3 M2 PHASE FREQ DET. VCO2 CLK4 N2 Pin Description 16 LD QFN SYMBOLS 1,14,16 VCC 2 X1 The X1 pin is the terminal 1 of an external 30MHz crystal. This pin is grounded for external CK input. 3 X2 The X2 pin is the terminal 2 of external 30MHz crystal, or external clock input. 4, 5, 7 GND Ground 8 CLK1 CLK1 Output: 25MHz 10 CLK2 CLK2 Output: 30MHz 11 CLK3 CLK3 Output: 24MHz 13 CLK4 CLK4 Output: 27MHz 6, 9,12,15 NC 2 PIN DESCRIPTION Supply Voltage No Connect FN6427.0 January 30, 2007 ISL14011 Absolute Maximum Ratings Thermal Information Voltage on VCC, CLK pins (respect to Gnd) . . . . . . . . -0.3V to 4.0V Voltage on X1, X2 pins (respect to Gnd) . . . . . . . . . . . -0.3V to 2.5V ESD Rating MIL STD-883, Method 3014 . . . . . . . . . . . . . . . . . . . . . . . . .>±5kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>500V Thermal Resistance (Typical, Note 1) θJA (°C/W) θJC (°C/W) 16 Ld QFN Package. . . . . . . . . . . . . . . 59 11.5 Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65ºC to +150ºC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300ºC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. DC Electrical Specifications SYMBOL VCC = 3.3V ±10%, TA = -40ºC to +85ºC, Typical values are at TA = +25ºC and VCC = 3.3V, Unless otherwise noted SYMBOL CONDITIONS Supply Voltage VCC Supply Voltage Supply Current ICC Supply Current CL = 5pF on all outputs MIN TYP MAX UNIT 3.0 3.3 3.6 V 11 15 mA 2.4 V 0.5 V CLOCK INPUT X2 (X1 GROUNDED) FOR EXTERNAL CLOCK MODE Input High Level VIH Input Level Low VIL Input Current 1.5 IIL, IIH VX2 to Ground VOH IOH = -100µA 0.5 mA CLOCK OUTPUTS (CLK) Output High Level Output Low Level VOL Output Short Circuit Current IOSC AC Electrical Specifications SYMBOL VCC-0.2 V IOH = -4mA 2.4 V IOH = -6mA 2.1 V IOL = 100µA 0.2 V IOL = 4mA 0.4 V IOL = 6mA 0.75 V CLK = VCC or Gnd 13 30 mA MIN TYP MAX UNIT CL= 5pF on all outputs SYMBOL Crystal Frequency 6 CONDITIONS fin 30 MHz CLOCK OUTPUTS Rise Time tR 20% to 80% VCC 1.8 ns Fall Time tF 80% to 20% VCC 1.8 ns Duty Cycle 40 60 % Period Jitter JP RMS 50 ps Power Up Time tPO VCC >2.7V 2 ms 3 FN6427.0 January 30, 2007 ISL14011 Typical Performance Curves (Period Jitter) 70 VSUPPLY = 3.3V TEMPERATURE +23ºC PERIOD JITTER SIGMA (ps) 65 60 CK1 55 CK2 50 45 CK4 40 CK3 35 30 25 20 0 2 4 6 8 10 12 14 LOAD CAPACITANCE (pF) FIGURE 1. STANDARD DEVIATION vs LOAD CAPACITANCE 4 FN6427.0 January 30, 2007 ISL14011 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) L16.3x3 16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE 2X MILLIMETERS 0.15 C A D A 9 D/2 D1 D1/2 2X N 6 INDEX AREA 0.15 C B MIN NOMINAL E1/2 E A 0.80 0.90 1.00 - - - 0.05 - A2 - - 1.00 9 A3 0.20 REF 0.18 0.15 C B B TOP VIEW A2 D1 2.75 BSC 9 1.35 A 0 0.08 C 9 5 NX b 0.10 4X P D2 (DATUM B) A1 7, 8, 10 9 1.65 7, 8, 10 0.50 BSC - k 0.20 - - - L 0.30 0.40 0.50 8 N 16 2 Nd 4 3 4 3 8 P - - 0.60 NX k θ - - 12 7 D2 2 N 1.50 Ne M CA B 1.65 2.75 BSC 1.35 e / / 0.10 C 1.50 3.00 BSC E1 C A3 5, 8 - E2 SIDE VIEW 0.30 3.00 BSC E SEATING PLANE 0.23 9 D D2 2X 0.15 C A NOTES E/2 E1 2X MAX A1 b 1 2 3 9 4X SYMBOL 9 9 Rev. 1 6/04 4X P NOTES: 1 (DATUM A) 2 3 6 INDEX AREA E2/2 NX L N e 8 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. (Ne-1)Xe REF. E2 2. N is the number of terminals. 7 3. Nd and Ne refer to the number of terminals on each D and E. 8 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 9 CORNER OPTION 4X (Nd-1)Xe REF. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. BOTTOM VIEW A1 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. NX b 5 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. SECTION "C-C" C L 9. Features and dimensions A2, A3, D1, E1, P & θ are present when Anvil singulation method is used and not present for saw singulation. C L L1 10 L L1 10 L 10. Compliant to JEDEC MO-220VEED-2 Issue C, except for the E2 and D2 MAX dimension. e e TERMINAL TIP FOR ODD TERMINAL/SIDE FOR EVEN TERMINAL/SIDE C C All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 5 FN6427.0 January 30, 2007