:/ &6 3 IP4856CX25/C SD 3.0-compliant memory card integrated dual voltage level translator with EMI filter and ESD protection Rev. 2 — 15 October 2014 Product data sheet 1. General description The device is an SD 3.0-compliant 6-bit bidirectional dual voltage level translator. It is designed to interface between a memory card operating at 1.8 V or 2.9 V signal levels and a host with a fixed nominal supply voltage of 1.7 V to 3.6 V. The device supports SD 3.0, SDR104, SDR50, DDR50, SDR25, SDR12 and SD 2.0 high-speed (50 MHz) and default-speed (25 MHz) modes. The device has an integrated voltage selectable low dropout regulator to supply the card-side I/Os, built-in EMI filters and robust ESD protections (IEC 61000-4-2, level 4). 2. Features and benefits Supports up to 208 MHz clock rate Feedback channel for clock synchronization SD 3.0 specification-compliant voltage translation to support SDR104, SDR50, DDR50, SDR25, SDR12, high-speed and default-speed modes 100 mA low dropout voltage regulator to supply the card-side I/Os Low power consumption by push-pull output stage with break-before-make architecture Integrated pull-up and pull-down resistors: no external resistors required Integrated EMI filters suppress higher harmonics of digital I/Os Integrated 8 kV ESD protection according to IEC 61000-4-2, level 4 on card side Level shifting buffers keep ESD stress away from the host (zero-clamping concept) 25-ball WLCSP; pitch 0.4 mm 3. Applications Smartphones Mobile handsets Digital cameras Tablet PCs Laptop computers SD, MMC or microSD card readers 4. Ordering information Table 1. Ordering information Type number IP4856CX25/C Package Name Description Version WLCSP25 wafer level chip-size package with back side coating; 25 bumps (5 5); typical size: 2.05 mm 2.05 mm 0.51 mm - IP4856CX25/C NXP Semiconductors SD 3.0-compliant memory card integrated dual voltage level translator 5. Block diagram 96833/< 9&&% '&'& 96833/< 9&&$ 96'B5() ,3&; 6(/ /'2 &21752/ /2*,& (1$%/( &/.B,1 &/.B)% &/.B6' &0'B',5 &0'B+ +267 %$6( %$1' (0, N9(6' 3527(&7,21 ',5B &0'B6' (0,),/7(5 $1' 5(6,6725 1(7:25. '$7$B+ N9(6' 3527(&7,21 ',5BB '$7$B6' '$7$B+ '$7$B6' '$7$B+ '$7$B6' '$7$B+ '$7$B6' :3 :3 &' 0(025< &$5' (6' &' DDD Fig 1. Block diagram IP4856CX25_C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 2 of 21 IP4856CX25/C NXP Semiconductors SD 3.0-compliant memory card integrated dual voltage level translator 6. Functional diagram 96833/< 6(/ &$5'6,'( 9259 5 92/7$*(6(/(&7 ,17(51$/5()(5(1&( 96'B5() 92/7$*( 5(*8/$725 9/'2 5 5 5 &/.B,1 &/.B6' 5 &/.B)% 5 ',5B&0' 5 &0'B6' 5 &0'B+ 5 ',5B 5 '$7$B6' 5 '$7$B+ 5 ',5BB 5 '$7$B6' 5 '$7$B+ 5 5 '$7$B6' 5 '$7$B+ 5 '$7$B6' 5 '$7$B+ 5 9&&$ 5 (1$%/( 5 5 5 &' :3 *1' DDD Fig 2. Functional diagram IP4856CX25_C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 3 of 21 IP4856CX25/C NXP Semiconductors SD 3.0-compliant memory card integrated dual voltage level translator 7. Pinning information 7.1 Pinning bump A1 index area 1 2 3 4 5 A B C D E aaa-015216 transparent top view, solder balls facing down Fig 3. Pin configuration WLCSP25 Table 2. Pin allocation table Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol A1 DATA2_H A2 DIR_CMD A3 DIR_0 A4 VSUPPLY A5 DATA2_SD B1 DATA3_H B2 SEL B3 VCCA B4 VLDO B5 DATA3_SD C1 CLK_IN C2 ENABLE C3 GND C4 VSD_REF C5 CLK_SD D1 DATA0_H D2 CMD_H D3 CD D4 CMD_SD D5 DATA0_SD E1 DATA1_H E2 CLK_FB E3 DIR_1_3 E4 WP E5 DATA1_SD 7.2 Pin description Table 3. IP4856CX25_C Product data sheet Pin description Symbol[1] Pin Type[2] Description DATA2_H A1 I/O data 2 input or output on host side DIR_CMD A2 I direction control input for command DIR_0 A3 I direction control input for data 0 VSUPPLY A4 S supply voltage (from battery or regulator) DATA2_SD A5 I/O data 2 input or output on memory card side DATA3_H B1 I/O data 3 input or output on host side SEL B2 I card side I/O voltage level select VCCA B3 S supply voltage from host side VLDO B4 O internal supply decoupling DATA3_SD B5 I/O data 3 input or output on memory card side All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 4 of 21 IP4856CX25/C NXP Semiconductors SD 3.0-compliant memory card integrated dual voltage level translator Table 3. Pin description …continued Symbol[1] Pin Type[2] Description CLK_IN C1 I clock signal input on host side ENABLE C2 I device enable input GND C3 S supply ground VSD_REF C4 I reference voltage for the internal voltage regulator CLK_SD C5 O clock signal output on memory card side DATA0_H D1 I/O data 0 input or output on host side CMD_H D2 I/O command input or output on host side CD D3 O card detect switch biasing output CMD_SD D4 I/O command input or output on memory card side DATA0_SD D5 I/O data 0 input or output on memory card side DATA1_H E1 I/O data 1 input or output on host side CLK_FB E2 O clock feedback output on host side DIR_1_3 E3 I direction control input for data 1, data 2, data 3 WP E4 O write protect switch biasing output DATA1_SD E5 I/O data 1 input or output on memory card side [1] The pin names relate particularly to SD memory cards, but also apply to microSD and MMC memory cards. [2] I = input, O = output, I/O = input and output, S = power supply. 8. Functional description 8.1 Level translator The bidirectional level translator shifts the data between the I/O supply levels of the host and the memory card. Dedicated direction control signals determine if a command and data signals are transferred from the memory card to the host (card read mode) or from the host to the memory card (card write mode). The voltage translator has to support several clock and data transfer rates at the signaling levels specified in the SD 3.0 standard specification. Table 4. IP4856CX25_C Product data sheet Supported modes Bus speed mode Signal level (V) Clock rate (MHz) Data rate (MB/s) Default-speed 3.3 25 12.5 High-speed 3.3 50 25 SDR12 1.8 25 12.5 SDR25 1.8 50 25 SDR50 1.8 100 50 SDR104 1.8 208 104 DDR50 1.8 50 50 All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 5 of 21 IP4856CX25/C NXP Semiconductors SD 3.0-compliant memory card integrated dual voltage level translator 8.2 Enable and direction control The pin ENABLE enables/disables the internal Low DropOut (LDO) regulator and is used to put the host-side and card-side I/O drivers into high-ohmic (3-state) mode. Table 5. I/O function control signal truth table Control Host side Level[1] Pin Pin Memory card side Function Pin Function Pin ENABLE = HIGH and VCCA 1.62 V DIR_CMD H CMD_H input CMD_SD output L CMD_H output CMD_SD input H DATA0_H input DATA0_SD output L DATA0_H output DATA0_SD input H DATA1_H DATA2_H DATA3_H input DATA1_SD DATA2_SD DATA3_SD output L DATA1_H DATA2_H DATA3_H output DATA1_SD DATA2_SD DATA3_SD input - - CLK_IN input CLK_SD output - - CLK_FB output - - DIR_0 DIR_1_3 Pin ENABLE = LOW or VCCA 0.8 V DIR_CMD X CMD_H high-ohmic CMD_SD high-ohmic DIR_0 X DATA0_H high-ohmic DATA0_SD high-ohmic DIR_1_3 X DATA1_H DATA2_H DATA3_H high-ohmic DATA1_SD DATA2_SD DATA3_SD high-ohmic - - CLK_IN input CLK_SD high-ohmic - - CLK_IN high-ohmic - - [1] H = HIGH; L = LOW; X = don’t care. 8.3 Integrated voltage regulator The low dropout voltage regulator delivers supply voltage for the voltage translators and the card-side input/output stages. It has to support 1.8 V and 3 V signaling modes as stipulated in the SD 3.0 specification. The switching time between the two output voltage modes is compliant with SD 3.0 specification. Depending on the signaling level at pin SEL, the regulator delivers 1.8 V (SEL = HIGH) or 2.9 V (SEL = LOW, VSD_REF < 1 V). For card supply voltage, see Section 8.4. Table 6. SD card side voltage level control signal truth table Input Output SEL[1] VSD_REF H L [1] VLDO Pin[2] Function X 1.8 V DATA0_SD to DATA3_SD, CLK_SD low supply voltage level (1.8 V typical) <1V 2.9 V DATA0_SD to DATA3_SD, CLK_SD high supply voltage level (2.9 V typical) > 1.5 V VSD_REF DATA0_SD to DATA3_SD, CLK_SD supply voltage level based on VSD_REF [1] H = HIGH; L = LOW; X = don’t care. [2] Host-side pins are not influenced by SEL. IP4856CX25_C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 6 of 21 IP4856CX25/C NXP Semiconductors SD 3.0-compliant memory card integrated dual voltage level translator An external capacitor is needed between the regulator output pin VLDO and ground for proper operation of the integrated voltage regulator. See Table 8 for recommended capacitance and equivalent series resistance. To place the capacitor close to the VLDO pin and maintain short connections to both, to the VLDO and to the ground, is recommended. 8.4 Memory card voltage tracking (reference select) The device can track the memory card supply via pin VSD_REF. This allows achieving optimum interoperability by perfectly matching input/output levels between voltage translator and memory card in the 3 V signaling mode. Therefore, the voltage regulator aims to follow the reference voltage provided at input VSD_REF directly. If tracking of the memory card supply is not desired, connect pin VSD_REF to ground so the voltage regulator refers to an integrated voltage reference. For 1.8 V (SEL = HIGH) signaling, the voltage regulator is referred to the internal reference which is independent of the voltage at VSD_REF. 8.5 Feedback clock channel The clock is transmitted from the host to the memory card side. The voltage translator and the Printed-Circuit Board (PCB) tracks introduce some amount of delay. It reduces timing margin for data read back from memory card, especially at higher data rates. Therefore, a feedback path is provided to compensate the delay. The reasoning behind this approach is the fact that the clock is always delivered by the host, while the data in the timing critical read mode comes from the card. 8.6 EMI filter All input/output driver stages are equipped with EMI filters to reduce interferences towards sensitive mobile communication. 8.7 ESD protection The device has robust ESD protections on all memory card pins as well as on the VSD_REF and VSUPPLY pins. The architecture prevents any stress for the host: the voltage translator discharges any stress to supply ground. Pins Write Protect (WP) and Card Detection (CD) might be pulled down by the memory card which has to be detected by the host. Both signals must be HIGH if no card is inserted. Therefore the pins are equipped with International Electrotechnical Commission (IEC) system-level ESD protections and pull-up resistors connected to the host supply VCCA. IP4856CX25_C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 7 of 21 IP4856CX25/C NXP Semiconductors SD 3.0-compliant memory card integrated dual voltage level translator 9. Limiting values Table 7. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VCC supply voltage 4 ms transient on pin VSUPPLY 0.5 +4.6 V on pin VCCA 0.5 +4.6 V VI input voltage 4 ms transient at I/O pins 0.5 +4.6 V Ptot total power dissipation Tamb = 40 C to +85 C - 1000 mW Tstg storage temperature 55 +150 C Tamb ambient temperature 40 +85 C VESD Ilu(IO) [1] electrostatic discharge voltage IEC 61000-4-2, level 4, all memory card-side pins, VSUPPLY, VSD_REF, WP and CD to ground [1] contact discharge 8 +8 kV air discharge 15 +15 kV Human Body Model (HBM) JEDEC JESD22-A114F; all pins 2000 +2000 V Machine Model (MM) JEDEC JESD22-A115; all pins 200 +200 V 100 +100 mA input/output latch-up current JESD78B: 0.5 VCC < VI < 1.5 VCC; Tj < 125 C All system level tests are performed with the application-specific capacitors connected to the supply pins VSUPPLY, VLDO and VCCA. 10. Recommended operating conditions Table 8. Operating conditions Symbol Parameter VCC supply voltage VI input voltage Conditions [1] on pin VSUPPLY Min Typ Max Unit 2.8 - 3.6 V 1.7 - VSUPPLY V 0.3 - VCCA + 0.3 V memory card side 0.3 - VO(reg) + 0.3 V on pin VCCA [2] host side Cext external capacitance recommended capacitor at pin VLDO - 1.0 - F ESR equivalent series resistance at pin VLDO 0 - 50 m Cext external capacitance recommended capacitor at pin VSUPPLY - 0.1 - F recommended capacitor at pin VCCA - 0.1 - F [1] By minimum value the device is still fully functional, but the voltage on pin VLDO might drop below the recommended memory card supply voltage. [2] The voltage must not exceed 3.6 V. IP4856CX25_C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 8 of 21 IP4856CX25/C NXP Semiconductors SD 3.0-compliant memory card integrated dual voltage level translator Table 9. Integrated resistors Tamb = 25 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Rpd pull-down resistance R7 272 470 668 k R30 70 100 130 R20; R21; R38 200 350 500 k R10 10.5 15 19.5 k pull-up resistance Rpu series resistance Rs [1] R11 to R13 49 70 91 k R14 and R15 70 100 130 k card side; R1 to R6 [1] 12 15 18 host side; R31 to R37 [1] 18 22.5 27 Guaranteed by design and characterization. 11. Static characteristics Table 10. Static characteristics At recommended operating conditions; Tamb = 40 C to +85 C; voltages are referenced to GND (ground = 0 V); Cext = 1 F at pin VLDO; unless otherwise specified. Symbol Parameter Min Typ[1] Max Unit SEL = LOW; VSD_REF < 1 V; VSUPPLY 2.9 V 2.7 2.9 3.3 V SEL = LOW; VSD_REF > 1.5 V; VSUPPLY VSD_REF VSD_REF 0.15 VSD_REF VSD_REF + 0.15 V SEL = HIGH; VSUPPLY 2.5 V 1.7 1.85 2.0 V SEL = LOW; VSUPPLY 2.9 V; IO = 50 mA - - 150 mV - - 100 mA Conditions Supply voltage regulator for card-side I/O pin: VLDO VO(reg) regulator output voltage Vdo(reg) regulator dropout voltage IO(reg) regulator output current Host-side input signals: CMD_H, DATA0_H to DATA3_H and CLK_IN VIH HIGH-level input voltage 0.625 VCCA - VCCA + 0.3 V VIL LOW-level input voltage 0.3 - 0.35 VCCA V ILI input leakage current - - 1.0 nA VCCA = 1.8 V; ENABLE = LOW [2] Host-side control signals SEL, ENABLE, DIR_0, DIR_1_3 and DIR_CMD VIH HIGH-level input voltage 0.625 VCCA - VCCA + 0.3 V VIL LOW-level input voltage 0.3 - 0.35 VCCA V VIH HIGH-level input voltage 1.5 - 3.63 V VIL LOW-level input voltage 0.3 - +1.0 V VSD_REF IP4856CX25_C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 9 of 21 IP4856CX25/C NXP Semiconductors SD 3.0-compliant memory card integrated dual voltage level translator Table 10. Static characteristics …continued At recommended operating conditions; Tamb = 40 C to +85 C; voltages are referenced to GND (ground = 0 V); Cext = 1 F at pin VLDO; unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit - V Host-side output signals: CLK_FB, CMD_H and DATA0_H to DATA3_H VOH HIGH-level output voltage IO = 2 mA; VI = VIH (card side) 0.85 VCCA VOL LOW-level output voltage IO = 2 mA; VI = VIL (card side) - - 0.125 VCCA V SEL = LOW (2.9 V interface) 0.625 VO(reg) - VO(reg) + 0.3 V SEL = HIGH (1.8 V interface) 0.625 VO(reg) - VO(reg) + 0.3 V SEL = LOW (2.9 V interface) 0.3 - 0.35 VO(reg) V SEL = HIGH (1.8 V interface) 0.3 - 0.35 VO(reg) V IO = 4 mA; VI = VIH (host side); SEL = LOW (2.9 V interface) 0.85 VO(reg) - VO(reg) + 0.3 V IO = 2 mA; VI = VIH (host side); SEL = HIGH (1.8 V interface) 0.85 VO(reg) - 2.0 V IO = 4 mA; VI = VIL (host side); SEL = LOW (2.9 V interface) 0.3 - 0.125 VO(reg) V IO = 2 mA; VI = VIL (host side); SEL = HIGH (1.8 V interface) 0.3 - 0.125 VO(reg) V host side - 3.5 5.0 pF card side - 5.0 10.0 pF SEL = LOW (2.9 V interface) - - 100 A SEL = HIGH (1.8 V interface) - - 100 A ENABLE = LOW (inactive mode) - - 1 A Card-side input signals: CMD_SD and DATA0_SD to DATA3_SD HIGH-level input voltage VIH LOW-level input voltage VIL Card-side output signal CMD_SD, DATA0_SD to DATA3_SD and CLK_SD VOH VOL HIGH-level output voltage LOW-level output voltage Bus signal equivalent capacitance Cch channel capacitance VI = 0 V; fi = 1 MHz; VSUPPLY = 3.5 V; VCCA = 1.8 V [3] Current consumption ICC(stat) ICC(stb) static supply current standby supply current ENABLE = HIGH (active mode); all inputs = HIGH; DIR = LOW [1] Typical values are measured at Tamb = 25 C. [2] Guaranteed by design and characterization. [3] EMI filter line capacitance per data channel from I/O driver to pin; Cch is guaranteed by design. IP4856CX25_C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 10 of 21 IP4856CX25/C NXP Semiconductors SD 3.0-compliant memory card integrated dual voltage level translator 12. Dynamic characteristics 12.1 Voltage regulator Table 11. Voltage regulator Tamb = 25 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Voltage regulator output pin: VLDO tstartup(reg) regulator start-up time VCCA = 1.8 V; VSUPPLY = 3.5 V; Cext = 1 F; see Figure 5 - - 100 s tf(o) output fall time VO(reg) = 2.9 V to 1.8 V; SEL = LOW to HIGH; see Figure 4 - - 1 ms tr(o) output rise time VO(reg) = 1.8 V to 2.9 V; SEL = HIGH to LOW; see Figure 4 - - 100 s 9 9 &/.B6' 9 9 9 9 9 9 9 9 9 PVPLQ 9 9 &0' 9 9 9 '$7$>@ 9 6(/ 9 9 9/'2 9 9 WUR WIR 9 P9 9 9 DDD Fig 4. Regulator mode change timing VI 50 % ENABLE GND tstartup(reg) VO(reg) 97 % regulator output 0V 001aah981 Measuring points: ENABLE signal at 0.5 VCCA and regulator output signal at 0.97 VO(reg). Fig 5. Regulator start-up time IP4856CX25_C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 11 of 21 IP4856CX25/C NXP Semiconductors SD 3.0-compliant memory card integrated dual voltage level translator 12.2 Level translator Table 12. Level translator dynamic characteristics At recommended operating conditions; VCCA = 1.8 V; Tamb = 25 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Host-side transition times tr rise time SEL = HIGH (1.8 V interface) [1] - 0.4 1.0 ns tf fall time SEL = HIGH (1.8 V interface) [1] - 0.4 1.0 ns SEL = HIGH (1.8 V interface) [2] 0.4 0.9 1.4 ns SEL = HIGH (1.8 V interface) [2] 0.4 0.9 1.4 ns SEL = HIGH (1.8 V interface) - 2.4 3.5 ns SEL = HIGH (1.8 V interface) - 4.8 7.0 ns - 2.4 3.5 ns Card-side transition times rise time tr fall time tf Host-side to card-side propagation delay DATAx_H to DATAx_SD, CMD_H to CMD_SD and CLK_IN to CLK_SD propagation delay tpd Host-side to host-side propagation delay CLK_IN to CLK_FB propagation delay tpd Card-side to host-side propagation delay DATAx_SD to DATAx_H and CMD_SD to CMD_H propagation delay tpd SEL = HIGH (1.8 V interface) [1] Transition between VOL = 0.35 VCCA and VOH = 0.65 VCCA. [2] Transition between VOL = 0.45 V and VOH = 1.4 V. WW 9&& 9,+ 9,/ *1' Fig 6. WW DDD Output rise and fall times IP4856CX25_C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 12 of 21 IP4856CX25/C NXP Semiconductors SD 3.0-compliant memory card integrated dual voltage level translator 9&& 9,+ 9,+ &/.B,1 9,/ 9,/ *1' RXWSXWGHOD\WLPH 9&& 92+ '$7$>@B6' 92+ *1' Fig 7. DDD Output delay timing 12.3 ESD characteristic of pin write protect and card detect Table 13. ESD characteristic of write protect and card detect At recommended operating conditions; Tamb = 25 C; voltages are referenced to GND (ground = 0 V); unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit ESD protection pins: WP and CD VBR breakdown voltage TLP; I = 1 mA - 8 - V rdyn dynamic resistance positive transient [1] - 0.5 - negative transient [1] - 0.5 - [1] IP4856CX25_C Product data sheet TLP according to ANSI-ESD STM5.5.1/IEC 62615 Zo = 50 ; pulse width = 100 ns; rise time = 200 ps; averaging window = 50 ns to 80 ns. All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 13 of 21 IP4856CX25/C NXP Semiconductors SD 3.0-compliant memory card integrated dual voltage level translator 13. Test information SXOVHZLGWK 9, QHJDWLYH LQSXW 9 WIR WUR WUR WIR 9, SRVLWLYH LQSXW 9 SXOVHZLGWK 96833/< 9&& 38/6( *(1(5$725 5VRXUFH 9, 92 '87 ȍ 5WHUP &/ 5/ DDD Definitions test circuit: Rsource = source resistance of pulse generator. Rterm = termination resistance should be equal to output impedance Zo of pulse generator. CL = load capacitance including jig and probe capacitance. RL = load resistance. Fig 8. IP4856CX25_C Product data sheet Load circuitry for measuring switching time All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 14 of 21 IP4856CX25/C NXP Semiconductors SD 3.0-compliant memory card integrated dual voltage level translator 14. Package outline :/&63ZDIHUOHYHOFKLSVL]HSDFNDJHZLWKEDFNVLGHFRDWLQJEXPSV[ ' $ EXPS$ LQGH[DUHD ( $ $ GHWDLO; H H E ( H ' H & % $ (XURSHDQ SURMHFWLRQ ; ZOFVSB[BFBSR Fig 9. Package outline IP4856CX25/C (WLCSP25 with back side coating) Table 14. Dimensions for Figure 9 Symbol Min Typ Max Unit A 0.47 0.51 0.55 mm A1 0.18 0.20 0.22 mm A2 0.03 0.04 0.05 mm b 0.23 0.25 0.27 mm D 2.01 2.05 2.09 mm E 2.01 2.05 2.09 mm e - 0.4 - mm e1 - 1.6 - mm IP4856CX25_C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 15 of 21 IP4856CX25/C NXP Semiconductors SD 3.0-compliant memory card integrated dual voltage level translator 15. Design and assembly recommendations 15.1 PCB design guidelines For optimum performance, use a Non-Solder Mask PCB Design (NSMD), also known as a copper-defined design, incorporating laser-drilled micro-vias connecting the ground pads to a buried ground-plane layer. This results in the lowest possible ground inductance and provides the best high frequency and ESD performance. For this case, refer to Table 15 for the recommended PCB design parameters. Table 15. Recommended PCB design parameters Parameter Value or specification PCB pad diameter 250 m Micro-via diameter 100 m (0.004 inch) Solder mask aperture diameter 325 m Copper thickness 20 m to 40 m Copper finish AuNi or OSP PCB material FR4 15.2 PCB assembly guidelines for Pb-free soldering Table 16. Assembly recommendations Parameter Value or specification Solder screen aperture diameter 290 m Solder screen thickness 100 m (0.004 inch) Solder paste: Pb-free SnAg (3 % to 4 %) Cu (0.5 % to 0.9 %) Solder to flux ratio 50 : 50 Solder reflow profile see Figure 10 7 & 7UHIORZSHDN FRROLQJUDWH SUHKHDW W W W W W WV DDL The device can withstand at least three reflows with this profile. Fig 10. Pb-free solder reflow profile IP4856CX25_C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 16 of 21 IP4856CX25/C NXP Semiconductors SD 3.0-compliant memory card integrated dual voltage level translator Table 17. Symbol Reflow soldering process characteristics Parameter Conditions Treflow(peak) peak reflow temperature Min Typ Max Unit 230 - 260 C t1 time 1 soak time 60 - 180 s t2 time 2 time during T 250 C - - 30 s t3 time 3 time during T 230 C 10 - 50 s t4 time 4 time during T > 217 C 30 - 150 s t5 time 5 dT/dt rate of change of temperature - - 540 s cooling rate - - 6 C/s preheat 2.5 - 4.0 C/s 16. Abbreviations Table 18. Acronym IP4856CX25_C Product data sheet Abbreviations Description DUT Device Under Test EMI ElectroMagnetic Interference ESD ElectroStatic Discharge FR4 Flame Retard 4 MMC MultiMedia Card NSMD Non-Solder Mask PCB Design OSP Organic Solderability Preservation PCB Printed-Circuit Board RoHS Restriction of Hazardous Substances SD Secure Digital WLCSP Wafer-Level Chip-Scale Package All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 17 of 21 IP4856CX25/C NXP Semiconductors SD 3.0-compliant memory card integrated dual voltage level translator 17. Revision history Table 19. Revision history Document ID Release date Data sheet status Change notice Supersedes IP4856CX25_C v.2 20141015 Product data sheet - IP4856CX25 v.1 Modifications: IP4856CX25 v.1 IP4856CX25_C Product data sheet • • Product without back side coating has been removed Product status changed 20140602 Preliminary data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2014 - © NXP Semiconductors N.V. 2014. All rights reserved. 18 of 21 IP4856CX25/C NXP Semiconductors SD 3.0-compliant memory card integrated dual voltage level translator 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 18.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. IP4856CX25_C Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 19 of 21 IP4856CX25/C NXP Semiconductors SD 3.0-compliant memory card integrated dual voltage level translator Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] IP4856CX25_C Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 October 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 20 of 21 IP4856CX25/C NXP Semiconductors SD 3.0-compliant memory card integrated dual voltage level translator 20. Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 9 10 11 12 12.1 12.2 12.3 13 14 15 15.1 15.2 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Level translator . . . . . . . . . . . . . . . . . . . . . . . . . 5 Enable and direction control . . . . . . . . . . . . . . . 6 Integrated voltage regulator . . . . . . . . . . . . . . . 6 Memory card voltage tracking (reference select) . . . . . . . . . . . . . . . . . . . . . . . 7 Feedback clock channel . . . . . . . . . . . . . . . . . . 7 EMI filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended operating conditions. . . . . . . . 8 Static characteristics. . . . . . . . . . . . . . . . . . . . . 9 Dynamic characteristics . . . . . . . . . . . . . . . . . 11 Voltage regulator. . . . . . . . . . . . . . . . . . . . . . . 11 Level translator . . . . . . . . . . . . . . . . . . . . . . . . 12 ESD characteristic of pin write protect and card detect . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Test information . . . . . . . . . . . . . . . . . . . . . . . . 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 Design and assembly recommendations . . . 16 PCB design guidelines . . . . . . . . . . . . . . . . . . 16 PCB assembly guidelines for Pb-free soldering . . . . . . . . . . . . . . . . . . . . . . 16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Contact information. . . . . . . . . . . . . . . . . . . . . 20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 15 October 2014 Document identifier: IP4856CX25_C