TH3122 K-Bus Transceiver with integrated Voltage Regulator Pin Diagram Features and Benefits SOIC16 K-Bus Transceiver: VS 1 16 VCC EN 2 15 SENSE BUS input voltage -24V ... 30V (independently of VS) VTR 3 14 RESET ISO 9141 and ODBII compliant GND 4 13 GND Possibility of BUS wake up GND 5 12 GND BUS 6 11 TxD SI 7 10 RxD SO 8 9 PNP-open emitter driver with slew rate control and current limitation Operating voltage VS = 5.5 ... 16 V Very low standby current consumption <100 µ A in normal mode (< 50 µ A in sleep mode) TH3122 SEN/STA Linear low drop voltage regulator: Output voltage 5V± 2% Output current max. 100mA Output current limitation Overtemperature shutdown Configurable reset time (15ms/100ms) and reset threshold voltage (3.15V / 4.65V) Low voltage detection at VS Wake-up by K-BUS traffic and start-up capable independent of EN voltage level Universal comparator with an input voltage range –24V … 30V and digital output Load dump protected (40V) Ordering Information Part No. Temperature Code Package Code TH3122 K ( -40ºC to 125ºC ) DF ( SOIC16, 300mil ) General Description The TH3122 consists of a low drop voltage regulator 5V/100mA and a K-Bus transceiver. The transceiver is suitable for K-Bus systems conform to ISO 9141. The combination of voltage regulator and bus transceiver in combination with the monitoring 3901003122 Rev 004 functions make it possible to develop simple, but powerful and cheap nodes in K-Bus systems. The wide output current area and the configurable reset time and reset voltage works together with many different microcontrollers. Page 1 Dec/04 TH3122 K-Bus Transceiver with integrated Voltage Regulator Functional Diagram VCC VS Power Supply EN Over Temp SENSE 7.8V 6.8V +5V +5V Reset-Logic RESET VTR VTR-Logic OSC Wake-up VthH VthL RxD BUS Bus-Logic TxD pnp Control slew rate foldback SEN/STA +5V SI SO VTHSI_H VTHSI_L Figure 1 - Block Diagram 3901003122 Rev 004 Page 2 Dec/04 TH3122 K-Bus Transceiver with integrated Voltage Regulator Functional Description The TH3122 consists of a voltage regulator 5V/100mA and a K-Bus transceiver, which is a bi-directional bus interface device for data transfer between K-Bus and the K-Bus protocol controller. to Wake-up Logic Also integrated into the transceiver are a voltage and time controlled reset management, power down, wake up function and a universal comparator for extended applications. tdebWake tdebBUS Controllogic RxD VthH VthL POR VBAT POR VCC VCC pnpControl Bit-Compare Constant-Low BUS - slew rate - IB - foldback TxD ESD VCC SENSE OSC Vref Biasing ESD Figure 2 - Block Diagram K-Bus Transceiver K-BUS Interface The BUS Interface builds the connection between the serial 5V bus line of the protocol controller and the 12V K-Bus line. The transceiver consists of a pnp-driver with slew rate control and fold-back characteristic and contains also in the receiver a high voltage comparator followed by a debouncing unit. electromagnetic emission of the bus line, the TH3122 has an integrated slew rate control. Receive Mode The data at the pin BUS will be transferred to the pin RxD. Short spikes on the bus signal are suppressed by the implemented debouncing circuit. Transmit Mode BUS During the transmission the data at the pin TxD will be transferred to the pin BUS. To minimize the < tdebH < tdebL SEN/STA RxD tdebH TxD tdebL Figure 4 - Receive Mode Pulse Diagram BUS Figure 3 - Transmit Mode Pulse Diagram 3901003122 Rev 004 Page 3 Dec/04 TH3122 K-Bus Transceiver with integrated Voltage Regulator Bit Compare If the signals at the pin TxD and the pin BUS within a specified time tbc are not identical, the transmission will be interrupted. If both signals at TxD and BUS are “High” within the time tena the transmission will be enabled. The bit-compare-function is active when the pin SEN/ STA is open (not overwritten). Using this pin as an input the transmission path can be overwritten (independent of bit-compare and constant-low function): SEN/STA=”0” forcing the transmission path free SEN/STA=”1” disable the transmission path Constant Low Switch Off A falling edge at pin TxD (from “1” to “0”) starts the internal constant low timer (SEN/STA open). If the low level “0” is valid for the time tlow the transmission unit of the TH3122 will be disabled. The receive unit is still active. A high level “1” at TxD with a minimum pulse width of trec resets the constant low timer. Transmitting is not possible until TxD and BUS is High for the time tena. t < trec Figure 5 - Bit Compare Pulse Diagram TxD SEN/STA The pin SEN/STA is bidirectional. Used as an output the pin indicates whether the transmit-path is enabled or disabled: SEN/STA =”0” transmission path is enabled SEN/STA =”1” transmission path is disabled SEN/STA tlow tena Figure 6 - Constant Low Pulse Diagram Linear Regulator and Controlling Functions Regulator The TH3122 has an integrated linear regulator with an output voltage of 5V ±2% and an output current of max. 100mA. The regulator is switched on or off with a signal on the EN pin or wakes up with a BUS signal. Initialization voltage level on the VTR pin (see table VTR Programming). After tRES a rising edge on the RESET output is generated (see figure 7 - Initialization). The regulator is active and can only be switched off with a falling edge on EN. The regulator remains with EN=high in active mode and therefore the VCC voltage is also active. The initialization is started if the power supply is switched on, or after the temperature limitation has switched off the regulator or in case of BUS traffic (wake up). If the VCC voltage level is higher than VRESEIN, the reset time tRES is started. This reset time is determined by the 3901003122 Rev 004 Page 4 Dec/04 TH3122 K-Bus Transceiver with integrated Voltage Regulator VTR-Mode VRES tRes VTR = GND VRES = VRES1 = 3.15V 100ms VTR = VCC VRES = VRES2 = 4.65V 100ms VRES1/2 VTR with R ≥ 50k Ω to GND VRES = VRES1 = 3.15V 15ms trr VTR with R ≥ 50k Ω to VCC VRES = VRES2 = 4.65V 15ms VS VRESEIN VCC tRes RESET VTR-Programming Figure 7 - Initialization The input EN has an internal pull down resistor. If EN=high, the internal pull down current is switched off to minimize the quiescent current. RESET Output The RESET output is switched from low to high if VS is switched on and VCC>VRESEIN after the time tRES. If the voltage VCC drops below VRES1 or VRES2 then the RESET output is switched from high to low after the time trr has been reached. The voltage level for VRES1 and VRES2 and the corresponding times tRES can be programmed via the analogue input VTR. The voltage on VTR input is read out if the voltage at this pin is higher than VRESEIN . This value defines the reset switch off voltage VRES. With the next oscillator cycle it switches on the pull up current source if VTR=low or the pull down current source if VTR=high. The sources are active for one oscillator cycle. The level changes during this procedure on VTR, which depends on the external pull up or pull down resistors control the reset time tRes Temperature Limitation If the junction temperature 150ºC < Tj < 170ºC the over temperature recognition will be active and the regulator voltage and the BUS driver will be switched off. After Tj falls below 140ºC the TH3122 will be initialized, independently of the voltage levels on EN and BUS. The function of the TH3122 is possible between TAmax and the switch off temperature, but small parameter differences can appear. Wake up with BUS traffic If the regulator is put in standby mode it can be woken up with the BUS interface. Every pulse on the BUS (high pulse or low pulse) with a pulse width of min. 45 µ s will switch on the regulator. Low Voltage Detection VS After the BUS has woken up the regulator, it can only be switched off with a high level followed by a low level on the EN pin. If VS has reached the level of VS =6.8V then the SENSE output generates low level. The normal operating range is VS > 7.8V and the SENSE output generates a high level. Low voltage on VS is monitored on SENSE output. Reset Programming on VTR With the VTR pin the reset switches off levels and delay time can be programmed. The voltage on VCC influences the reset function. 3901003122 Rev 004 Universal Comparator The TH3122 consist of a universal comparator for general use. The positive input of this comparator is connected to the pin SI. The input voltage range of SI is 0V...VS. The input voltage is compared with a fixed reference voltage at high or low level and the comparator output SO drives a 5V digital signal. Page 5 Dec/04 TH3122 K-Bus Transceiver with integrated Voltage Regulator Application Hints Regulator Circuitry Operating during Disturbances The absence of VS ,VCC or GND connection or ground shift either alone or in any combination, do not influence or disturb the communication between other bus nodes. Undervoltage The reset unit secures the correct behavior of the driver during undervoltage. The inputs have pull-up or pulldown characteristics and have therefore defined voltage levels. The choice and dimension of the capacitor on VCC is determined by application point of view. Important parameters are the current difference on load changes and the maximum short time voltage drop. The VCC pin must be connected to a min. 2 µ F capacitor for stable operating of the regulator in the whole operating range. Short Circuit Proof With 4.5V ≤ VCC ≤ 5.25V the bus connection operates within the correct parameters . All in- and outputs are short circuit proof to battery and ground. A thermal shut down circuit prevents VCC and BUS from any damage. If VRES1 ≤ VCC ≤4.5V the TxD signal is transmitted to the bus. The receive mode is also active. Baud Rate If VCC < VRES1the bus driver is tristate. The TH3122 has a maximum Baud rate of 9600 Baud SENSE and SO output the correct signal if VCC > VRES . The specificated values of the input voltages on SO can’t guaranteed. (CBUS < 25nF, RPU > 400 Ω). Application Circuitry battery reverse diode VBat 100u 47n 33uH BUS 82p optional µC TH3122 VS VCC EN SENSE VTR RESET GND GND GND GND BUS TxD SI RxD SO SEN/STA +5V Port X.1 Reset 6.8u TxD RxD 10 Control Unit 100p Figure 8 - Application Circuit There should be used an LC-Filter to minimize the influence of EMI on the BUS lines. 3901003122 Rev 004 Page 6 Dec/04 TH3122 K-Bus Transceiver with integrated Voltage Regulator Electrical Specification All voltages are referenced to ground (GND). Positive currents flow into the IC. The absolute maximum ratings given in the table below are limiting values that do not lead to a permanent damage of the device but exceeding any of these limits may do so. Long term exposure to limiting values may affect the reliability of the device. Reliable operation of the TH3122 is only specified within the limits shown in ”Operating conditions”. Operating Conditions Parameter Symbol Min Max Unit Battery voltage VS 5.25 16 V Supply voltage VCC 4.75 5.25 V Operating ambient temperature TA -40 +125 °C Junction temperature [1] TJ +150 °C Absolute Maximum Ratings Parameter Symbol Supply voltage at VS [2] VS Input voltage at pin BUS [2] VINBUS Condition Min Max -1.0 16 T ≤ 1min - 30 T ≤ 500 ms - 40 -24 30 - 40 Unit V V T ≤ 500 ms Difference VS-VCC VS-VCC -0.3 40 V Input voltage at pin EN and SI VINENSI -0.3 VS+0.3 V Input voltage at pin VTR, TxD, SEN/STA, SO, RESET, SENSE VIN -0.3 VCC+0.3 V Input current at pin EN, VTR, SI, SO, SEN/STA, TxD, RxD,RESET, SENSE IIN -25 25 mA IShort -500 500 mA Input current for short circuit of pin VS and VCC Power dissipation P0 Thermal resistance from junction to ambient Junction temperature [4] Storage temperature Internal limited [3] [4] mW RTHJA 50 K/W TJ 150 °C 150 °C TSTG -55 ______________________________ [1] Junction temperature is defined in IEC 747-1 The current and voltage values are valid independent from each other. [3] The maximum power dissipation is defined by the ambient temperature and the thermal resistance. It can be calculated with P0 =(VS-VCC)*IVCC+PBUS. PBUS is the BUS driver output with normally ≤25 mW [4] see over temperature protection [2] 3901003122 Rev 004 Page 7 Dec/04 TH3122 K-Bus Transceiver with integrated Voltage Regulator Static Characteristics (VS = 5.25 to 16V, VCC= 4.75 to 5.25V, TA = -40 to +125°C, unless otherwise specified) Parameter Symbol Condition Min Typ Max Unit VCCn 5.5V ≤ VS ≤ 16V TA = 25°C 4.95 5.0 5.05 V VCCt 5.5V ≤ VS ≤ 16V 4.90 5.0 5.10 V VCCh VSUP > 16V 4.95 5.0 5.25 V VCCI 3.3 V< VS< 5.5 V 5.1 V ISnl VEN = VS = 12V, Pins 8-11, 14-16 open 100 µA ISsleep VEN = 0V, VCC switched off 50 µA VS ≥ 4.0V, IVCC = 25mA 200 mV VS ≥ 4.0V, IVCC = 100mA 400 mV VS ≥ 3.3V, IVCC = 20mA 600 mV Linear Regulator Output voltage VCC Supply current, „normal mode“ Supply current, „sleep mode“ Drop-out voltage VD Output current VCC IVCC VS ≥ 3.0V Current limitation VCC ILVCC VS > 0V Load capacity Cload ESR ≤ 5Ω Power-on-reset threshold “VCC on” VRESEIN VS-VD 35 100 mA 300 mA µF 2 refered to VCC, VS > 4.6V 4.5 4.65 4.8 VRES2 VTR=High, VS > 0V 4.5 4.65 4.8 VRES1 VTR=Low, VS > 0V 3.0 3.15 3.3 Power-on-reset threshold “VCC off” V V SENSE-Output VS - threshold low at SENSE VSENL VS - threshold high an SENSE VSENH 6.8 V 7.8 Hysteresis SENSE VSENHYS Output voltage low VOL IOUT = 1mA Output voltage high VOH IOUT = -1mA 100 V mV 0.8 VCC-0.8 V V Enable-Input EN Input voltage low VENL -0.3 1.75 V Input voltage high VENH 2.5 VS +0.3 V VENHYS 100 Hysteresis Pull-down current EN IpdEN mV VEN > VENH 1.8 4.0 7.5 µA VEN < VENL 70 100 130 µA IOUT = 1 mA, VSUP > 5.5 V 0.8 V 10 k Ω RESET to VCC 0.2 V -250 µA Output RESET Output voltage low Pull-up current 3901003122 Rev 004 VOL Ipu -500 Page 8 -375 Dec/04 TH3122 K-Bus Transceiver with integrated Voltage Regulator Static Characteristics (continued) Parameter Symbol Condition Min Typ 1.05 1.16 Max Unit Comparator SI, SO Threshold low SI VIL Threshold High SI VIH Hysteresis VHYS Output voltage low at SO VOL Pull-up current at SO 1.21 V 1.4 30 V mV IOUT = 1 mA, VS > 5.5 V 0.8 V 10 k Ω SO to VCC, VCC > 3.3V 0.4 V -250 µA Ipu -500 -375 Threshold low VTRL 0.15 0.25 Threshold high VTRH Input VTR VCC 0.75 0.85 VCC 160 230 300 µA -300 -230 -160 µA 3.0 3.15 3.3 V Ipu -500 -375 -250 µA Pull-down current SEN/STA IpdSEN 250 375 500 µA Pull-up current SEN/STA IpuSEN -500 -375 -250 µA 0.25 VCC Output current low IOL VCC > 3.3 V Output current high IOH K-Bus-Interface Power-on-reset threshold Pull-up current TxD VPOR Input voltage low TxD, SEN/STA VIL Input voltage high TxD, SEN/STA VIH Input voltage low BUS VIL Input voltage high BUS VIH Hysteresis BUS VPOR =VRES1 0.75 0.45 0.55 VHYS 400 0 ≤ VBUS ≤ 40 V RINBUS VBUS = -25V TA ≤ 125 °C Output voltage BUS VBUS 1500 1.2 VS = 12V, SENSE = low IOUT = 25 mA 1.0 ILIM VBUS > 2.5V Output voltage low RxD VOL IOUT = 1 mA Output voltage high RxD VOH IOUT = -1mA Page 9 kΩ 60 VS = 12V, SENSE = low IOUT = 40 mA Current limitation BUS 3901003122 Rev 004 600 mV 1300 TA ≤ 125 °C VS VS 50 0 ≤ VBUS ≤ 40 V Input restistance BUS VCC V 40 VCC-0.8 100 mA 0.8 V V Dec/04 TH3122 K-Bus Transceiver with integrated Voltage Regulator Dynamic Characteristics (5.25V ≤ VS ≤ 16V, 4.75V ≤ VCC ≤ 5.25V, -40°C ≤ TA ≤ 125°C, unless otherwise specified) Parameter Symbol Condition Min Typ Max Unit RVTR < 1 k Ω 70 100 140 ms RVTR > 45 k Ω 10 15 20 ms trr 3.0 6.5 10 µs Slew rate BUS falling edge dV/dTfall -2.2 -1.6 -1.0 Slew rate BUS rising edge dV/dTrise 1.0 1.6 2.2 Symmetry of Slew rate BUS dV/dTsym RESET Reset time Reset rising time tRes K-Bus-Interface V/µs 0.3 V/µ s 4.0 µs Debouncing time BUS tdebBUS Symmetry of debouncing BUS tdebsym 0.5 µs Propagation delay TxD -> RxD tpd 20 µs Symmetry of propagation delay TxD -> RxD tpdsym 3.5 µs High pulse or low pulse 1.5 2.8 Bit compare time BUS, SENSE, TxD tbc 35 52 70 µs Recovery time BUS, TxD trec 30 50 75 µs Inhibit time for transmit BUS, TxD tena 0.92 1.33 1.8 ms Constant low switch off BUS, TxD tlow 3 6 12 ms Oscillator frequency fOSC 8 12 15 kHz Debouncing time TxD tdeb 0.6 1.0 1.5 µs Debouncing time EN tdeb 200 Wake-up debouncing BUS tdebWake 25 Propagation delay SI -> SO tpdcomp 4 tdeb 10 Debouncing VS-SENSE 3901003122 Rev 004 Page 10 ns 45 17 90 µs 11 µs 25 µs Dec/04 TH3122 K-Bus Transceiver with integrated Voltage Regulator Pin Description Pin Name VS 1 16 VCC EN 2 15 SENSE VTR 3 14 RESET GND 4 13 GND GND 5 12 GND BUS 6 11 TxD SI 7 10 RxD SO 8 9 SEN/STA TH3122 I/O Function 1 VS 2 EN I Enable Input voltage regulator, HV-pull-down-Input, High-active 3 VTR I Analogue Input - definition of reset time und Reset voltage level 4 GND Ground 5 GND Ground 6 BUS I/O 7 SI I Comparator Input, HV-Input 8 SO O 5V-Comparator Output 9 SEN/STA I/O Send status 10 RxD O Receive Output, 5V-push-pull 11 TxD I 5V-Transmit Input, pull-up-Input 12 GND Ground 13 GND Ground 14 RESET O 5V-output reset, active low 15 SENSE O 5V-output of VS-Monitoring 16 VCC O Regulator output 5V/100mA 3901003122 Rev 004 Supply voltage Bi-directional bus line Page 11 Dec/04 TH3122 K-Bus Transceiver with integrated Voltage Regulator Mechanical Specifications DF (SOIC16) Package Dimensions E H A1 A 1 2 3 D α L b e Small Outline Integrated Circiut (SOIC), DF (SOIC 16, 300 mil) All Dimension in mm, coplanarity < 0.1 mm D E H A A1 min 10.1 7.40 10.00 2.35 0.10 max 10.5 7.60 10.65 2.65 0.30 e 1.27 b L α 0.33 0.40 0° 0.51 1.27 8° 0.013 0.016 0° 0.020 0.050 8° All Dimension in inch, coplanarity < 0.004” min 0.398 0.291 0.394 0.093 0.004 max 0.413 0.299 0.419 0.104 0.012 3901003122 Rev 004 Page 12 0.050 Dec/04 TH3122 K-Bus Transceiver with integrated Voltage Regulator Assembly Information This Melexis device is classified and qualified regarding soldering technology, solderability and moisture sensitivity level, as defined in this specification, according to following test methods: IPC/JEDEC J-STD-020 Moisture/Reflow Sensitivity Classification For Nonhermetic Solid State Surface Mount Devices (classification reflow profiles according to table 5-2) EIA/JEDEC JESD22-A113 Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing (reflow profiles according to table 2) CECC00802 Standard Method For The Specification of Surface Mounting Components (SMDs) of Assessed Quality EIA/JEDEC JESD22-B106 Resistance to soldering temperature for through-hole mounted devices EN60749-15 Resistance to soldering temperature for through-hole mounted devices MIL 883 Method 2003 / EIA/JEDEC JESD22-B102 Solderability For all soldering technologies deviating from above mentioned standard conditions (regarding peak temperature, temperature gradient, temperature profile etc) additional classification and qualification tests have to be agreed upon with Melexis. The application of Wave Soldering for SMD’s is allowed only after consulting Melexis regarding assurance of adhesive strength between device and board. Based on Melexis commitment to environmental responsibility, European legislation (Directive on the Restriction of the Use of Certain Hazardous substances, RoHS) and customer requests, Melexis has installed a roadmap to qualify their package families for lead free processes also. Various lead free generic qualifications are running, current results on request. For more information on Melexis lead free statement http://www.melexis.com/html/pdf/MLXleadfree-statement.pdf see quality page at our website: ESD Precautions Electronic semiconductor products are sensitive to Electro Static Discharge (ESD). Always observe Electro Static Discharge control procedures whenever handling semiconductor products. 3901003122 Rev 004 Page 13 Dec/04 TH3122 K-Bus Transceiver with integrated Voltage Regulator Disclaimer Devices sold by Melexis are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. Melexis makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Melexis reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with Melexis for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by Melexis for each application. The information furnished by Melexis is believed to be correct and accurate. However, Melexis shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of Melexis’ rendering of technical or other services. © 2002 Melexis NV. All rights reserved. For the latest version of this document, go to our website at: www.melexis.com Or for additional information contact Melexis Direct: Europe and Japan: All other locations: Phone: +32 13 67 04 95 E-mail: [email protected] Phone: +1 603 223 2362 E-mail: [email protected] ISO/TS 16949 and ISO14001 Certified 3901003122 Rev 004 Page 14 Dec/04