MELEXIS TH8061KDCA

TH8061
Voltage Regulator with integrated LIN Transceiver
Features
o
Compatible to LIN Specification 1.3, 2.0 and SAE J2602
o
Operating voltage VS = 5.5 ... 18 V
o
Low standby current consumption of < 50 µA in sleep mode
o
Linear low drop voltage regulator 5V/50mA
ƒ
o
Output current limitation
LIN-Bus Transceiver
ƒ
Compatible to ISO9141 functions
ƒ
Baud rate up to 20 kBaud
ƒ
Slew rate control for best EME behavior
ƒ
High EMI immunity
ƒ
High signal symmetry for using in RC – based slave nodes up to 2% clock tolerance
o
Wake-up via LIN bus traffic
o
Reset output (100ms/4.65V)
o
Overtemperature shutdown
o
Automotive Temperature Range of –40°C to 125°C
o
CMOS compatible interface to microcontroller
o
Load dump protected (40V)
o
Small SOIC8 package
Ordering Information
Part No.
Temperature Range
Package
Revision
TH8061 KDC A
K (-40 to 125 °C)
DC (SOIC8)
A
General Description
The TH8061 consists of a low-drop voltage regulator 5V/50mA and a LIN bus transceiver. The LIN
transceiver is suitable for LIN bus systems conform to LIN specification revision 1.3, 2.0 and SAE J2602.
The combination of voltage regulator and bus transceiver makes it possible to develop simple, but powerful
and cheap slave nodes in LIN Bus systems.
TH8061 – Datasheet
3901008061
Page 1 of 36
June 2004
Rev 007
TH8061
Voltage Regulator with integrated LIN Transceiver
Contents
1.
Functional Diagram ............................................................................................................................... 4
2.
Electrical Specification.......................................................................................................................... 5
2.1
Operating Conditions........................................................................................................................ 5
2.2
Absolute Maximum Ratings ............................................................................................................. 5
2.3
Static Characteristics........................................................................................................................ 6
2.4
Dynamic Characteristics................................................................................................................... 8
2.5
Timing Diagrams .............................................................................................................................. 9
2.6
Test Circuit for Dynamic and Static Characteristics....................................................................... 11
3.
Functional Description ........................................................................................................................ 13
3.1
Operating Modes............................................................................................................................ 13
3.2
Initialization..................................................................................................................................... 14
3.3
Wake-Up ........................................................................................................................................ 15
3.4
VSUP under voltage reset.............................................................................................................. 16
3.5
Overtemperature Shutdown ........................................................................................................... 16
3.6
LIN BUS Transceiver...................................................................................................................... 17
3.7
Linear Regulator............................................................................................................................. 19
3.8
RESET ........................................................................................................................................... 19
3.9
Mode Input EN ............................................................................................................................... 20
4.
Application Hints ................................................................................................................................. 22
4.1
Power Dissipation and operating range ......................................................................................... 22
4.2
Low Dropout Regulator .................................................................................................................. 23
4.3
Application Circuitry........................................................................................................................ 25
4.4
EMI Supressing .............................................................................................................................. 25
4.5
Connection to Flash-MCU .............................................................................................................. 27
5.
Operating during Disturbance............................................................................................................ 28
5.1
Operating without VSUP or GND ................................................................................................... 28
5.2
Short Circuit BUS against VBAT .................................................................................................... 28
5.3
Short Circuit BUS against GND ..................................................................................................... 28
5.4
Short Circuit TxD against GND ...................................................................................................... 28
5.5
TxD open........................................................................................................................................ 28
5.6
Short Circuit VCC against GND ..................................................................................................... 28
5.7
Overload of VCC ............................................................................................................................ 28
5.8
Undervoltage VSUP, VCC ............................................................................................................. 28
5.9
Short circuit RxD, RESET against GND or VCC............................................................................ 28
6.
PIN Description .................................................................................................................................... 29
7.
Mechanical Specification .................................................................................................................... 30
8.
8.1
8.2
Tape and Reel Specification ............................................................................................................... 31
Tape Specification.......................................................................................................................... 31
Reel Specification........................................................................................................................... 32
9.1
9.2
9.3
ESD/EMC Remarks .............................................................................................................................. 33
General Remarks ........................................................................................................................... 33
ESD-Test........................................................................................................................................ 33
EMC................................................................................................................................................ 33
9.
10.
Revision History................................................................................................................................... 34
11.
Assembly Information ......................................................................................................................... 35
12.
Disclaimer............................................................................................................................................. 35
TH8061 – Datasheet
3901008061
Page 2 of 36
June 2004
Rev 007
TH8061
Voltage Regulator with integrated LIN Transceiver
List of Figures
Figure 1- Block diagram........................................................................................................................... 4
Figure 2 - Timing diagram for propagation delay acc. to LIN 1.3 and 2.0 ............................................... 9
Figure 3 - Timing diagram for slope times acc. to LIN 1.3..................................................................... 10
Figure 4 - Timing diagram for duty cycle acc. to LIN 2.0....................................................................... 10
Figure 5 - Test circuit for delay-, slope times and duty cycles............................................................... 11
Figure 6 - Test circuit for supply current ISnl........................................................................................... 11
Figure 7 - Test circuit for bus voltage “recessiv” VBUSrec ........................................................................ 11
Figure 8 - Test circuit for bus voltage “dominant” VBUSdom ..................................................................... 12
Figure 9 - Test circuit for bus current “recessiv” IINBUSR ......................................................................... 12
Figure 10 - State diagram of operating modes...................................................................................... 13
Figure 11 - Operating of power-on and under-voltage reset ................................................................. 15
Figure 12 - Receive mode impulse diagram.......................................................................................... 17
Figure 13 - TxD input circuitry ............................................................................................................... 18
Figure 14 - RxD output circuitry............................................................................................................. 18
Figure 15 - Characteristic of current limitation VCC = f(IVCC)................................................................. 19
Figure 16 - Reset behaviour .................................................................................................................. 19
Figure 17 - Output current of reset output vs. VCC voltage .................................................................. 20
Figure 18 - EN input circuitry ................................................................................................................. 20
Figure 19 - RIN characteristics of EN-input ............................................................................................ 21
Figure 20 - EN controlled via MCU........................................................................................................ 21
Figure 21 - Permanent normal mode..................................................................................................... 21
Figure 22 - Power dissipation LIN transceiver @ 20kbit ....................................................................... 22
Figure 23 - Save operating area............................................................................................................ 23
Figure 24 - ESR Curves for 6.8µF ≤ CL ≤ 100µF and Frequency of 100kHz ........................................ 24
Figure 25 - Application circuit (slave node) ........................................................................................... 25
Figure 26 - Application circuit for LIN subbus with TH8061 as slave node ........................................... 26
Figure 27 – Example circuitry for connection of RxD to MCU for flash programming........................... 27
TH8061 – Datasheet
3901008061
Page 3 of 36
June 2004
Rev 007
TH8061
Voltage Regulator with integrated LIN Transceiver
1. Functional Diagram
VSUP
VCC
Control
Amplifier
Aux.
Supply
VBG
Bandgap
MR
Current
Limitation
Reset
Generator
Vaux
POR
4.65 V
Adjustment
UVR
Mode
Control
EN
Temp.
Protection
VSS
Wake-up
Control
TSHD
RESET
Reset
Timer
Osc
WakeFilter
VSUP
VCC
VSUP
VCC
Rec-Filter
RxD
Receiver
VCC
30k
BUS
TSHD
Driver
control
Filter
TxD
MR
Figure 1 - Block diagram
TH8061 – Datasheet
3901008061
Page 4 of 36
June 2004
Rev 007
TH8061
Voltage Regulator with integrated LIN Transceiver
2. Electrical Specification
All voltages are referenced to ground (GND). Positive currents flow into the IC.
The absolute maximum ratings (in accordance with IEC 134) given in the table below are limiting values that
do not lead to a permanent damage of the device but exceeding any of these limits may do so. Long term
exposure to limiting values may affect the reliability of the device. Correct operating of the device cannot be
guaranteed if any of these limits are exceeded.
2.1 Operating Conditions
Parameter
Symbol
Min
Max
Unit
Supply voltage
VSUP
5.25
18
V
Output voltage
VCC
4.95
5.05
V
Operating ambient temperature
TA
-40
+125
°C
Junction temperature
TJ
+150
°C
2.2 Absolute Maximum Ratings
Parameter
Supply voltage at VSUP [1]
Input voltage at pin BUS [1]
Symbol
Condition
VSUP
VBUS
Min
Max
-1.0
18
T ≤ 60 s
-
30
T ≤ 500 ms
-
40
-24
30
-
40
T ≤ 500 ms
Unit
V
V
Difference VSUP-VCC
VSUP-VCC
-0.3
40
V
Input voltage at pin EN
VINEN
-0.3
VSUP+0.3
V
Input voltage at pin TxD, RxD, RESET
VIN
-0.3
VCC+0.3
V
Input current at pin EN, TxD, RxD, RESET
IIN
-25
25
mA
IINSH
-500
500
mA
-2
2
kV
Input current for short circuit of pin VSUP and VCC
ESD Capability on any pin
Power dissipation
Thermal resistance from junction to ambient(SOIC8)
Junction temperature [2]
Storage temperature
[1]
[2]
ESDHB
Human body Modell, 100pF
via 1.5kΩ
P0
Internal limited [2]
RTHJA
160
K/W
TJ
150
°C
150
°C
TSTG
-55
The voltage values are valid independent from each other.
See chapter 4.1 Power Dissipation and operating range
TH8061 – Datasheet
3901008061
Page 5 of 36
June 2004
Rev 007
TH8061
Voltage Regulator with integrated LIN Transceiver
2.3 Static Characteristics
Unless otherwise specified all values in the following tables are valid for VSUP = 5.25 to 18V and
TAMB = -40 to 125oC. All voltages are referenced to ground (GND), positive currents flow into the IC.
Parameter
Symbol
Condition
Min
Typ
Max
Unit
5.25
12
18
V
110
µA
35
50
µA
VSUP
Operating voltage
VSUP
ISnl
VEN = VSUP = 12V,
VBUS > VSUP-0.5V,
Pins 4 to 8 open
Supply current, „sleep mode“
ISsleep
VSUP = 12V,
VEN = 0V,
VBUS > VSUP-0.5V
VSUP under voltage reset “off”
VSUVR_OFF
VSUP ramp up
3.1
3.5
3.9
V
VSUP under voltage reset “on”
VSUVR_ON
VSUP ramp down
2.7
3.0
3.3
V
VSUP under voltage reset hysteresis
VSUVR_HYS
VSUVR_OFF - VSUVR_ON
0.2
Supply current, VCC „noload“ [3]
V
VCC
Output voltage VCC
VCCn
5.5V ≤ VSUP ≤ 18V
TA = 25°C
4.95
5.0
5.05
V
VCCt
5.5V ≤ VSUP ≤ 18V
4.90
5.0
5.10
V
VCCh
VSUP > 18V
4.90
5.0
5.25
V
VCCI
3.3 V< VSUP< 5.5 V
5.1
V
IVCC = 20mA
150
mV
IVCC = 50mA
500
mV
VSUP-VD
Drop-out voltage [4]
VD
Output current VCC
IVCC
VSUP ≥ 3.0V
Current limitation VCC
ILVCC
VSUP > 0V
Load capacity [5]
Cload
See chapter 4.2 Low Dropout
Regulator
4.7
Reset threshold
VRES
refered to VCC, VSUP > 4.6V
4.5
4.65
4.8
V
Master reset threshold (internal signal) [1]
VMRes
3.0
3.15
3.3
V
50
mA
150
mA
µF
Enable Input EN
Input voltage low
VENL
-0.3
1.6
V
Input voltage high
VENH
2.5
VSUP +0.3
V
VENHYS
100
Hysteresis [1]
Pull-down current EN
TH8061 – Datasheet
3901008061
IpdEN
mV
VEN > VENH
1.0
4.0
7.0
µA
VEN < VENL
70
100
130
µA
Page 6 of 36
June 2004
Rev 007
TH8061
Voltage Regulator with integrated LIN Transceiver
Parameter
Symbol
Condition
Min
Typ
Max
Unit
IOUT = 1 mA, VSUP > 5.5 V
0.8
V
10 kΩ RESET to VCC
VSUP = VCC = 0.8 V
0.2
V
-250
µA
Output RESET
Output voltage low
VOL
Pull-up current
Ipu
-500
-375
LIN BUS Interface
Receive threshold
Vthr_rec,
Vthr_dom
Center point of receive threshold
Vthr_cnt = (Vthr_rec+Vthr_dom)/2
Vthr_cnt
Hysteresis of receive threshold
Vthr_hys = Vthr_rec-Vthr_dom
Vthr_hys
Input current BUS (recessive) [3]
IINBUSR
8.0 ≤ VBUS ≤ 18 V,
VSUP= VBUS - 0.7V, TxD = 5V
Input current BUS (recessive)
-IINBUSR
VSUP= 0V, VBUS =- 12V
Pull up resistor bus
RBUSpu
Output voltage BUS (dominant) [3]
VBUSdom
7.0 ≤ VSUP ≤ 18 V,
TxD = 0V, RL = 500Ω
Output voltage BUS (recessive) [2] [3]
VBUSrec
7.0 ≤ VSUP ≤ 18 V, TxD = 5V
Current limitation BUS
ILIM
0.4* VSUP
7.0 V ≤ VSUP ≤ 18 V
0.475*
VSUP
0.5*
VSUP
0.525*
VSUP
0.12*
VSUP
0.135*
VSUP
0.15*
VSUP
20
-1
20
VBUS > 2.5V, TxD = 0V
0.6* VSUP
V
µA
mA
30
47
kΩ
1.2
V
0.8*VSUP
V
40
120
mA
21
kΩ
0.25
VCC
Input TxD
Pull-up resistor
Rpu_TxD
Input low level TxD
VIL
Input high level TxD
VIH
VIN = 0V
9.5
15
VCC
0.75
Output RxD
Output voltage Low RxD
VOL
IOUT = 1 mA
Output voltage High RxD
VOH
IOUT = -1 mA
0.8
VCC - 0.3
V
V
Thermal Protection
Thermal shutdown [1]
TJSHD
155
175
°C
Thermal recovery [1]
TJREC
126
150
°C
[1]
[2]
[3]
[4]
[5]
No production test, guaranteed by design and qualification
The recessive voltage at pin BUS should be less than 80% of the voltage at VBAT. The voltage at VSUP results with consideration
of reverse diode VSUP = VBAT - 0,7V
See chapter 2.6 Test Circuit for Dynamic and Static Characteristics
The nominal VCC voltage is measured at VSUP =12V. If the VCC voltage is 100mV below its nominal value then the voltage drop is
VD = VSUP – VCC.
See chapter 4 for application hints.
TH8061 – Datasheet
3901008061
Page 7 of 36
June 2004
Rev 007
TH8061
Voltage Regulator with integrated LIN Transceiver
2.4 Dynamic Characteristics
7V ≤ VSUP ≤ 18V, -40°C ≤ TA ≤ 125°C, unless otherwise specified
Parameter
Symbol
Condition
Min
Typ
Max
Unit
tRes
70
100
140
ms
trr
3.0
7.5
15
µs
Debouncing time BUS [1]
tdeb_BUS
1.5
2.8
4.0
µs
Wake up time
twake_BUS
25
60
120
µs
4
µs
2
µs
6
µs
2
µs
RESET
Reset time
Reset rising time [1]
General LIN BUS parameter
tdr_TXD,
tdf_TXD
RL/CL at BUS
1kΩ/1nF
660Ω/6.8nF
500Ω/10nF
tdsym_TXD
tdr_TXD - tdf_TXD
tdr_RXD
tdf_RXD
CL(RXD) = 50pF
tdsym_RXD
tdr_RXD - tdf_RXD
-2
Slew rate BUS rising edge [1]
dV/dTrise
20% ≤ VBUS ≤ 80%
CBUS = 100 pF
1.0
1.7
2.5
V/µs
Slew rate BUS falling edge [1]
dV/dTfall
20% ≤ VBUS ≤ 80%
100pF ≤ CBUS ≤ 10nF
-2.5
-1.7
-1.0
V/µs
Transmit propagation delay
TxD -> BUS [2] [3]
Symmetry of propagation delay
BUS -> RxD [2]
Receiver propagation delay
BUS -> RxD [2] [3]
Symmetry of propagation delay
TxD -> BUS [2]
-2
LIN BUS parameter according to LIN Spec. Rev. 1.3
Slope time, transition from recessive to
dominant [2] [3]
tsdom
Slope time, transition from dominant to
recessive [2] [3]
tsrec
Slope time symmetry
TH8061 – Datasheet
3901008061
tssym
VSUP = 8 V
RL= 500Ω / CL=10nF
VSUP = 18 V
RL= 500Ω / CL=10nF
VSUP = 8 V
RL= 500Ω / CL=10nF
VSUP = 18 V
RL= 500Ω / CL=10nF
VSUP = 8 V
RL= 500Ω / CL=10nF
Tssym = tsdom - tsrec
VSUP = 18 V
RL= 500Ω / CL=10nF
Tssym = tsdom - tsrec
Page 8 of 36
12
µs
18
12
µs
18
-7
1
µs
-5
5
June 2004
Rev 007
TH8061
Voltage Regulator with integrated LIN Transceiver
Parameter
Symbol
Condition
Min
Typ
Max
Unit
LIN BUS parameter according to LIN Spec. Rev. 2.0
Conditions:
VSUP =7.0V to 18V; BUS loads: 1kΩ/1nF;660Ω/6.8nF;500Ω/10nF
TxD signal: tBit = 50µs, twH = TwL = tBit; trise = tfall < 100ns
Minimal recessive bit time [2] [3]
trec(min)
40
50
58
µs
Maximum recessive bit time [2] [3]
trec(max)
40
50
58
µs
Dyty cycle 1
D1
D1 = trec(min) / (2*tBit)
Dyty cycle 2
D2
D2 = trec(max) / (2*tBit)
[1]
[2]
[3]
0.396
0.581
No production test, guaranteed by design and qualification
See chapter 2.5 Timing Diagrams
See chapter 2.6 Test Circuit for Dynamic and Static Characteristics
2.5 Timing Diagrams
50%
TxD
tdf_TXD
tdr_TXD
VBUS
100%
95%
BUS
50%
50%
5%
0%
tdf_RXD
RxD
tdr_RXD
50%
Figure 2 - Timing diagram for propagation delay acc. to LIN 1.3 and 2.0
TH8061 – Datasheet
3901008061
Page 9 of 36
June 2004
Rev 007
TH8061
Voltage Regulator with integrated LIN Transceiver
VBUS
100%
95%
60%
BUS
40%
5%
Vdom
0%
tsrec
tsdom
Figure 3 - Timing diagram for slope times acc. to LIN 1.3
tBit
tBit
TxD
tdom(max)
VSUP
trec(min)
100%
74.4%
tdom(min)
58.1%
BUS
58.1%
42.2%
28.4%
VSS
trec(max)
28.4%
0%
RxD
Figure 4 - Timing diagram for duty cycle acc. to LIN 2.0
TH8061 – Datasheet
3901008061
Page 10 of 36
June 2004
Rev 007
TH8061
Voltage Regulator with integrated LIN Transceiver
2.6 Test Circuit for Dynamic and Static Characteristics
VSUP
TH8061
VSUP
EN
VCC
RESET
GND
BUS
RL
10u
100n
TxD
RxD
50p
CL
Figure 5 - Test circuit for delay-, slope times and duty cycles
12V
IS1
TH8061
VSUP
EN
VCC
RESET
GND
BUS
10u
100n
TxD
RxD
Figure 6 - Test circuit for supply current ISnl
TH8061
VBAT
VSUP
VBUSR
EN
GND
BUS
VCC
RESET
10u
100n
TxD
RxD
Figure 7 - Test circuit for bus voltage “recessiv” VBUSrec
TH8061 – Datasheet
3901008061
Page 11 of 36
June 2004
Rev 007
TH8061
Voltage Regulator with integrated LIN Transceiver
VSUP
TH8061
VSUP
VCC
EN
500
VBUSD
RESET
GND
BUS
10u
100n
TxD
RxD
Figure 8 - Test circuit for bus voltage “dominant” VBUSdom
TH8061
VBAT
VSUP
EN
VCC
RESET
GND
BUS
10u
100n
TxD
RxD
IINBUSR
Figure 9 - Test circuit for bus current “recessiv” IINBUSR
TH8061 – Datasheet
3901008061
Page 12 of 36
June 2004
Rev 007
TH8061
Voltage Regulator with integrated LIN Transceiver
3. Functional Description
The TH8061 consists of a low drop voltage regulator 5V/50mA and a LIN bus transceiver, which is a bidirectional bus interface for data transfer between LIN bus and the LIN protocol controller.
Additionally integrated is a RESET output with a reset delay of 100ms and a fixed threshold of 4.65V.
3.1 Operating Modes
The TH8061 provides two main operating modes “normal” and “sleep” and the intermediate states “POR”,
“Ini-state” and “thermal shutdown”. The main modes are fixed states defined by basic actions (VSUP start,
EN or wake-up). The intermediate states are soft states. They aren’t defined by logical actions but by
changes of voltage (VSUP, VCC) or junction temperature.
VSUP power on
clear all state-FF
clear reset timer
Regulator On -> VCC ramp up
RESET = L
Wake-up disabled
VSUP > UVR_OFF
POR
Ini-state
VSUP < UVR_ON
VCC > VRES (4.65V)
VSUP < UVR_ON
EN=H
VCC < VRES
NormalMode
VSUP > UVR_OFF &
(EN= L/H or BUS Wake-up)
Regulator on
RESET = L after 100ms
RESET=H
Wake-up disabled
LIN-Transceiver on
EN= H/L
EN=L
normal mode &
TJ < TJREC
SleepMode
Regulator off
Wake-up enabled (LIN-Receiver on)
LIN-Transmitter off
normal mode &
TJ > TJSHD
sleep mode &
TJ < TJREC
sleep mode &
TJ > TJSHD
thermal
shutdown
Regulator off
Wake-up disabled
LIN-Transceiver off
TJ > TJREC
Figure 10 - State diagram of operating modes
TH8061 – Datasheet
3901008061
Page 13 of 36
June 2004
Rev 007
TH8061
Voltage Regulator with integrated LIN Transceiver
Normal Mode
The whole TH8061 is active. Switching to normal mode can be done via the following actions:
- Start of VSUP or after under voltage reset
- Rising edge at EN (EN=high)
(local wake-up)
- Activity on the LIN bus
(remote wake-up)
Sleep Mode
Sleep mode is most current saving. With a falling edge on EN (EN=low) the TH8061 is switched from normal
mode into sleep mode. The voltage regulator will be switched off and the LIN transceiver is in recessive
state.
Switching into sleep mode can be done independently from the current transceiver state. That means if the
transmitter is in dominant state this state will be cancelled and it will be switched to recessive state.
POR-state
This is the power-on-reset state of the TH8061, while Vsup < VSUVR_OFF. If the prior state was sleep mode,
the TH8061 switches via the ini-state to normal mode.
Ini-state
This is an intermediate state, which will pass through after switch on of VSUP or VCC. The TH8061 remains
in this state if VCC is below VRES (Reset output = L) and Vsup > VSUVR_ON.
Thermal Shutdown
If the junction temperature TJ is higher than TJSHD (>155°C), the TH8061 will be switched into the thermal
shutdown mode. The behaviour within this mode is comparable with the sleep mode except for LIN
transceiver operating. The transceiver is completely disabled, no wake-up functionality is available.
If TJ falls below the thermal recovery temperature TJREC (typ. 140°C) the TH8061 will be recover to the
previous state (normal or sleep).
3.2 Initialization
Initialization is started if the power supply is switched on as well as every rising edge on of the TH8061 via
the EN pin.
VSUP- Power-ON
If VSUP is switched on the TH8061 starts to normal mode via the POR- and Ini-state. A combination of
dynamic POR and under voltage reset circuitry generates a POR signal, which switches the TH8061 into
normal mode. This power on behaviour is independent from the status of the EN-pin.
Power-on reset and under-voltage reset operates independent from each other, which secures the
independence from the rise time of VSUP. During fast VSUP edges the power-on reset will be active. If the
increasing of VSUP is very slow (> 1ms/V) the under voltage reset unit initializes the voltage regulator if
VSUP > VSUVR_OFF (typ. 3.5V).
The effects of both POR circuits at different VSUP slopes will shown in Figure 11.
TH8061 – Datasheet
3901008061
Page 14 of 36
June 2004
Rev 007
TH8061
Voltage Regulator with integrated LIN Transceiver
VSUP
VSUVR_OFF
VSUVR_ON
UVR
POR
POR
UVR
EN=H/L
VCC
normal mode
sleep mode
normal mode
Figure 11 - Operating of power-on and under-voltage reset
After POR the voltage regulator starts and VCC will be output. If VCC>VMRes the bus interface will be
activated. If the VCC voltage level is higher than VRES, the reset time tRes = 100ms is started. After tRes the
RESET output switches from low to high (see Figure 16).
Start of Linear Regulator via Wake-up
The initialization is only being done for the VCC circuitry parts. This procedure begins with leaving the master
reset state (VCC > VMRes) and runs in the same manner as the VSUP-Power-On.
3.3 Wake-Up
If the regulator is put into sleep mode it can be wake up with the BUS interface. Every pulse on the BUS
(high pulse or low pulse) with a pulse width of min. 60µs switches on the regulator.
After the BUS has wake up the regulator, it can only be switched off with a high level followed by a low level
on the EN pin.
TH8061 – Datasheet
3901008061
Page 15 of 36
June 2004
Rev 007
TH8061
Voltage Regulator with integrated LIN Transceiver
3.4 VSUP under voltage reset
The under voltage detection unit inhibit an undefined behaviour of the TH8061 under low voltage condition. If
VSUP drops below VSUVR_ON (typ. 3V) the under voltage detection becomes active and the IC will be
switched to POR state. The following increasing of VSUP above VSUVR_OFF (typ. 3.5V) cancels this POR state
and the voltage regulator starts with the initialization sequence.
VSUP under voltage in Normal Mode
Supply Voltages below VSUVR_OFF don’t influence the voltage regulator. The output voltage Vcc follows VSUP.
VSUP under voltage in Sleep Mode
No exit from the sleep mode will take place if the VSUP voltage drops down to VSUVR_ON (typ. 3V). The under
voltage reset becomes active (POR-state). As a result of this operating, the sleep mode is left to the normal
mode. If VSUP rises again above VSUVR_OFF (typ. 3.5V) the IC initialize the voltage regulator and continue to
work with the normal mode.
The under voltage reset unit secures stable operating in the under voltage range of VSUP down to GND
level. The dynamic Power-On-Reset secures a defined internal state independent from the duration of the
VSUP drop, which secures a stable restart.
3.5 Overtemperature Shutdown
If the junction temperature is 155°C < TJ < 170°C the over-temperature recognition will be activated and the
regulator voltage will be switched off. The VCC voltage drops down, the reset state is entered and the bustransceiver is switched off (recessive state).
After TJ falls below 140°C the TH8061 will be initialized again (see Figure 16) independently from the voltage
levels on EN and BUS. Within the thermal shutdown mode the transceiver can’t be switched to the normal
mode neither with local nor with remote wake-up.
The operation of the TH8061 is possible between TAmax (125°C) and the switch off temperature, but small
parameter differences can appear.
After over-temperature switch-off the IC behaves as described in chapter 3.8 RESET.
TH8061 – Datasheet
3901008061
Page 16 of 36
June 2004
Rev 007
TH8061
Voltage Regulator with integrated LIN Transceiver
3.6 LIN BUS Transceiver
The TH8061 is a bi-directional bus interface device for data transfer between LIN bus and the LIN protocol
controller.
The transceiver consists of a pnp-driver (1.2V@40mA) with slew rate control, wave shaping and current
limitation and a receiver with high voltage comparator followed by a debouncing unit.
Transmit Mode
During transmission the data at the pin TxD will be transferred to the BUS driver to generate a bus signal. To
minimize the electromagnetic emission of the bus line, the BUS driver has an integrated slew rate control
and wave shaping unit.
Transmitting will be interrupted in the following cases:
- Sleep mode
- Thermal Shutdown active
- Master Reset (VCC < 3.15V)
The recessive BUS level is generated from the integrated 30k pull up resistor in serial with an active diode
This diode prevents the reverse current of VBUS during differential voltage between VSUP and BUS
(VBUS>VSUP).
No additional termination resistor is necessary to use the TH8061 in LIN slave nodes. If this IC is used for
LIN master nodes it is necessary that the BUS pin is terminated via an external 1kΩ resistor in series with a
diode to VBAT.
Receive Mode
The data signals from the BUS pin will be transferred continuously to the pin RxD. Short spikes on the bus
signal are suppressed by the implemented debouncing circuit (τ = 2.8µs).
VSUP
60%
BUS
Vthr_max
Vthr_hys
50%
40%
Vthr_cnt
Vthr_min
t < tdeb_BUS
t < tdeb_BUS
RxD
Figure 12 - Receive mode impulse diagram
The receive threshold values Vthr_max and Vthr_min are symmetrical to the centre voltage of 0.5*VSUP with a
hysteresis of 0.135*VSUP. Including all tolerances the LIN specific receive threshold values of 0.4*VSUP and
0.6*VSUP will be securely observed.
Datarate
The TH8061 is a constant slew rate transceiver which means that the bus driver works with a fixed slew
rate range of 1.0 V/µs ≤ ∆V/∆T ≤ 2.5V/µs. This principle secures a very good symmetry of the slope times
between recessive to dominant and dominant to recessive slopes within the LIN bus load range (CBUS, Rterm).
The TH8061 guarantees data rates up to 20kbit within the complete bus load range under worst case
conditions. The constant slew rate principle is very robust against voltage drops and can operate with RCoscillator systems with a clock tolerance up to ±2% between 2 nodes.
TH8061 – Datasheet
3901008061
Page 17 of 36
June 2004
Rev 007
TH8061
Voltage Regulator with integrated LIN Transceiver
Input TxD
The 5V input TxD controls directly the BUS level:
TxD = low
TxD = high
->
->
BUS = low (dominant level)
BUS = high (recessive level)
The TxD pin has an internal pull up resistor connected to VCC. This guarantees that an open TxD pin
generates a recessive BUS level.
MCU
VCC
VCC
RPU_TXD
IPU_TXD
TH8061
Typ.
15k
RC-Filter
(10ns)
TxD
Figure 13 - TxD input circuitry
Output RxD
The received BUS signal will be output to the RxD pin:
BUS < Vthr_cnt – 0.5 * Vthr_hys
BUS > Vthr_cnt + 0.5 * Vthr_hys
->
->
RxD = low
RxD = high
This output is a push-pull driver between VCC and GND with an output current of 1mA.
TH8061
MCU
VCC
RxD
Figure 14 - RxD output circuitry
TH8061 – Datasheet
3901008061
Page 18 of 36
June 2004
Rev 007
TH8061
Voltage Regulator with integrated LIN Transceiver
3.7 Linear Regulator
The TH8061 has an integrated low drop linear regulator with a p-channel-MOSFET as driving transistor. This
regulator outputs a voltage of 5V ±2% and a current of ≤50mA within an input voltage range of
5.5V ≤ VSUP ≤ 18V. The current limitation unit limits the output current for short circuits or overload to 100mA
respectively drop-down of the VCC voltage.
6
VCC [V]
5
4
3
2
1
0
0
20
40
60
80
100
120
IVCC [mA]
Figure 15 - Characteristic of current limitation VCC = f(IVCC)
3.8 RESET
The RESET pin outputs the reset state of the TH8061. This output is switched from low to high if VSUP is
switched on and VCC>VRES after the time tRes.
VSUP
T>Tj
T<Tj
t<trr
VCC
t<trr
VRES
tRes
trr
tRes
tRes
tRes
RESET
Initialisation
Thermal
shutdown
Spike VSUP
Current limitation
Low voltage
active
VSUP
Spike VCC
Figure 16 - Reset behaviour
If the voltage VCC drops below VRES then the RESET output is switched from high to low after the time trr has been
reached. For this reason short breaks of the VCC voltage and uncontrolled reset generations will be inhibited.
The circuitry of the RESET output driver guarantees, that the reset low level during decreasing of the VCC
voltage will be hold sure (s.a.Figure 17).
TH8061 – Datasheet
3901008061
Page 19 of 36
June 2004
Rev 007
TH8061
Voltage Regulator with integrated LIN Transceiver
Figure 17 - Output current of reset output vs. VCC voltage
3.9 Mode Input EN
The TH8061 is switched into the sleep mode with a falling edge and into normal mode with a rising edge at
the EN pin. The normal mode will be kept as long as EN = high.
The deactivation of TH8061 with a falling edge at EN can be done independently from the state of the bustransceiver.
VSUP
EN
4µA
Voltage
limiter
enable
96µA
Figure 18 - EN input circuitry
The maximum input voltage is VSUP. The threshold is typ. 2.1V and therefore also CMOS levels can be
used as input signal. Figure 18 shows the internal circuitry of the EN pin.
The EN input is internally pulled down to secure that if this pin is not connected a low level will be generated.
It will be used two different pull down current sources for high and low level to minimize the sleep mode
current.
The 4µA pull down current source is used if the input voltage VIN > high level voltage VENH. If the input
voltage drops below the low level of EN VENL additional the second current source is used. The resulting pull
down current in this case is 100µA.
TH8061 – Datasheet
3901008061
Page 20 of 36
June 2004
Rev 007
TH8061
Voltage Regulator with integrated LIN Transceiver
Figure 19 - RIN characteristics of EN-input
The wide input voltage range allows different EN control possibilities. If the EN input is connected to an
CMOS output of the MCU, a falling edge switches the TH8061 into sleep mode (the regulator is also
switched off). The wake up is only possible via the bus line.
MCU
TH8061
VSUP
VBAT
EN
CIN
LINBUS
VCC
+5V
RESET
GND
TxD
BUS
RxD
220p
Cload
Figure 20 - EN controlled via MCU
If the application don’t needs the wake up capability of the TH8061 a direct connection EN to VSUP is
possible. In this case the TH8061 operates in permanent normal mode. Also possible is the external (outside
of the module) control of the EN line via a VBAT signal.
MCU
TH8061
VSUP
VBAT
EN
CIN
LINBUS
VCC
+5V
RESET
GND
TxD
BUS
RxD
220p
Cload
Figure 21 - Permanent normal mode
TH8061 – Datasheet
3901008061
Page 21 of 36
June 2004
Rev 007
TH8061
Voltage Regulator with integrated LIN Transceiver
4.
Application Hints
4.1 Power Dissipation and operating range
The maximum power dissipation depends on the thermal resistance of the package and the PCB, the
temperature difference between Junction and Ambient as well as the airflow.
The power dissipation can be calculated with:
PD = (VSUP – VCC) * IVCC + PD_TX
The power dissipation of the transmitter PD_TX depends on the transceiver configuration and its parameters
as well as on the bus voltage VBUS=VBAT-VD, the resulting termination resistance RL, the capacitive bus load
CL and the bit rate. Figure 22 shows the dependence of power dissipation of the transmitter as function of
VSUP. The conditions for calculation of the power dissipation is RL=500Ω, CL=10nF, bit rate=20kbit and duty
cycle on TxD of 50%
50
45
40
35
PD [mW]
30
25
20
15
10
5
0
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
VSUP [V]
Figure 22 - Power dissipation LIN transceiver @ 20kbit
The permitted package power dissipation can be calculated:
PD max =
Tj − TA
R THJ − A
If we consider that PD_TX_max= f(VSUP) the max output current IVCC on VCC can be calculated:
Tj − TA
IV CCmax =
R THJ − A
TH8061 – Datasheet
3901008061
− PD _ TX _ max
@ VSUP
VSUP − VCC
Page 22 of 36
June 2004
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TH8061
Voltage Regulator with integrated LIN Transceiver
TJ -TA is the temperature difference between junction and ambient and Rth is the thermal resistance of the
package. The thermal energy is transferred via the package and the pins to the ambient. This transfer can be
improved with additional ground areas on the PCB as well as ground areas under the IC.
60
maximum current
50
IVCC_max [mA]
SOIC8
TA=125°C
TJ=150°C
30
max. supply voltage
SOIC8
TA=85°C
TJ=150°C
40
SOIC8
TA=85°C
TJ=125°C
20
10
0
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
VSUP [V]
Figure 23 - Save operating area
The linear regulator of the TH8061 operates with input voltages up to 18V and can output a current of 50mA.
The maximum power dissipation limits the maximum output current at high input voltages and high ambient
temperatures. The output current of 50mA at an ambient temperature of TA = 125°C is only possible with
small voltage differences between VSUP and VCC. See Figure 23 for safe operating areas for different ambient
and junction temperatures.
4.2 Low Dropout Regulator
The voltage regulator of theTH8061 is a low dropout regulator (LDO) with a p-MOSFET as driving transistor.
This kind of regulator has a standard pole, generated from the internal frequency compensation and an
additional pole, which is dependent from the load and the load capacity. This additional pole can cause an
instable behaviour of the regulator! It is required a zero point to compensate this additional pole. It can be
realised via an additional load resistor in series with a load capacity. It is used for this compensation the
equivalent series resistance (ESR) of the load capacity. Every real capacity is characterized with an ESR
value. With the help of this ESR value an additional zero point is implemented into the amplification loop and
therefore the result of the negative phase shift is compensated.
Because of this correlation the regulator has a stable operating area which is defined by the load resistance
RL, the load capacity CL and the corresponding ESR value. The load resistance resp. load current is defined
by the application itself and therefore the compensation of the pole can only be done via variation of the load
capacity and ESR value.
Input Capacity on VSUP CIN
It is necessary an input capacity of CIN ≥ 4.7µF. Higher capacity values improves the line transient response
and the supply noise rejection behaviour. The combination of electrolytic capacity (e.g.100µF) in parallel with
a ceramic RF-capacity (e.g.100nF) archives good disturbance suppressing.
The input capacity should be as closed as possible (< 1cm) placed to the VSUP pin.
TH8061 – Datasheet
3901008061
Page 23 of 36
June 2004
Rev 007
TH8061
Voltage Regulator with integrated LIN Transceiver
Load Capacity on VCC CL
The regulator is stabilized by the output capacitor CL. The TH8061 requires a minimum of 4.7µF capacity
connected to the 5V output to insure stability. This capacitor should maintain its ESR in the stable region of
the ESR curve (See Figure 24) over the full operating temperature range of the application. The capacity
value and the ESR of a capacitor changes with temperature. The minimal capacity value must be kept within
the whole operating temperature range.
ESR@100kHz [Ohm]
100
10
1
0,1
0,01
0
10
20
30
40
50
load current [mA]
Figure 24 - ESR Curves for 6.8µF ≤ CL ≤ 100µF and Frequency of 100kHz
The value and type of the output capacitor can be selected using the diagram shown in Figure 24.
Capacity Value
The capacity value of an electrolytic capacitor is dependence from the voltage, temperature and the
frequency. The temperature coefficient of the capacity value is positive, that means that the value increases
with increasing of the temperature. The capacity value decreases with increasing of the frequency. This
behavior of a capacitor can cause that at TA=-40°C the capacity value falls below the minimum required
capacity for the regulator. In this case the regulator becomes instable, which means the regulator starts
oscillation. The nominal value of the capacitor at TA=25°C have to be chosen with enough margin under
consideration of the capacitor specification. The instable behavior will be amplified because of the
decreasing of the capacity with this oscillation.
ESR
The equivalent serial resistance is the resistor part of the equivalent circuit diagram of a capacitor. The ESR
value is dependent from the temperature and frequency. Normally the specified ESR values for a capacitor is
valid at a temperature of TA=25°C and a frequency of f=100kHz.
The temperature coefficient is negative, which means with increasing of the temperature the ESR value
decreases. In the choice of the capacity has to be taken into account that the ESR can decrease at TA=-40°C
dramatically that the valid operating area can be left, which causes that the regulator will be instable.
TH8061 – Datasheet
3901008061
Page 24 of 36
June 2004
Rev 007
TH8061
Voltage Regulator with integrated LIN Transceiver
Tantalum Capacitors
This type of capacitor has a low dependence of the capacity and the ESR from the temperature and is
therefore well suitable as VCC load capacity.
Aluminum Capacitors
These capacitors show a strong influence of the capacity and the ESR from the temperature. These
characteristic restrains the usability as load capacity for the low drop regulator of TH8061.
4.3 Application Circuitry
rev.prot. diode
VBAT
CIN
100µ
100n
LINBUS
220p
CL
10µ...100µ
or
optional
10
RC-Filter
MCU
TH8061
VSUP VCC
EN RESET
GND TxD
BUS RxD
+5V
100n
Control unit
with LIN protocol
33uH
100p
LC-Filter
82p
Figure 25 - Application circuit (slave node)
4.4 EMI Supressing
To minimize the influence of EMI on the bus line a 220pF capacitor should be connected directly to the BUS
pin (see Figure 25). This EMI-Filter makes sure that the RF imissions into the IC from the BUS line have no
affect resp. will be limited.
The value of the filter capacity can be adjusted to the size of the LIN network. 220pF should be used for
bigger networks. Values from 333pF up to 1nF should be used for middle to small LIN networks. Finally the
size of the filter capacity influences the effectiveness of the EMI suppressing in observation of the maximum
LIN bus capacity of 10nF.
Alternatively to a pure C-filter it is also possible to use LC- or RC-filter. The dimension of C, L or R, L
depends on the corner frequency, the maximum LIN bus capacity (10nF) and the compliance with the DCand AC LIN bus parameters.
TH8061 – Datasheet
3901008061
Page 25 of 36
June 2004
Rev 007
TH8061
Voltage Regulator with integrated LIN Transceiver
VBAT
100n
VIN
VOUT
GND
100u
100n
+5V
100n
TH8080
1k
n.c.
VS
BUS
GND
220p
Master-Node
LIN-BUS
MCU
RxD
n.c.
VCC
TxD
100n
TH8061
100u
VSUP
EN
GND
BUS
100n
+5V
VCC
RESET
TxD
RxD
MCU
220p
100u
100n
Slave-Node
Figure 26 - Application circuit for LIN subbus with TH8061 as slave node
TH8061 – Datasheet
3901008061
Page 26 of 36
June 2004
Rev 007
TH8061
Voltage Regulator with integrated LIN Transceiver
4.5 Connection to Flash-MCU
While programming a flash MCU the TH8061 should be disconnected from the MCU. This can be done via
disconnecting the supply voltage from the TH8061 or by switching off with the EN pin. The reverse current
supply of the IC via the RxD pin, if the connected MCU pin is used as normal signal input and programming
input, must be inhibited via a decoupling diode. In this case the MCU must be supplied via the programming
interface.
Prog.-Data
10u...47u
MCU
TH8061
VCC
47n...100n
RESET
TxD
RxD
Vhigh_RxD >= 4.7V at VCC = 5V
Vlow_RxD = 0.8V
0.7V
Vhigh = 4V at VCC = 5V
Figure 27 – Example circuitry for connection of RxD to MCU for flash programming
The programming of the Flash is also possible via the LIN pin, if the MCU supports this kind of flash mode.
TH8061 – Datasheet
3901008061
Page 27 of 36
June 2004
Rev 007
TH8061
Voltage Regulator with integrated LIN Transceiver
5. Operating during Disturbance
5.1 Operating without VSUP or GND
The absence of VSUP or GND connection will not influence or disturb the communication between other bus
nodes. No reverse supply of the IC can appear if without GND or VSUP connection the BUS pin is on VBAT
level.
5.2 Short Circuit BUS against VBAT
The reaction of the IC depends on the send state of the transceiver:
- Recessive
LIN bus is blocked, no influence to the TH8061
- Dominant
Current limitation, thermal shut down of TH8061 if power dissipation will make an
overrun of TJ
5.3 Short Circuit BUS against GND
LIN bus is blocked. No influence on the TH8061.
5.4 Short Circuit TxD against GND
The LIN transceiver is permanently in the dominant state, that means the whole LIN bus. This state can only
be detected from the LIN controller. In this case the controller must switch off the LIN node via the EN input
of the TH8061. A thermal shut down of TH8061 will appear if the power dissipation and will make an overrun
of TJ.
5.5 TxD open
The internal pull-up resistor forces the LIN node to the recessive state. The communication between the
other bus-nodes will not be disturbed.
5.6 Short Circuit VCC against GND
The VCC pin is protected via a current limitation. This state is comparable with the behaviour in the sleep
mode.
5.7 Overload of VCC
Thermal switch off
The power dissipation is increasing if the load current is between IVCC_max and ILVCC. If the max junction
temperature of >155°C is reached, the IC will be switched off. The voltage regulator will also be switched off
and a reset signal is forced.
Over current
If the current limitation is active the voltage on VCC drops down. If this voltage under-runs the threshold
VRES, a reset will be forced.
5.8 Undervoltage VSUP, VCC
The reset unit ensures the correct behaviour of the driver during under-voltage. The BUS pin generates the
recessive state if VCC < VMRes. The inputs EN and TxD have pull-up and pull-down characteristics.
If VMRes ≤ VCC ≤ 4.5V the TxD signal is transmitted to the bus. The receive mode is also active.
5.9 Short circuit RxD, RESET against GND or VCC
Both outputs are short circuit proof to VCC and ground.
TH8061 – Datasheet
3901008061
Page 28 of 36
June 2004
Rev 007
TH8061
Voltage Regulator with integrated LIN Transceiver
6. PIN Description
VSUP
1
8
VCC
EN
2
7
RESET
GND
3
6
TxD
BUS
4
5
RxD
TH8061
Pin
Name
1
VSUP
2
EN
3
GND
4
BUS
I/O
LIN bus line
5
RxD
O
Receive Output, 5V-push-pull
6
TxD
I
5V-Transmit Input, pull-up-Input
7
RESET
O
Reset 5V-output, active low
8
VCC
O
Regulator output 5V/50mA
TH8061 – Datasheet
3901008061
IO-Typ
Description
Supply voltage
I
Enable Input voltage regulator, HV-pull-down-Input, High-active
Ground
Page 29 of 36
June 2004
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TH8061
Voltage Regulator with integrated LIN Transceiver
7. Mechanical Specification
Small Outline Integrated Circiut (SOIC), SOIC 8, 150 mil
A1
B
D
E
e
H
h
L
A
α
ZD
A2
4.80
4.98
3.81
3.99
1.27
5.80
6.20
0.25
0.50
0.41
1.27
1.52
1.72
0°
8°
0.53
1.37
1.57
0.189
0.196
0.150
0.157
0.050
0.016
0.050
0.060
0.068
0°
8°
0.021
0.054
0.062
C
All Dimension in mm, coplanarity < 0.1 mm
min
max
0.10
0.25
0.36
0.46
0.19
0.25
All Dimension in inch, coplanarity < 0.004”
min
max
0.004
0.0098
0.014 0.0075
0.018 0.0098
TH8061 – Datasheet
3901008061
0.2284 0.0099
0.244 0.0198
Page 30 of 36
June 2004
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TH8061
Voltage Regulator with integrated LIN Transceiver
8. Tape and Reel Specification
8.1 Tape Specification
max. 10°
max. 10°
IC pocket
R
Top View
n.
mi
Sectional View
T2
P0
D0
P2
T
E
G1
< A0 >
F
K0
W
B0
B1
S1
G2
P1
D1
T1
Cover Tape
Abwickelrichtung
Standard Reel with diameter of 13“
Package
Parts per Reel
Width
Pitch
SOIC8
2500
12 mm
8 mm
D0
E
P0
P2
Tmax
T1 max
G1 min
G2 min
B1 max
D1 min
F
P1
Rmin
T2 max
W
1.5
+0.1
1.75
±0.1
4.0
±0.1
2.0
±0.05
0.6
0.1
0.75
0.75
8.2
1.5
5.5
±0.05
4.0
±0.1
30
6.5
12.0
±0.3
A0, B0, K0 can be calculated with package specification.
Cover Tape width 9.2 mm.
TH8061 – Datasheet
3901008061
Page 31 of 36
June 2004
Rev 007
TH8061
Voltage Regulator with integrated LIN Transceiver
8.2 Reel Specification
W2
W1
B*
D*
C
A
N
Amax
B*
C
D*min
330
2.0 ±0.5
13.0 +0,5/-0,2
20.2
Width of half reel
Nmin
W1
W2 max
4 mm
100,0
4,4
7,1
8 mm
100,0
8,4
11,1
TH8061 – Datasheet
3901008061
Page 32 of 36
June 2004
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TH8061
Voltage Regulator with integrated LIN Transceiver
9. ESD/EMC Remarks
9.1 General Remarks
Electronic semiconductor products are sensitive to Electro Static Discharge (ESD).
Always observe Electro Static Discharge control procedures whenever handling semiconductor products.
9.2 ESD-Test
The TH8061 is tested according MIL883-3015.7 (human body model).
9.3 EMC
The test on EMC impacts is done according to ISO 7637-1 for power supply pins and ISO 7637-3 for dataand signal pins.
Power Supply pin VSUP:
Testpulse
Condition
Duration
1
t1 = 5 s / US = -100 V / tD = 2 ms
5000 pulses
2
t1 = 0.5 s / US = 100 V / tD = 0.05 ms
5000 pulses
US = -150 V/ US = 100 V
burst 100ns / 10 ms / 90 ms break
1h
3a/b
5
Ri = 0.5 Ω, tD = 400 ms
10 pulses every 1min
tr = 0.1 ms / UP+US = 40 V
Data- and signal pins EN, BUS:
Testpulse
Condition
Duration
1
t1 = 5 s / US = -100 V / tD = 2 ms
1000 pulses
2
t1 = 0.5 s / US = 100 V / tD = 0.05 ms
1000 pulses
US = -150 V/ US = 100 V
burst 100ns / 10 ms / 90 ms break
1000 burst
3a/b
TH8061 – Datasheet
3901008061
Page 33 of 36
June 2004
Rev 007
TH8061
Voltage Regulator with integrated LIN Transceiver
10. Revision History
Version
Changes
Remark
Date
1.0
Preliminary Release
Sep. 2000
1.2a
First official release
Feb. 2001
Complete rework of
datasheet
Aug. 2002
002
-
General changes to new document layout
Improved features description
Added detailed block diagram
Changed LIN Bus static and dynamic parameters to be conform to LIN
specification 1.2 and future 1.3
Added static parameters for pin TxD and RxD
Add timing diagram for slope time
Improved functional description
Added chapter “Operating during Disturbance”
Added chapter “Application Hints”
Added chapter “ESD/EMC Remarks”
Added chapter “Reliability Information”
Added chapter “Disclaimer”
003
-
Added chapter “LIN System Parameters”
Added chapter “Min/max slope time calculation”
Sep. 2002
004
-
Added chapter “Revision History”
Nov. 2002
005
-
Add compatibility to LIN 1.3
Jan. 2003
006
-
Changed ESR values in chapter 2.3 Static Characteristics
Update of chapter 0
Add chapter “Tape and Reel Specification”
Sep.2003
007
-
Update of “Block diagram”
Update of “Dynamic characteristic” with LIN 2.0 parameters
Update of chapter “Initialisation”
Update of chapter “Functional description TxD, RxD, Reset and EN”
Update of chapter “Low drop regulator”
Add chapter “Under voltage reset”
Deleted chapter “Recommandations for system design”
Delete of chapter “Min/Max slope time calculation”
Jun 2004
-
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11. Assembly Information
This Melexis device is classified and qualified regarding soldering technology, solderability and moisture
sensitivity level, as defined in this specification, according to following test methods:
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
IPC/JEDEC J-STD-020
Moisture/Reflow Sensitivity Classification For Nonhermetic Solid State Surface Mount Devices
(classification reflow profiles according to table 5-2)
EIA/JEDEC JESD22-A113
Preconditioning of Nonhermetic Surface Mount Devices Prior to Reliability Testing
(reflow profiles according to table 2)
CECC00802
Standard Method For The Specification of Surface Mounting Components (SMDs) of Assessed
Quality
EIA/JEDEC JESD22-B106
Resistance to soldering temperature for through-hole mounted devices
EN60749-15
Resistance to soldering temperature for through-hole mounted devices
MIL 883 Method 2003 / EIA/JEDEC JESD22-B102
Solderability
For all soldering technologies deviating from above mentioned standard conditions (regarding peak
temperature, temperature gradient, temperature profile etc) additional classification and qualification tests
have to be agreed upon with Melexis.
The application of Wave Soldering for SMD’s is allowed only after consulting Melexis regarding assurance of
adhesive strength between device and board.
Based on Melexis commitment to environmental responsibility, European legislation (Directive on the
Restriction of the Use of Certain Hazardous substances, RoHS) and customer requests, Melexis has
installed a roadmap to qualify their package families for lead free processes also.
Various lead free generic qualifications are running, current results on request.
For more information on Melexis lead free statement
http://www.melexis.com/html/pdf/MLXleadfree-statement.pdf
see
quality
page
at
our
website:
12. Disclaimer
Devices sold by Melexis are covered by the warranty and patent indemnification provisions appearing in its
Term of Sale. Melexis makes no warranty, express, statutory, implied, or by description regarding the
information set forth herein or regarding the freedom of the described devices from patent infringement.
Melexis reserves the right to change specifications and prices at any time and without notice. Therefore,
prior to designing this product into a system, it is necessary to check with Melexis for current information.
This product is intended for use in normal commercial applications. Applications requiring extended
temperature range, unusual environmental requirements, or high reliability applications, such as military,
medical life-support or life-sustaining equipment are specifically not recommended without additional
processing by Melexis for each application.
The information furnished by Melexis is believed to be correct and accurate. However, Melexis shall not be
liable to recipient or any third party for any damages, including but not limited to personal injury, property
damage, loss of profits, loss of use, interrupt of business or indirect, special incidental or consequential
damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical
data herein. No obligation or liability to recipient or any third party shall arise or flow out of Melexis’ rendering
of technical or other services.
© 2002 Melexis NV. All rights reserved.
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Rev 007
TH8061
Voltage Regulator with integrated LIN Transceiver
Your notes
For the latest version of this document. Go to our website at
www.melexis.com
Or for additional information contact Melexis Direct:
Europe and Japan:
Phone: +32 1367 0495
E-mail: [email protected]
All other locations:
Phone: +1 603 223 2362
E-mail: [email protected]
ISO/TS16949 and ISO14001 Certified
TH8061 – Datasheet
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June 2004
Rev 007