PANASONIC MN8390-C

For Information Equipment
MN8390-C
LCD Panel Source Driver
Overview
The MN8390-C is for displaying an analog video signal on
a TFT color liquid crystal display panel in such applications
as LCD television sets and video cameras.
Features
Lower power consumption and reduced EMI emissions
owing to digital 3.0 volt power supply and analog 5.0
volt power supply
Broad dynamic range of 4.6 V (for power supply
voltage of 5.0 V)
Low discrepancies between output pins: ±20 mV (typ.)
240 output channels
Support for striped and delta panel layouts by switching
analog (R, G, B) signals
Support for sequential sampling mode (with CLK1 to
CLK3 inputs)
Support for serial cascade connections
Automatic clock suspension after reading specified
amount of data
Choice of shift register shift directions (right/left)
Applications
LCD television sets and video cameras
MN8390-C
For Information Equipment
QC80
QB80
QA80
QC1
QB1
QA1
Block Diagram
VDD2
VSS2
VBS
Bias
control circuit
Output buffer
OE
240
VA,VB,
VC
3
D1
Analog
multiplexer
3
Two sample-and-hold circuits
VDD1
VSS1
240
CLK1,
CLK2,
CLK3
3
Clock
generator
circuit
Bidirectional 240-bit shift register
MOD
RL
STHR
TEST1
TEST2
Shift register
control circuit
STHL
For Information Equipment
MN8390-C
Pin Descriptions
Pin No.
99 to 102
Symbol
STHR
21 to 24
STHL
Pin Name
Shift data I/O
I/O
I/O
Function Description
These are I/O pins for the bidirectional shift register.
The RL pin controls their I/O directions.
RL
H
L
27 to 30
RL
Shift direction
I
control
STHR
Input
Output
STHL
Output
Input
(1) Input
The pins provide input data to the shift register's first
stage. The shift register reads in this data at the rising
edge of the CLK1 signal.
(2) Output
In a cascade connection, the pins provide the data for
the synchronizing output stage synchronized with the
rising edge of the CLK1 signal.
This pin controls the shift direction for the
bidirectional shift register.
RL="H" : QA1→ QB1→ QC1→ → QC80
RL="L" : QC80→ QB80→ QA80→ → QA1
42 to 45
CLK1 to 3
Clock input
I
37 to 40
These pins provide the shift clock signals that the
sample-and-hold circuits use to generate the data for
32 to 35
the LCD drive output pins (QA1-QC80).
The following lists the relationships between these
clock signals and the output pins.
CLK1 RL="H":
RL="L":
CLK2:
70 to 73
OE
Output enable
I
QA1 to QA80
QC1 to QC80
QB1 to QB80
CLK3 RL="H":
QC1 to QC80
RL="L":
QA1 to QA80
At each rising edge of this signal, the MN8390-C
switches between its two sample-and-hold circuits
and initiates output of new data. When the outputs
reach the drive potential, the MN8390-C
automatically reduces the drive power, but maintains
the outputs at the drive potential.
47 to 50
D1
Analog signal
swiching
I
This pin controls the mapping between the three
analog inputs (VA, VB, and VC) and the drive
outputs (QA, QB, and QC).
D1
L
H
Input
VA
VB
VC
VA
VB
VC
Output
QA1 to QA80
QB1 to QB80
QC1 to QC80
QB1 to QB80
QC1 to QC80
QA1 to QA80
MN8390-C
For Information Equipment
Pin Descriptions
Pin No.
Symbol
Pin Name
I/O
93 to 97
VBS
Bias adjustment
I
Function Description
The voltage applied to this pin adjusts the output
buffer bias and thus the drive capacity of the LCD
drive outputs.
87 to 91
VA
Analog signal
81 to 85
VB
input
75 to 79
VC
147, 149
QA1 to 80
LCD drive
151 to 385
QB1 to 80
output
387, 389
QC1 to 80
I
These pins accept the analog signal inputs for routing
to the LCD drive outputs.
O
These pins yield the levels obtained by applying the
sample-and-hold circuits to the analog inputs (VA,
VB, and VC).
391
52
MOD
62
TEST1
Mode selection
I
signal input
Test input
Connect this pin to VSS1 for sequential sampling
mode.
I
Connect this pin to VDD1.
61
TEST2
Test input
I
63 to 68
VDD1
Power supply for
—
These pins supply the driving potential for the logic
9 to 18
VDD2
Power supply for
—
These pins supply the driving potential for the
—
These pins supply the ground potential for the logic
—
These pins supply the ground potential for the
digital circuits
105 to 114
and other digital circuits.
analog circuits
53 to 58
V SS1
127 to 142
V SS2
Ground for
sample-and-hold and other analog circuits.
digital circuits
396 to 409
Ground for
analog circuits
Connect this pin to VDD1.
and other digital circuits.
sample-and-hold and other analog circuits.