DATA SHEET MOS INTEGRATED CIRCUIT µ PD160062 420-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 64-GRAY SCALE) DESCRIPTION The µ PD160062 is a source driver for TFT-LCDs capable of dealing with displays with 64-gray scale. Data input is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors by output of 64 values γ -corrected by an internal D/A converter and 5-by-2 external power modules. Because the output dynamic range is as large as VSS2 +0.1 V to VDD2 –0.1 V, level inversion operation of the LCD’s common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and column line inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit D/A converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. Assuring a clock frequency of 45 MHz when driving at 2.3 V, this driver is applicable to SXGA+ standard TFT-LCD panels. FEATURES • CMOS level input (2.3 to 3.6 V) • 420 outputs • Input of 6 bits (gray scale data) by 6 dots • Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter (R-DAC) • Logic power supply voltage (VDD1) : 2.3 to 3.6 V • Driver power supply voltage (VDD2) : 8.0 to 9.0 V • High-speed data transfer: fCLK = 45 MHz (internal data transfer speed when operating at VDD1 = 2.3 V) • Output dynamic range VSS2 +0.1 V to VDD2 –0.1 V • Apply for dot-line inversion, n-line inversion and column line inversion • Output voltage polarity inversion function (POL) • Input data inversion function (capable of controlling by each input port) (POL21, POL22) • Current consumption control function (LPC, HPC, Bcont) • Slim chip ORDERING INFORMATION Part Number Package µ PD160062N-××× TCP (TAB package) Remark The TCP’s external shape is customized. To order the required shape, please contact one of our sales representatives. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S16449EJ1V0DS00 (1st edition) Date Published July 2003 NS CP(K) Printed in Japan 2002 µ PD160062 1. BLOCK DIAGRAM STHR R,/L CLK STB STHL VDD1 VSS1 70-bit bidirectional shift register C1 C2 C69 D00 to D05 D10 to D15 D20 to D25 D30 to D35 D40 to D45 D50 to D55 POL21, POL22 C70 Data register POL Latch VDD2 Level shifter VSS2 V0 to V9 D/A converter HPC LPC Bcont Voltage follower output S1 S2 S3 S420 Remark /xxx indicates active low signal. 2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER S1 V5 S419 5 V0 V4 S2 Multiplexer 6-bit D/A converter 5 V9 POL 2 Data Sheet S16449EJ1V0DS S420 µ PD160062 3. PIN CONFIGURATION (µ PD160062N-xxx: TCP) (Copper Foil Surface, Face-up) STHL D55 D54 D53 D52 D51 D50 D45 D44 D43 D42 D41 D40 D35 D34 D33 D32 D31 D30 VDD1 R,/L V9 V8 V7 V6 V5 VDD2 VSS2 Bcont V4 V3 V2 V1 V0 HPC VSS1 LPC CLK STB POL POL21 POL22 D25 D24 D23 D22 D21 D20 D15 D14 D13 D12 D11 D10 D05 D04 D03 D02 D01 D00 STHR S420 S419 S418 S417 Copper Foil Surface S4 S3 S2 S1 Remark This figure does not specify the TCP package. Data Sheet S16449EJ1V0DS 3 µ PD160062 4. PIN FUNCTIONS (1/2) Pin Symbol Pin Name S1 to S420 Driver D00 to D05 Display data I/O Output Input Description The D/A converted 64-gray-scale analog voltage is output. The display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by D10 to D15 6 dots (2 pixels). D20 to D25 DX0: LSB, DX5: MSB D30 to D35 D40 to D45 D50 to D55 R,/L Shift direction Input control The shift direction control pin of shift register. The shift directions of the shift registers are as follows. R,/L = H (right shift) : STHR input, S1 → S420, STHL output R,/L = L (left shift) : STHL input, S420 → S1, STHR output STHR Right shift start I/O These refer to the start pulse I/O pins when driver ICs are connected in cascade. Fetching of display data starts when H is read at the rising edge of CLK. pulse R,/L = H (right shift) : STHR input, STHL output STHL Left shift start I/O pulse R,/L = L (left shift) : STHL input, STHR output A H level should be input as the pulse of one cycle of the clock signal. If the start pulse input is more than 2 CLK, the first 1 CLK of the H level input is valid. CLK Shift clock Input Refers to the shift register’s shift clock input. The display data is incorporated into the data register at the rising edge. At the rising edge of the 70th clock after the start pulse input, the start pulse output reaches the high level, thus becoming the start pulse of the next-level driver. If 72 clock pulses are input after input of the start pulse, input of display data is halted automatically. The contents of the shift register are cleared at the STB’s rising edge. STB Latch Input The contents of the data register are transferred to the latch circuit at the rising edge. And, at the falling edge, the gray scale voltage is supplied to the driver. It is necessary to ensure input of one pulse per horizontal period. POL Polarity input Input POL = L: The S2n–1 output uses V0 to V4 as the reference supply. The S2n output uses V5 to V9 as the reference supply. POL = H: The S2n–1 output uses V5 to V9 as the reference supply. The S2n output uses V0 to V4 as the reference supply. S2n−1 indicates the odd output and S2n indicates the even output. Input of the POL signal is allowed the setup time (tPOL-STB) with respect to STB’s rising edge. POL21, Data inversion Input Data inversion can invert when display data is loaded. POL21: Invert/not invert of display data D00 to D05, D10 to D15, D20 to D25 POL22 POL22: Invert/not invert of display data D30 to D35, D40 to D45, D50 to D55 POL21, POL22 = H: Data inversion loads display data after inverting it. POL21, POL22 = L: Data inversion does not invert input data. LPC Low power control Input Controls the write function of the driver section by digitally controlling the bypass Input CONTROL FUNCTION for details. current of the output amplifier. Refer to 9. CURRENT CONSUMPTION HPC High power control This pin is pulled up to the VDD1 power supply inside the IC. Bcont Bias control Input This pin can be used to finely control the bias current inside the output amplifier. Refer to 9. CURRENT CONSUMPTION CONTROL FUNCTION for details. When this fine-control function is not required, leave this pin open. 4 Data Sheet S16449EJ1V0DS µ PD160062 (2/2) Pin Symbol V0 to V9 Pin Name I/O γ -corrected power − supplies Description Input the γ -corrected power supplies from outside by using operational amplifier. Make sure to maintain the following relationships. During the gray scale voltage output, be sure to keep the gray scale level power supply at a constant level. VDD2 −0.1 V ≥ V0 > V1 > V2 > V3 > V4 ≥ 0.5 V DD2 0.5 V DD2 ≥ V5 > V6 > V7 > V8 > V9 ≥ VSS2 +0.1 V VDD1 Logic power supply − 2.3 to 3.6 V VDD2 Driver power supply − 8.0 to 9.0 V VSS1 Logic ground − Grounding VSS2 Driver ground − Grounding Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0 to V9 in that order. Reverse this sequence to shut down. 2. To stabilize the supply voltage, please be sure to insert a 0.1 µF bypass capacitor between VDD1-VSS1 and VDD2-VSS2. Furthermore, for increased precision of the D/A converter, insertion of a bypass capacitor of about 0.01 µF is also recommended between the γ -corrected power supply terminals (V0, V1, V2, ···, V9) and VSS2. Data Sheet S16449EJ1V0DS 5 µ PD160062 5. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE The µ PD160062 incorporates a 6-bit D/A converter whose odd output pins and even output pins output respectively gray scale voltages of differing polarity with respect to the LCD’s counter electrode (common electrode) voltage. The D/A converter consists of ladder resistors and switches. The ladder resistors (r0 to r62) are designed so that the ratio of LCD panel γ -compensated voltages to V0’ to V63’ and V0” to V63” is almost equivalent. For the 2 sets of five γ -compensated power supplies, V0 to V4 and V5 to V9, respectively, input gray scale voltages of the same polarity with respect to the common voltage. When fine gray scale voltage precision is not necessary, there is no need to connect a voltage follower circuit to the γ -compensated power supplies V1 to V3 and V6 to V8. Figure 5−1 shows the relationship between the driving voltages such as liquid-crystal driving voltages VDD2 and VSS2, common electrode potential VCOM, and γ -corrected voltages V0 to V9 and the input data. Be sure to maintain the voltage relationships of VDD2 −0.1 V ≥ V0 > V1 > V2 > V3 > V4 ≥ 0.5 VDD2 0.5 VDD2 ≥ V5 > V6 > V7 > V8 > V9 ≥ VSS2 +0.1 V Figures 5−2 shows γ -corrected power supply voltage and ladder resistors ratio and figure 5−3 shows the relationship between the input data and the output voltage. Figure 5−1. Relationship between Input Data and γ -corrected Power Supplies VDD2 0.1 V Split interval V0 16 V1 16 V2 V3 16 15 V4 VCOM 0.5 VDD2 V5 15 V6 16 V7 16 V8 16 V9 0.1 V VSS2 00 6 10 20 Input data (HEX) Data Sheet S16449EJ1V0DS 30 3F µ PD160062 Figure 5−2. γ -corrected Voltages and Ladder Resistors Ratio V0 V0’ V5 r0 V63’’ r62 V1’ V62’’ r61 r1 V61’’ V2’ r60 r2 V60’’ V3’ r59 r3 r49 r14 V15’ V49’’ r48 r15 V16’ V1 V48’’ V6 r47 r16 V17’ V47’’ r46 r17 r46 r17 V47’ V17’’ r47 r16 V48’ V3 V16’’ V8 r48 r15 V49’ V15’’ r49 r14 r60 r2 V2’’ V61’ r1 r61 V62’ V1’’ r62 V4 r0 V63’ V9 V0’’ rn Ratio 1 Ratio 2 r0 8.00 0.0505 r1 7.50 0.0473 r2 7.00 0.0442 r3 6.50 0.0410 r4 6.00 0.0379 r5 5.50 0.0347 r6 5.50 0.0347 r7 5.00 0.0315 r8 5.00 0.0315 r9 4.00 0.0252 r10 4.00 0.0252 r11 3.50 0.0221 r12 3.50 0.0221 r13 3.50 0.0221 r14 3.00 0.0189 r15 3.00 0.0189 r16 3.00 0.0189 r17 2.50 0.0158 r18 2.50 0.0158 r19 2.50 0.0158 r20 2.00 0.0126 r21 2.00 0.0126 r22 2.00 0.0126 r23 1.50 0.0095 r24 1.50 0.0095 r25 1.50 0.0095 r26 1.50 0.0095 r27 1.00 0.0063 r28 1.00 0.0063 r29 1.00 0.0063 r30 1.00 0.0063 r31 1.00 0.0063 r32 1.00 0.0063 r33 1.00 0.0063 r34 1.00 0.0063 r35 1.00 0.0063 r36 1.00 0.0063 r37 1.00 0.0063 r38 1.00 0.0063 r39 1.00 0.0063 r40 1.00 0.0063 r41 1.00 0.0063 r42 1.00 0.0063 r43 1.00 0.0063 r44 1.00 0.0063 r45 1.00 0.0063 r46 1.00 0.0063 r47 1.00 0.0063 r48 1.00 0.0063 r49 1.00 0.0063 r50 1.00 0.0063 r51 1.00 0.0063 r52 1.00 0.0063 r53 1.50 0.0095 r54 1.50 0.0095 r55 1.50 0.0095 r56 2.00 0.0126 r57 2.00 0.0126 r58 2.50 0.0158 r59 2.50 0.0158 r60 3.00 0.0189 r61 5.00 0.0315 r62 8.00 0.0505 Total resistance Minimum resistance value Value (Ω) 544 510 476 442 408 374 374 340 340 272 272 238 238 238 204 204 204 170 170 170 136 136 136 102 102 102 102 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 68 102 102 102 136 136 170 170 204 340 544 10778 68 Remark The resistance ratio1 is a relative ratio in the case of setting the minimum resistance value to 1. The resistance ratio2 is a relative ratio in the case of setting the total resistance to 1. Caution There is no connection between V4 and V5 terminal in the chip. Data Sheet S16449EJ1V0DS 7 µ PD160062 Figure 5−3. Relationship between Input Data and Output Voltage (POL21, POL22 = L) (Output Voltage 1) VDD2 −0.1 V ≥ V0 > V1 > V2 > V3 > V4 ≥ 0.5 VDD2 (Output Voltage 2) 0.5 VDD2 ≥ V5 > V6 > V7 > V8 > V9 ≥ VSS2 +0.1 V Input Data 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 8 V0' V1' V2' V3' V4' V5' V6' V7' V8' V9' V10' V11' V12' V13' V14' V15' V16' V17' V18' V19' V20' V21' V22' V23' V24' V25' V26' V27' V28' V29' V30' V31' V32' V33' V34' V35' V36' V37' V38' V39' V40' V41' V42' V43' V44' V45' V46' V47' V48' V49' V50' V51' V52' V53' V54' V55' V56' V57' V58' V59' V60' V61' V62' V63' Output Voltage 1 V0 V1+(V0-V1)× 4930 V1+(V0-V1)× 4420 V1+(V0-V1)× 3944 V1+(V0-V1)× 3502 V1+(V0-V1)× 3094 V1+(V0-V1)× 2720 V1+(V0-V1)× 2346 V1+(V0-V1)× 2006 V1+(V0-V1)× 1666 V1+(V0-V1)× 1394 V1+(V0-V1)× 1122 V1+(V0-V1)× 884 V1+(V0-V1)× 646 V1+(V0-V1)× 408 V1+(V0-V1)× 204 V1 V2+(V1-V2)× 1666 V2+(V1-V2)× 1496 V2+(V1-V2)× 1326 V2+(V1-V2)× 1156 V2+(V1-V2)× 1020 V2+(V1-V2)× 884 V2+(V1-V2)× 748 V2+(V1-V2)× 646 V2+(V1-V2)× 544 V2+(V1-V2)× 442 V2+(V1-V2)× 340 V2+(V1-V2)× 272 V2+(V1-V2)× 204 V2+(V1-V2)× 136 V2+(V1-V2)× 68 V2 V3+(V2-V3)× 1020 V3+(V2-V3)× 952 V3+(V2-V3)× 884 V3+(V2-V3)× 816 V3+(V2-V3)× 748 V3+(V2-V3)× 680 V3+(V2-V3)× 612 V3+(V2-V3)× 544 V3+(V2-V3)× 476 V3+(V2-V3)× 408 V3+(V2-V3)× 340 V3+(V2-V3)× 272 V3+(V2-V3)× 204 V3+(V2-V3)× 136 V3+(V2-V3)× 68 V3 V4+(V3-V4)× 2278 V4+(V3-V4)× 2210 V4+(V3-V4)× 2142 V4+(V3-V4)× 2074 V4+(V3-V4)× 2006 V4+(V3-V4)× 1904 V4+(V3-V4)× 1802 V4+(V3-V4)× 1700 V4+(V3-V4)× 1564 V4+(V3-V4)× 1428 V4+(V3-V4)× 1258 V4+(V3-V4)× 1088 V4+(V3-V4)× 884 V4+(V3-V4)× 544 V4 / / / / / / / / / / / / / / / 5474 5474 5474 5474 5474 5474 5474 5474 5474 5474 5474 5474 5474 5474 5474 / / / / / / / / / / / / / / / 1870 1870 1870 1870 1870 1870 1870 1870 1870 1870 1870 1870 1870 1870 1870 / / / / / / / / / / / / / / / 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 / / / / / / / / / / / / / / 2346 2346 2346 2346 2346 2346 2346 2346 2346 2346 2346 2346 2346 2346 V0'' V1'' V2'' V3'' V4'' V5'' V6'' V7'' V8'' V9'' V10'' V11'' V12'' V13'' V14'' V15'' V16'' V17'' V18'' V19'' V20'' V21'' V22'' V23'' V24'' V25'' V26'' V27'' V28'' V29'' V30'' V31'' V32'' V33'' V34'' V35'' V36'' V37'' V38'' V39'' V40'' V41'' V42'' V43'' V44'' V45'' V46'' V47'' V48'' V49'' V50'' V51'' V52'' V53'' V54'' V55'' V56'' V57'' V58'' V59'' V60'' V61'' V62'' V63'' Output Voltage 2 V9 V9+(V8-V9)× 544 V9+(V8-V9)× 1054 V9+(V8-V9)× 1530 V9+(V8-V9)× 1972 V9+(V8-V9)× 2380 V9+(V8-V9)× 2754 V9+(V8-V9)× 3128 V9+(V8-V9)× 3468 V9+(V8-V9)× 3808 V9+(V8-V9)× 4080 V9+(V8-V9)× 4352 V9+(V8-V9)× 4590 V9+(V8-V9)× 4828 V9+(V8-V9)× 5066 V9+(V8-V9)× 5270 V8 V8+(V7-V8)× 204 V8+(V7-V8)× 374 V8+(V7-V8)× 544 V8+(V7-V8)× 714 V8+(V7-V8)× 850 V8+(V7-V8)× 986 V8+(V7-V8)× 1122 V8+(V7-V8)× 1224 V8+(V7-V8)× 1326 V8+(V7-V8)× 1428 V8+(V7-V8)× 1530 V8+(V7-V8)× 1598 V8+(V7-V8)× 1666 V8+(V7-V8)× 1734 V8+(V7-V8)× 1802 V7 V7+(V6-V7)× 68 V7+(V6-V7)× 136 V7+(V6-V7)× 204 V7+(V6-V7)× 272 V7+(V6-V7)× 340 V7+(V6-V7)× 408 V7+(V6-V7)× 476 V7+(V6-V7)× 544 V7+(V6-V7)× 612 V7+(V6-V7)× 680 V7+(V6-V7)× 748 V7+(V6-V7)× 816 V7+(V6-V7)× 884 V7+(V6-V7)× 952 V7+(V6-V7)× 1020 V6 V6+(V5-V6)× 68 V6+(V5-V6)× 136 V6+(V5-V6)× 204 V6+(V5-V6)× 272 V6+(V5-V6)× 340 V6+(V5-V6)× 442 V6+(V5-V6)× 544 V6+(V5-V6)× 646 V6+(V5-V6)× 782 V6+(V5-V6)× 918 V6+(V5-V6)× 1088 V6+(V5-V6)× 1258 V6+(V5-V6)× 1462 V6+(V5-V6)× 1802 V5 Data Sheet S16449EJ1V0DS / / / / / / / / / / / / / / / 5474 5474 5474 5474 5474 5474 5474 5474 5474 5474 5474 5474 5474 5474 5474 / / / / / / / / / / / / / / / 1870 1870 1870 1870 1870 1870 1870 1870 1870 1870 1870 1870 1870 1870 1870 / / / / / / / / / / / / / / / 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 / / / / / / / / / / / / / / 2346 2346 2346 2346 2346 2346 2346 2346 2346 2346 2346 2346 2346 2346 µ PD160062 6. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN Data format: 6 bits × 2 RGBs (6 dots) Input width: 36 bits (2-pixel data) (1) R,/L = H (right shift) Output S1 S2 S3 S4 xxx S419 S420 Data D00 to D05 D10 to D15 D20 to D25 D30 to D35 xxx D40 to D45 D50 to D55 (2) R,/L = L (left shift) Output S1 S2 S3 S4 xxx S419 S420 Data D00 to D05 D10 to D15 D20 to D25 D30 to D35 xxx D40 to D45 D50 to D55 POL S2n−1 Note S2n Note L V0 to V4 V5 to V9 H V5 to V9 V0 to V4 Note S2n−1 (odd output), S2n (even output) 7. RELATIONSHIP BETWEEN STB, POL AND OUTPUT WAVEFORM The output voltage is written to the LCD panel synchronized with the STB falling edge. STB POL S2n-1 Selected voltage V0 to V4 Selected voltage V5 to V9 Selected voltage V0 to V4 S2n Selected voltage V0 to V4 Selected voltage V5 to V9 Hi-Z Hi-Z Selected voltage V5 to V9 Hi-Z Remark Hi-Z: High impedance Data Sheet S16449EJ1V0DS 9 µ PD160062 8. RELATIONSHIP BETWEEN STB, CLK AND OUTPUT WAVEFORM The output voltage is written to the LCD panel synchronized with the STB falling edge. Figure 8−1. Output Circuit Block Diagram Output Amp. − DAC + SW1 Sn (VX) VAMP(IN) Figure 8−2. Output Circuit Timing Waveform [1] [2] CLK (External input) STB (External input) SW1: ON SW1: OFF SW1: ON VAMP(IN) Sn (VOUT: External output) Output Hi-Z Output Remarks 1. STB = L: SW1 = ON, STB = H: SW1 = OFF 2. STB = H is acknowledged at timing [1] . 3. The display data latch is completed at timing [2] and the input voltage (VAMP(IN): gray-scale level voltage) of the output amplifier changes. 10 Data Sheet S16449EJ1V0DS µ PD160062 9. CURRENT CONSUMPTION CONTROL FUNCTION The µ PD160062 has a power control function which can switch the bias current of the output amplifier between four levels and a bias control function (Bcont) which can be used to finely control the bias current. < Power control function (LPC, HPC) > The bias current of the output amplifier can be switched between four levels using LPC (Low Power Control) pins and HPC (High Power Control) pins (show in below table). Power Mode LPC HPC L L Middle H or open L Normal L H or open H or open H or open High Low Following graph shows the relationship between each power modes and bias current. High Middle Normal IDD2 Low 6.00 7.00 8.00 9.00 VDD2 Remark This relationship is founded on results of simulation and don’t assuring a characteristics of this product. Data Sheet S16449EJ1V0DS 11 µ PD160062 < Bias Current Control Function (Bcont) > It is possible to fine-control the current consumption by using the bias current control function (Bcont pin). When using this function, connect this pin to the stabilized ground potential (VSS2) via an external resistor (REXT). When not using this function, leave this pin open. Figure 9−1. Bias Current Control Function (Bcont) µ PD160062 HPC H/L LPC H/L Bcont REXT VSS2 Refer to the table below for the percentage of current regulation when using the bias current control function. Table 9−1. Current Consumption Regulation Percentage Compared to Normal Mode (VDD1 = 3.3 V, VDD2 = 8.7 V) REXT (kΩ) Current Consumption Regulation Percentage (%) LPC = L LPC = H/open ∞ (Open) 100 65 50 110 70 20 115 80 10 120 85 Remark The above current consumption regulation percentages are founded on results of simulation and don’t assuring a characteristics of this product. Caution Because the power and bias-current control functions control the bias current in the output amplifier and regulate the over-all current consumption of the driver IC, when this occurs, the characteristics of the output amplifier will simultaneously change. Therefore, when using these functions, be sure to sufficiently evaluate the picture quality. 12 Data Sheet S16449EJ1V0DS µ PD160062 10. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C, VSS1 = VSS2 = 0 V) Parameter Symbol Rating Unit Logic Part Supply Voltage VDD1 −0.5 to +4.0 V Driver Part Supply Voltage VDD2 −0.5 to +10.0 V Logic Part Input Voltage VI1 −0.5 to VDD1 +0.5 V Driver Part Input Voltage VI2 −0.5 to VDD2 +0.5 V Logic Part Output Voltage VO1 −0.5 to VDD1 +0.5 V Driver Part Output Voltage VO2 −0.5 to VDD2 +0.5 V Operating Ambient Temperature TA −10 to +75 °C Storage Temperature Tstg −55 to +125 °C Caution Product qualify may suffer if the absolute maximum rating is exceeded even momentarily for any parameter/ That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Range (TA = −10 to +75°C, VSS1 = VSS2 = 0 V) Parameter Symbol Conditions MIN. TYP. 2.3 MAX. Unit 3.6 V Logic Part Supply Voltage VDD1 Driver Part Supply Voltage VDD2 9.0 V High-Level Input Voltage VIH 0.7 VDD1 VDD1 V Low-Level Input Voltage VIL 0 0.3 VDD1 V γ -corrected Voltage V0 to V4 0.5 VDD2 VDD2 −0.1 V V5 to V9 VSS2 +0.1 0.5 VDD2 V Driver Part Output Voltage VO VSS2 +0.1 VDD2 −0.1 V Maximum Clock Frequency fCLK 45 MHz 8.0 VDD1 = 2.3 V Data Sheet S16449EJ1V0DS 8.5 13 µ PD160062 Electrical Characteristics (TA = −10 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 8.0 to 9.0 V, VSS1 = VSS2 = 0 V, unless otherwise specified, power mode = normal, Bcont = open.) Parameter Symbol Conditions MIN. Input Leak Current IIL High-Level Output Voltage VOH STHR (STHL), IOH = 0 mA Low-Level Output Voltage VOL STHR (STHL), IOL = 0 mA γ -corrected Resistance Rγ VDD2 = 8.5 V, V0 to V4 = V5 to V9 = Driver Output Current IVOH TYP. MAX. Unit ±1.0 µA VDD1 −0.1 5.4 V 10.8 0.1 V 21.6 kΩ −30 µA 4.0 V VX = 7.0 V, VOUT = 6.5 V IVOL VX = 1.0 V, VOUT = 1.5 V Output Voltage Deviation ∆VO TA = 25°C, VDD1 = 3.3 V, Output swing difference ∆VP–P Note Note µA 30 ±7 ±20 mV VOUT = 2.0 V, 4.25 V, 6.5 V ±2 ±15 mV IDD1 VDD1 1.0 6.5 mA IDD2 VDD2, with no load 3.0 6.5 mA VDD2 = 8.5 V, deviation Logic Part Dynamic Current Consumption Driver Part Dynamic Current Consumption Note VX refers to the output voltage of analog output pins S1 to S420. VOUT refers to the voltage applied to analog output pins S1 to S420. Cautions 1. fSTB = 64 kHz, fCLK = 40 MHz 2. The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the measured values in the dot checkerboard input pattern. 3. Refers to the current consumption per driver when cascades are connected under the assumption of SXGA+ single-sided mounting (10 units). Switching Characteristics (TA = −10 to +75°C, VDD1 = 2.3 to 3.6 V, VDD2 = 8.0 to 9.0 V, VSS1 = VSS2 = 0 V, unless otherwise specified, power mode = normal, Bcont = open.) Parameter Symbol Conditions MIN. TYP. MAX. Unit Start Pulse Delay Time tPLH1 CL = 10 pF 10 20 ns Driver Output Delay Time tPLH2 CL = 75 pF, RL = 5 kΩ 2.5 5 µs tPLH3 5 8 µs tPHL2 2.5 5 µs tPHL3 5 8 µs 10 pF 10 pF Input Capacitance CI1 STHR (STHL) excluded, TA = 25°C CI2 14 STHR (STHL), TA = 25°C Data Sheet S16449EJ1V0DS µ PD160062 Timing Requirement (TA = −10 to +75°C, VDD1 = 2.3 to 3.6 V, VSS1 = 0 V, tr = tf = 5.0 ns) Parameter Symbol Conditions MIN. TYP. MAX. Unit Clock Pulse Width PWCLK 22 ns Clock Pulse High Period PWCLK(H) 4 ns Clock Pulse Low Period PWCLK(L) 4 ns Data Setup Time tSETUP1 4 ns Data Hold Time tHOLD1 0 ns Start Pulse Setup Time tSETUP2 4 ns Start Pulse Hold Time tHOLD2 0 ns POL21, POL22 Setup Time tSETUP3 4 ns POL21, POL22 Hold Time tHOLD3 0 ns STB Pulse Width PWSTB 2 CLK Last Data Timing tLDT 2 CLK CLK-STB Time tCLK-STB CLK ↑ → STB ↑ 6 ns STB-CLK Time tSTB-CLK STB ↑ → CLK ↑ 9 ns Time Between STB and Start Pulse tSTB-STH STB ↑ → STHR(STHL) ↑ 2 CLK POL-STB Time tPOL-STB POL ↑ or ↓ → STB ↑ –5 ns STB-POL Time tSTB-POL STB ↓ → POL ↓ or ↑ 6 ns Remark Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1. Data Sheet S16449EJ1V0DS 15 2 3 1 70 71 72 513 tr 2 tf VDD1 90% 514 10% tSETUP2 tHOLD2 VSS1 tCLK-STB tSTB-CLK VDD1 STHR (1st Dr.) VSS1 tSETUP1 Dn0 to Dn5 INVALID D1 to D6 D7 to D12 tSETUP3 POL21, POL22 tHOLD1 tSTB-STH D409 to D414 D415 to D420 D421 to D426 VDD1 D3067 to D3072 INVALID D1 to D6 D7 to D12 VSS1 tHOLD3 VDD1 INVALID INVALID Data Sheet S16449EJ1V0DS VSS1 tPLH1 VDD1 STHL (1st Dr.) VSS1 tLDT PWSTB VDD1 STB VSS1 tPOL-STB tSTB-POL VDD1 POL VSS1 tPLH3 Hi-Z tPLH2 Sn (VX) Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1. 1 CLK PWCLK(H) Switching characteristics waveform (R,/L = H) 16 PWCLK(L) PWCLK Target voltage ±0.1 VDD2 6-bit accuracy µ PD160062 tPHL2 tPHL3 µ PD160062 11. RECOMMENDED MOUNTING CONDITIONS The following conditions must be met for soldering conditions of the µ PD160062. For more details, refer to the Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html). Please consult with our sales offices in case other soldering process is used, or in case the soldering is done under different conditions. µ PD160062N-×××: TCP (TAB package) Mounting Condition Thermocompression Mounting Method Soldering Condition Heating tool 300 to 350°C, heating for 2 to 3 seconds, pressure 100g (per solder) 2 ACF Temporary bonding 70 to 100°C, pressure 3 to 8 kg/cm , time 3 to 5 seconds. (Adhesive Conductive Real bonding 165 to 180°C, pressure 25 to 45 kg/cm , time 30 to 40 seconds. Film) (When using the anisotropy conductive film SUMIZAC1003 of Sumitomo 2 Bakelite, Ltd.) Caution To find out the detailed conditions for packaging the ACF part, please contact the ACF manufacturing company. Be sure to avoid using two or more packaging methods at a time. Data Sheet S16449EJ1V0DS 17 µ PD160062 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 18 Data Sheet S16449EJ1V0DS