CD40102BMS CD40103BMS CMOS 8-Stage Presettable Synchronous Down Counters December 1992 Features Description • High Voltage Type (20V Rating) CD40102BMS and CD40103BMS consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero. The CD40102BMS is configured as two cascaded 4-bit BCD counters, and the CD40103BMS contains a single 8-bit binary counter. Each type has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the CARRY-OUT/ZERO-DETECT output are active-low logic. • CD40102BMS: 2-Decade BCD Type • CD40103BMS: 8-Bit Binary Type • Synchronous or Asynchronous Preset • Medium Speed Operation - fCL = 3.6MHz (Typ) at 10V • Cascadable • 100% Tested for Quiescent Current at 20V • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Standardized Symmetrical Output Characteristics • 5V, 10V and 15V Parametric Ratings • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” In normal operation, the counter is decremented by one count on each positive transition of the CLOCK. Counting is inhibited when the CARRY-IN/COUNTER ENABLE (CI/CE) inputs is high. The CARRY-OUT/ZERO-DETECT (CO/ZD) output goes low when the count reaches zero if the CI/CE input is low, and remains low for one full clock period. When the SYNCHRONOUS PRESET-ENABLE (SPE) input is low, data at the JAM input is clocked into the counter on the next positive clock transition regardless of the state of the CI/CE input. When the ASYNCHRONOUS PRESETENABLE (APE) input is low, data at the JAM inputs is asynchronously forced into the counter regardless of the state of the SPE, CI/CE, or CLOCK inputs. JAM inputs J0-J7 represent two 4-bit BCD words for the CD40102BMS and a single 8-bit binary word for the CD40103BMS. When the CLEAR (CLR) input is low, the counter is asynchronously cleared to its maximum count (9910 for the CD40102BMS and 25510 for the CD40103BMS) regardless of the state of any other input. The precedence relationship between control inputs is indicated in the truth table. Applications • Divide-By- “N” Counters • Programmable Times • Interrupt Timers • Cycle/Program Counter If all control inputs except CI/CE are high at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 100 or 256 clock pulses long. Pinout This causes the CO/ZD output to go low to enable the clock on each succeeding clock pulse. CD40102BMS, CD40130BMS TOP VIEW CLOCK 1 CLEAR 2 CARRY IN/ COUNTER ENABLE J0 3 4 16 VDD SYNCHRONOUS 15 PRESET ENABLE 14 CARRY OUT/ ZERO DETECT 13 J7 J1 5 12 J6 J2 6 11 J5 J3 7 10 J4 VSS 8 The CD40102BMS and CD40103BMS may be cascaded using the CI/CE input and the CO/ZD output, in either a synchronous or ripple mode as shown in Figures 16 and 17. The CD40102MS and CD40103BMS are supplied in these 16-lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack *CD40102B Only *H4W †H4X *H1L †H1F H6W †CD40130B Only 9 ASYNCHRONOUS PRESET ENABLE CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-1294 File Number 3351 Specifications CD40102BMS, CD40103BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance θja θjc Ceramic DIP Package . . . . . . . . . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20V VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20V VDD = 18V Output Voltage Output Voltage VOL15 VOH15 VDD = 15V, No Load VDD = 15V, No Load (Note 3) LIMITS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 1 +25oC - 10 µA 2 +125oC - 1000 µA 3 -55oC - 10 µA 1 +25oC -100 - nA 2 +125oC -1000 - nA 3 -55oC -100 - nA 1 +25oC - 100 nA 2 +125oC - 1000 nA 3 -55oC - 100 nA 1, 2, 3 +25oC, +125oC, -55oC - 50 mV 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA 1 +25oC 3.5 - mA 1 +25oC - -0.53 mA Output Current (Sink) Output Current (Source) IOL15 IOH5A VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA 1 +25oC - -3.5 mA 1 +25oC -2.8 -0.7 V VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC Output Current (Source) N Threshold Voltage P Threshold Voltage Functional IOH15 VNTH VPTH F VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10µA VOH > VOL < VDD/2 VDD/2 V Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC - 4 V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC 11 - V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 7-1295 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. Specifications CD40102BMS, CD40103BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Propagation Delay Clock to Output SYMBOL TPHL1 TPLH1 CONDITIONS (NOTE 1, 2) VDD = 5V, VIN = VDD or GND TPHL2 TPLH2 VDD = 5V, VIN = VDD or GND Propagation Delay Asynchronous Preset Enable to Output TPHL3 TPLH3 VDD = 5V, VIN = VDD or GND Propagation Delay Clear to Output TPLH4 VDD = 5V, VIN = VDD or GND Maximum Clock Input Frequency 9 10, 11 Propagation Delay Carry In/Counter Enable to Output Transition Time GROUP A SUBGROUPS TEMPERATURE 9 10, 11 VDD = 5V, VIN = VDD or GND FCL VDD = 5V, VIN = VDD or GND +125oC, -55oC +25oC +125oC, -55oC MIN MAX UNITS - 600 ns - 810 ns - 400 ns - 540 ns 9 +25oC - 1300 ns 10, 11 +125oC, -55oC - 1755 ns 9 +25oC - 750 ns - 1012 ns - 200 ns 10, 11 TTHL TTLH +25oC LIMITS 9 10, 11 +125oC, -55oC +25oC +125oC, -55oC - 270 ns 9 +25oC .7 - MHz 10, 11 +125oC, -55oC .52 - MHz NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC - 5 µA +125oC - 150 µA µA VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND Output Voltage VOL VDD = 5V, No Load 1, 2 1, 2 1, 2 -55oC, +25oC - 10 +125oC - 300 µA -55oC, +25oC - 10 µA +125oC - 600 µA +25oC, +125oC, - 50 mV -55oC Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA -55oC 0.64 - mA +125oC 0.9 - mA -55oC 1.6 - mA +125oC 2.4 - mA -55oC 4.2 - mA +125oC - -0.36 mA -55oC - -0.64 mA +125oC - -1.15 mA -55oC - -2.0 mA Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) IOL10 IOL15 IOH5A IOH5B VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V 1, 2 1, 2 1, 2 VDD = 5V, VOUT = 2.5V 1, 2 7-1296 Specifications CD40102BMS, CD40103BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER SYMBOL Output Current (Source) IOH10 Output Current (Source) IOH15 CONDITIONS VDD = 10V, VOUT = 9.5V VDD =15V, VOUT = 13.5V NOTES TEMPERATURE MIN MAX UNITS 1, 2 +125oC - -0.9 mA -55oC - -1.6 mA +125oC - -2.4 mA -55oC 1, 2 - -4.2 mA Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC - 3 V Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC 7 - V Propagation Delay Clock to Output TPHL1 TPLH1 VDD = 10V 1, 2, 3 +25oC - 260 ns VDD = 15V 1, 2, 3 +25 C - 190 ns Propagation Delay Carry In/Counter Enable to Output TPHL2 TPLH2 VDD = 10V 1, 2, 3 +25oC - 180 ns VDD = 15V 1, 2, 3 +25 C - 130 ns Propagation Delay Asynchronous Preset Enable to Output TPHL3 TPLH3 VDD = 10V 1, 2, 3 +25oC - 600 ns VDD = 15V 1, 2, 3 +25oC - 400 ns Propagation Delay Clear to Output TPLH4 VDD = 10V 1, 2, 3 +25oC - 360 ns VDD = 15V 1, 2, 3 +25oC - 200 ns Transition Time TTHL1 TTLH1 VDD = 10V 1, 2, 3 +25oC - 100 ns 1, 2, 3 +25oC - 80 ns 1, 2 +25oC 1.8 - MHz VDD = 15V 1, 2 +25oC 2.4 - MHz VDD = 5V 1, 2, 3 +25oC - 280 ns 1, 2, 3 +25oC - 140 ns 1, 2, 3 +25oC - 100 ns VDD = 5V 1, 2, 3 +25oC - 500 ns VDD = 10V 1, 2, 3 +25oC - 250 ns 1, 2, 3 +25oC - 150 ns 1, 2, 3 +25oC - 300 ns VDD = 10V 1, 2, 3 +25oC - 180 ns VDD = 15V 1, 2, 3 +25oC - 80 ns 1, 2, 3 +25oC - 360 ns 1, 2, 3 +25oC - 160 ns VDD = 15V 1, 2, 3 +25oC - 120 ns VDD = 5V 1, 2, 3 +25oC - 200 ns 1, 2, 3 +25oC - 80 ns 1, 2, 3 +25oC - 60 ns VDD = 5V 1, 2, 3 +25oC - 220 ns VDD = 10V 1, 2, 3 +25oC - 100 ns 1, 2, 3 +25oC - 70 ns 1, 2, 3 +25oC - 320 ns VDD = 10V 1, 2, 3 +25oC - 160 ns VDD = 15V 1, 2, 3 +25oC - 100 ns Maximum Clock Input Frequency FCL Minimum SPE Setup Time TSU VDD = 15V VDD = 10V VDD = 10V VDD = 15V Minimum CI/CE Setup Time TSU VDD = 15V Minimum Clock Pulse Width Minimum APE Pulse Width Minimum JAM Setup Time (Synchronous Presetting) TW TW VDD = 5V VDD = 5V VDD = 10V TSU VDD = 10V VDD = 15V Minimum APE Removal Time TREM VDD = 15V Minimum CLR Pulse Width TW VDD = 5V 7-1297 o o Specifications CD40102BMS, CD40103BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER SYMBOL Input Capacitance CIN CONDITIONS Any Input NOTES TEMPERATURE MIN MAX UNITS 1, 2 +25oC - 7.5 pF NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 25 µA 1, 4 +25oC -2.8 -0.2 V VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V 1, 4 +25oC - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns Supply Current N Threshold Voltage VNTH N Threshold Voltage Delta ∆VTN P Threshold Voltage VTP P Threshold Voltage Delta ∆VTP Functional F VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2 IDD ± 1.0µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading IOH5A ± 20% x Pre-Test Reading Output Current (Source) TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 100% 5004 1, 7, 9, Deltas 100% 5004 2, 3, 8A, 8B, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 PDA (Note 1) Final Test Group A Group B 7-1298 READ AND RECORD IDD, IOL5, IOH5A Subgroups 1, 2, 3, 9, 10, 11 Specifications CD40102BMS, CD40103BMS TABLE 6. APPLICABLE SUBGROUPS (Continued) CONFORMANCE GROUP Group D MIL-STD-883 METHOD GROUP A SUBGROUPS Sample 5005 1, 2, 3, 8A, 8B, 9 READ AND RECORD Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD 9V ± -0.5V 50kHz 25kHz 14 1, 4, 6, 11, 13 5, 7, 9, 10, 12 PART NUMBER CD40102BMS, CD40103BMS Static Burn-In 1 Note 1 14 1 - 13, 15 16 Static Burn-In 2 Note 1 14 8 1 - 7, 9 - 13, 15, 16 Dynamic BurnIn Note 1 - 3, 8, 15 2, 16 Irradiation Note 2 - NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V Functional Diagram SPE APE CI/CE CLR JAM J0 8 - STAGE DOWN COUNTER J7 C0/ZD CLOCK CD40102BMS, CD40103BMS 7-1299 CD40102BMS, CD40103BMS Logic Diagrams LSD J0 * J1 * 4 J2 * 5 J3 * 6 (MSB) 7 A B TO FF1 - FF7 CLR CLR * SPE FF3 SPE 15 CL 9 Q J Q FF1 FF2 CI CI Q CL CI CLOCK * J Q J Q APE APE * J CLR 2 SPE * C FF3 CI Q 1 TO FF1 - FF7 D CI/CE * E 3 MSD J4 * J5 * 10 11 J6 * 12 J7 * 13 (MSB) A B C 14 CARRY OUT/ ZERO DETECT J J FF4 FF5 FF6 FF7 CI CI CI Q CI Q J Q J VDD Q VSS D *ALL INPUTS ARE PROTECTED BY COS/MOS PROTECTION NETWORK E FIGURE 1. LOGIC DIAGRAM FOR CD40102BMS 7-1300 CD40102BMS, CD40103BMS Logic Diagrams (Continued) J0 * J1 * 4 J2 * 5 J3 * 6 7 A B TO FF1 - FF7 CLR CLR * SPE FF3 SPE 15 J FF1 CL 9 Q CL J FF2 Q CI CLOCK * J Q Q APE APE * J CLR 2 SPE * C CI FF3 Q CI CI Q 1 VDD TO FF1 - FF7 D CI/CE * E 3 J4 * J5 * 10 11 J6 * 12 J7 * 13 (MSB) A B C 14 CARRY OUT/ ZERO DETECT J J J J FF4 FF5 FF6 FF7 Q Q CI CI Q VDD CI Q CI VSS D *ALL INPUTS ARE VDD E FIGURE 2. LOGIC DIAGRAM FOR CD40103BMS 7-1301 PROTECTED BY COS/MOS PROTECTION NETWORK CD40102BMS, CD40103BMS TRUTH TABLE CONTROL INPUTS CLR APE SPE CI/CE 1 1 1 1 PRESET MODE 1 1 1 0 Count Down* 1 1 0 X Preset on next positive clock transition 1 0 X X 0 X X X Synchronous ACTION Inhibit Counter Asynchronous Preset Asynchronously Clear to maximum count NOTES: 1. 0 = Low Level 1 = High Level X = Don’t Care 4. JAM inputs: CD40102BMS; MSD = J7, J6, J5, J4, (J7 is MSB) LSD = J3, J2, J1, J0 (J3 is MSB) CD40103BMS Binary; MBS = J7, LSB = J0 2. Clock connected to clock input 3. Synchronous operation: changes occur on negative-to-positive clock transitions *At zero count, the counters will jump to the maximum count on the next clock transition to “High” 30 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) AMBIENT TEMPERATURE (TA) = +25oC 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 10V 7.5 5.0 2.5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 GATE-TO-SOURCE VOLTAGE (VGS) = -5V 0 -5 -10 -15 -10V -20 -25 -15V -30 FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE (TA) = +25oC OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC 0 0 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 -10V -15V -10 -15 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) Typical Performance Characteristics FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 7-1302 CD40102BMS, CD40103BMS (Continued) PROPAGATION DELAY TIME (tPHL, tPLH) (ns) Typical Performance Characteristics TRANSITION TIME (tTHL, tTLH) (ns) AMBIENT TEMPERATURE (TA) = +25oC 200 150 SUPPLY VOLTAGE (VDD) = 5V 100 10V 15V 50 0 0 20 300 SUPPLY VOLTAGE (VDD) = 5V 200 10V 100 15V 0 40 60 80 100 LOAD CAPACITANCE (CL) (pF) 20 10 AMBIENT TEMPERATURE (TA) = 25oC LOAD CAPACITANCE (CL) = 50pF 7.5 5 2.5 30 40 50 60 70 80 LOAD CAPACITANCE (CL) (pF) 90 100 FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (CLOCK TO CO/ZD) POWER DISSIPATION /PACKAGE (PD) (µW) FIGURE 7. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE MAXIMUM CLOCK INPUT FREQUENCY (fCL MAX) (MHz) AMBIENT TEMPERATURE (TA) = +25oC 105 8 6 4 AMBIENT TEMPERATURE (TA) = +25oC tr, tf = 20ns RL = 200kΩ 2 104 8 6 4 103 SUPPLY VOLTAGE (VDD) = 15V 2 8 6 4 10V 10V 2 102 5V 8 6 4 CL = 50pF 2 CL = 15pF 10 0 5 10 15 2 20 1 SUPPLY VOLTAGE (VDD) (V) FIGURE 9. TYPICAL MAXIMUM CLOCK INPUT FREQUENCY AS A FUNCTION OF SUPPLY VOLTAGE 4 68 2 4 6 8 2 4 6 8 103 10 102 INPUT FREQUENCY (fI) (kHz) 2 4 6 8 104 FIGURE 10. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF FREQUENCY 7-1303 CD40102BMS, CD40103BMS Q CI CI CI D S Q TO GATING Q CL CL CL CL TO GATING Q R SPE SPE J CLR APE CLR FIGURE 11. DETAIL LOGIC DIAGRAM FOR FLIP-FLOPS, FF0 - FF7, USED IN LOGIC DIAGRAMS FOR CD40102BMS AND CD40103BMS CLK CLR CI/CE SPE APE J0 J1 J2 J3 J4 J5 J6 J7 CO/ZD CD40102BMS COUNT 99 98 3 2 1 0 99 98 98 97 8 7 6 5 4 99 98 97 96 CD40103BMS COUNT 255 254 3 2 1 0 255 254 254 253 8 7 6 5 4 255 254 253 252 FIGURE 12. TIMING DIAGRAM FOR CD40102BMS AND CD40103BMS 7-1304 CD40102BMS, CD40103BMS VDD VDD fOUT = fIN ÷ (N + 1) CO/ZD J0 J1 TIME-OUT CO/ZD J0 J1 J2 CI/CE J3 SPE N J2 CI/CE J3 SPE COUNT DOWN N J4 APE J4 APE J5 CLR J5 CLR J6 PRESET J6 J7 CLOCK J7 fIN CLOCK VSS fIN VSS FIGURE 13. DIVIDE-BY- “N” COUNTER FIGURE 14. PROGRAMMABLE TIMER VDD TO MICROPROCESSOR INTERRUPT LINE CO/ZD J0 J1 FROM MICROPROCESSOR DATA BUS J2 CI/CE J3 SPE J4 APE J5 CLR J6 J7 EXT OSC CLOCK PRESET TIMER (I/O COMMAND) VSS FIGURE 15. MICROPROCESSOR INTERRUPT TIMER CD4071BMS* CLOCK ENABLE CI/CE CO/ZD CLOCK CI/CE CO/ZD CLOCK CI/CE CO/ZD CLOCK CASCADED OUTPUT INPUT CLOCK *An output spike (160ns at VDD = 5V) occurs whenever two or more devices are cascaded in the parallel-clocked mode because the clock-to-carry out delay is greater than the carry-in-to-carry out delay. This spike is eliminated by gating the output of the last device with the clock as shown. FIGURE 16. SYNCHRONOUS CASCADING CLOCK ENABLE CI/CE CI/CE CO/ZD CLOCK CO/ZD CLOCK CI/CE INPUT CLOCK VSS VSS FIGURE 17. RIPPLE CASCADING 7-1305 CO/ZD CLOCK CASCADED OUTPUT CD40102BMS, CD40103BMS Chip Dimensions and Pad Layouts CD40102BMS CD40103BMS Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). METALLIZATION: PASSIVATION: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. 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