CD4527BMS CMOS BCD Rate Multiplier December 1992 Features Description • High Voltage Type (20V Rating) CD4527BMS is a low power 4-bit digital rate multiplier that provides an output pulse rate which is the clock input pulse rate multiplied by 1/10 times the BCD input. For example, when the BCD input is 8, there will be 8 output pulses for every 10 input pulses. This device may be used to perform arithmetic operations (add, subtract, divide, raise to a power), solve algebraic and differential equations, generate natural logarithms and trigonometric functions, A/D and D/A conversion, and frequency division. • Cascadable in Multiples of 4-Bits • Set to “9” Input and “9” Detect Output • 100% Tested for Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V For fractional multipliers with more than one digit, CD4527BMS devices may be cascaded in two different modes: the Add mode and the Multiply mode (see Figures 9 and 11). In the Add mode, Output Rate = (Clock Rate) [0.1BCD1 + 0.01BCD2 + 0.001BCD3 + . . .] • Standardized Symmetrical Output Characteristics • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” In the Multiply mode, the fraction programmed into the first rate multiplier is multiplied by the fraction programmed into the second one, Applications 9 10 e.g. • Numerical Control x 4 10 = 36 100 or 36 output pulses for every 100 clock input pulses. • Instrumentation The CD4527BMS is supplied in these 16-lead outline packages: • Digital Filtering • Frequency Synthesis Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4X H1F H6W Pinout Functional Diagram CD4527BMS TOP VIEW BCD RATE SELECT INPUTS “9” OUT 1 16 VDD C 2 15 B D 3 14 A SET TO “9” 4 CLOCK 5 12 CASCADE OUT 6 11 INHIBIT IN (CARRY) INHIBIT OUT (CARRY) 7 10 STROBE VSS 8 9 CLOCK 10 STROBE 12 9 CASCADE INHIBIT 11 (CARRY) IN SET TO 4 NINE 13 CLEAR OUT A B C D 14 15 2 3 CLEAR 13 RATE SELECT LOGIC ÷10 COUNTER 6 5 OUT OUT RATE OUTPUTS “9” OUT 1 7 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-1216 INHIBIT (CARRY) OUT VSS = 8 VDD = 16 File Number 3343 Specifications CD4527BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 VDD = 18V Output Voltage Output Voltage VOL15 VOH15 VDD = 15V, No Load VDD = 15V, No Load (Note 3) LIMITS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 1 +25oC - 10 µA 2 +125oC - 1000 µA 3 -55oC - 10 µA 1 +25oC -100 - nA 2 +125oC -1000 - nA 3 -55oC -100 - nA 1 +25oC - 100 nA 2 +125oC - 1000 nA 3 -55oC - 100 nA 1, 2, 3 +25oC, +125oC, -55oC - 50 mV 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA 1 +25oC 3.5 - mA 1 +25oC - -0.53 mA Output Current (Sink) Output Current (Source) IOL15 IOH5A VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA 1 +25oC - -3.5 mA 1 +25oC -2.8 -0.7 V VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC Output Current (Source) N Threshold Voltage P Threshold Voltage Functional IOH15 VNTH VPTH F VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10µA VOH > VOL < VDD/2 VDD/2 V Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC - 4 V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC 11 - V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 7-1217 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. Specifications CD4527BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Propagation Delay Clock to Output SYMBOL TPHL1 TPLH1 CONDITIONS (NOTE 1, 2) VDD = 5V, VIN = VDD or GND Propagation Delay Clear to Output TPHL2 TPLH2 VDD = 5V, VIN = VDD or GND Propagation Delay Cascade to Output TPHL3 TPLH3 VDD = 5V, VIN = VDD or GND Transition Time Maximum Clock Input Frequency TTHL TTLH GROUP A SUBGROUPS TEMPERATURE VDD = 5V, VIN = VDD or GND FCL VDD = 5V, VIN = VDD or GND LIMITS MIN MAX UNITS 9 +25oC - 300 ns 10, 11 +125oC, -55oC - 405 ns 9 +25oC - 760 ns 10, 11 +125oC, -55oC - 1026 ns 9 +25oC - 180 ns 10, 11 +125oC, -55oC - 243 ns 9 +25oC - 200 ns 10, 11 +125oC, -55oC - 270 ns 9 +25oC 1.2 - MHz 10, 11 +125oC, -55oC .89 - MHz NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC - 5 µA +125oC - 150 µA -55oC, +25oC - 10 µA +125oC - 300 µA VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND Output Voltage VOL VDD = 5V, No Load 1, 2 1, 2 1, 2 - 10 µA +125oC - 600 µA +25oC, +125oC, - 50 mV -55oC, +25oC -55oC Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA -55oC 0.64 - mA Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) Input Voltage Low IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VIL VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V 1, 2 1, 2 1, 2 VDD = 5V, VOUT = 2.5V 1, 2 VDD = 10V, VOUT = 9.5V VDD =15V, VOUT = 13.5V VDD = 10V, VOH > 9V, VOL < 1V 7-1218 1, 2 1, 2 1, 2 +125oC 0.9 - mA -55oC 1.6 - mA +125oC 2.4 - mA -55oC 4.2 - mA +125oC - -0.36 mA -55oC - -0.64 mA +125oC - -1.15 mA -55oC - -2.0 mA +125oC - -0.9 mA -55oC - -1.6 mA +125oC - -2.4 mA -55oC - -4.2 mA +25oC, +125oC, -55oC - 3 V Specifications CD4527BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Input Voltage High SYMBOL VIH CONDITIONS VDD = 10V, VOH > 9V, VOL < 1V NOTES TEMPERATURE MIN MAX UNITS 1, 2 +25oC, +125oC, +7 - V -55oC Propagation Delay Clock to Output TPHL1 TPLH1 Propagation Delay Clear to Output TPHL2 TPLH2 Propagation Delay Cascade to Output Propagation Delay Clock to Out TPHL3 TPLH3 TPHL TPLH 1, 2, 3 +25oC - 150 ns VDD = 15V 1, 2, 3 +25oC - 120 ns VDD = 10V 1, 2, 3 +25oC - 350 ns VDD = 10V VDD = 15V 1, 2, 3 +25 C - 260 ns VDD = 10V 1, 2, 3 +25oC - 90 ns VDD = 15V 1, 2, 3 +25oC - 70 ns TPHL VDD = 5V 1, 2, 3 +25 C - 220 ns 1, 2, 3 +25oC - 110 ns 1, 2, 3 +25oC - 90 ns TPLH Propagation Delay INHIBIT IN to INHIBIT Out TPHL TPLH Propagation Delay Clock to “9” or “15” Out TPHL TPLH Propagation Delay Set to Out Transition Time Maximum Clock Input Frequency Minimum Data Setup Time - Inhibit Minimum Inhibit Removal Time Minimum Clock Pulse Width Maximum Clock Rise and Fall Time TPHL TPLH o VDD = 5V 1, 2, 3 +25 C - 640 ns VDD = 10V 1, 2, 3 +25oC - 290 ns 1, 2, 3 +25oC - 200 ns VDD = 5V 1, 2, 3 +25oC - 500 ns VDD = 10V 1, 2, 3 +25oC - 200 ns VDD = 15V 1, 2, 3 +25oC - 150 ns VDD = 5V 1, 2, 3 +25oC - 260 ns 1, 2, 3 +25oC - 120 ns VDD = 15V 1, 2, 3 +25oC - 90 ns VDD = 5V 1, 2, 3 +25oC - 600 ns VDD = 10V 1, 2, 3 +25oC - 250 ns VDD = 15V 1, 2, 3 +25oC - 180 ns VDD = 5V 1, 2, 3 +25oC - 660 ns VDD = 10V 1, 2, 3 +25oC - 300 ns VDD = 15V 1, 2, 3 +25oC - 220 ns 1, 2, 3 +25oC - 100 ns VDD = 15V Propagation Delay Clock to INHIBIT Out o VDD = 10V VDD = 15V Propagation Delay Clock to INHIBIT Out o VDD = 10V TTHL TTLH VDD = 10V VDD = 15V 1, 2, 3 +25oC - 80 ns FCL VDD = 10V 1, 2 +25oC 2.5 - MHz VDD = 15V 1, 2 +25oC 3.5 - MHz VDD = 5V 1, 2, 3 +25oC - 100 ns VDD = 10V 1, 2, 3 +25oC - 40 ns VDD = 15V 1, 2, 3 +25oC - 20 ns VDD = 5V 1, 2, 3 +25oC - 240 ns VDD = 10V 1, 2, 3 +25oC - 130 ns VDD = 15V 1, 2, 3 +25oC - 110 ns VDD = 5V 1, 2, 3 +25oC - 330 ns 1, 2, 3 +25oC - 170 ns TS TREM TW VDD = 10V TRCL TFCL VDD = 15V 1, 2, 3 +25oC - 100 ns VDD = 5V 1, 2, 3, 4 +25oC - 15 µs VDD = 10V 1, 2, 3, 4 +25oC - 15 µs VDD = 15V 1, 2, 3, 4 +25oC - 15 µs 7-1219 Specifications CD4527BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER SYMBOL Minimum Clear Removal Time TREM Minimum Set Removal Time CONDITIONS NOTES TEMPERATURE MIN MAX UNITS 1, 2, 3 +25oC - 60 ns VDD = 10V 1, 2, 3 +25oC - 40 ns VDD = 15V 1, 2, 3 +25oC - 30 ns VDD = 5V 1, 2, 3 +25oC - 150 ns VDD = 10V 1, 2, 3 +25oC - 80 ns VDD = 5V TREM VDD = 15V Minimum Set or Clear Pulse Width TW 1, 2, 3 +25 C - 50 ns VDD = 5V 1, 2, 3 +25oC - 160 ns VDD = 10V 1, 2, 3 +25oC - 90 ns VDD = 15V Input Capacitance CIN o Any Input o 1, 2, 3 +25 C - 60 ns 1, 2 +25oC - 7.5 pF NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER SYMBOL Supply Current IDD CONDITIONS NOTES TEMPERATURE VDD = 20V, VIN = VDD or GND 1, 4 +25oC VDD = 10V, ISS = -10µA 1, 4 +25oC VDD = 10V, ISS = -10µA 1, 4 +25oC MIN MAX UNITS - 25 µA -2.8 -0.2 V - ±1 V N Threshold Voltage VNTH N Threshold Voltage Delta ∆VTN P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V P Threshold Voltage Delta ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns Functional F VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER Supply Current - MSI-2 Output Current (Sink) Output Current (Source) SYMBOL DELTA LIMIT IDD ± 1.0µA IOL5 ± 20% x Pre-Test Reading IOH5A ± 20% x Pre-Test Reading TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A CONFORMANCE GROUP 7-1220 READ AND RECORD Specifications CD4527BMS TABLE 6. APPLICABLE SUBGROUPS (Continued) CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 Group D MIL-STD-883 METHOD GROUP A SUBGROUPS 100% 5004 1, 7, 9, Deltas 100% 5004 1, 7, 9 READ AND RECORD IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas 100% 5004 2, 3, 8A, 8B, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD Static Burn-In 1 Note 1 1, 5-7 2-4, 8-15 16 Static Burn-In 2 Note 1 1, 5-7 8 2-4, 9-16 Dynamic BurnIn Note 1 - 2, 4, 8, 10, 12-15 3, 16 1, 5-7 8 2-4, 9-16 Irradiation Note 2 9V ± -0.5V 50kHz 25kHz 1, 5-7 9 11 NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V 7-1221 CD4527BMS Logic Diagram VDD 14* A VSS = 8 VDD = 16 15* B 2* VSS C 3* * D 11* INHIBIT IN T C ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK Q A Q * * STROBE CASCADE 10 12 R R1 OUT 6 R2 9* CLOCK T C Q B Q R OUT 5 R3 T C S C Q Q R4 R 4* SET TO “9” “9” T C S D R 1 Q Q 13* CLEAR FIGURE 1. 7-1222 INHIBIT OUT 7 CD4527BMS TRUTH TABLE INPUTS OUTPUTS NUMBER OF PULSES OR INPUT LOGIC LEVEL (0 = Low; 1 = High; X = Don’t Care) NUMBER OF PULSES OR OUTPUT LOGIC LEVEL (L = Low; H = High) D C B A CLK INH IN STR CAS CLR * SET * OUT OUT INH OUT “9” OUT 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 10 10 10 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L 1 2 3 H 1 2 3 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 10 10 10 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 5 6 7 4 5 6 7 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 10 10 10 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 9 8 9 8 9 8 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 10 10 10 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 9 8 9 8 9 8 9 1 1 1 1 1 1 1 1 X X X X X X X X X X X X 10 10 10 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 ** L H ** H *** H 1 1 ** 1 1 1 0 X X X X X X X X X X 10 10 10 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 10 L L 10 H H H H L L L H * Clear and Set Inputs should not be high at the same time; device draws increased quiescent current when in this non-valid state. ** Depends on internal state of counter. *** Output same as the first 16 lines of this truth table (depending on values of A, B, C, D). AMBIENT TEMPERATURE (TA) = +25oC 30 OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) Typical Performance Characteristics GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE (TA) = +25oC 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 10V 7.5 5.0 2.5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS 7-1223 CD4527BMS 0 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V 0 -5 -10 -15 -10V -20 -25 -15V DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 -30 FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE (TA) = +25oC 6 4 SUPPLY VOLTAGE (VDD) = 15V 2 104 8 10V 6 4 10V 2 5V 103 8 6 4 2 2 10 8 6 4 CL = 50pF 2 CL = 15pF 10 2 1 4 68 2 4 68 2 4 68 2 4 68 10 102 103 INPUT FREQUENCY (fIN) (kHz) 2 -10V -10 -15V -15 FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 4 68 200 AMBIENT TEMPERATURE (TA) = +25oC 150 SUPPLY VOLTAGE (VDD) = 15V 10V 100 5V 50 0 20 40 60 80 LOAD CAPACITANCE (CL) (pF) TRANSITION TIME (tTHL, tTLH) (ns) 200 SUPPLY VOLTAGE (VDD) = 5V 100 10V 15V 50 0 0 20 100 FIGURE 7. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (CLOCK OR STROBE TO OUT) AMBIENT TEMPERATURE (TA) = +25oC 150 0 -5 104 FIGURE 6. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF INPUT FREQUENCY 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V PROPAGATION DELAY TIME (tPHL, tPLH) (ns) POWER DISSIPATION PER (PD) (µW) 105 8 AMBIENT TEMPERATURE (TA) = +25oC OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 (Continued) OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) Typical Performance Characteristics 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 8. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE 7-1224 CD4527BMS Applications MOST SIGNIFICANT DIGIT DRM 1 A 0 B 0 C 1 D 1 DRM A OUT 0 B OUT OUT 1 C OUT 0 D CASC. INH. IN INH. IN “9” CLEAR S 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 CLOCK OUT DRM 2 INH. OUT CLOCK CASC. ST 2 0 INH. OUT CLOCK LEAST SIGNIFICANT DIGIT TIMING DIAGRAM SHOWING ONE OF FOUR OUTPUT PULSES CONTRIBUTED BY DRM 2 TO OUTPUT FOR EVERY 100 CLOCK PULSES IN FOR PRESET NO. 94 “9” ST CLEAR S CLOCK FIGURE 9. TWO CD4527BMS’s CASCADED IN THE “ADD” MODE WITH A PRESET NUMBER ( 9 10 DRM 1 OF 94 1 A 0 B 0 C 1 D CLOCK + 4 100 = ) 94 100 DRM 2 0 A OUT 0 B OUT OUT 1 C OUT 0 D INH. OUT CLOCK CASC. CASC. INH. IN INH. IN “9” ST CLEAR “9” ST S INH. OUT CLEAR S CLOCK FIGURE 10. TWO CD4527BMS’s CASCADED IN THE “MULTIPLY” MODE WITH A PRESET NUMBER OF 36 ( 9 10 x 4 100 = 36 100 ) All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 1225 CD4527BMS Timing Diagram 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 CLOCK Qa Qb Qc Qd R1 R2 R3 R4 OUTPUT (PIN 6) A ENABLED B ENABLED C ENABLED D ENABLED INH. OUT OUTPUT (PIN 6) PRESET NO. OF 1 PRESET NO. OF 2 PRESET NO. OF 3 PRESET NO. OF 4 PRESET NO. OF 5 PRESET NO. OF 6 PRESET NO. OF 7 PRESET NO. OF 8 PRESET NO. OF 9 FIGURE 11. (SEE LOGIC DIAGRAM) Chip Dimensions and Pad Layout Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). METALLIZATION: PASSIVATION: BOND PADS: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches 7-1226