APPLICATION NOTE - TDA9901 DIGITAL PROGRAMMABLE GAIN AMPLIFIER DEMONSTRATION BOARD AN/98105 Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD APPLICATION NOTE - TDA9901 DIGITAL PROGRAMMABLE GAIN AMPLIFIER DEMONSTRATION BOARD Author(s): Raymond MAUGIS Application Laboratory - Paris France Keywords TDA9901 Demoboard Digital Programmable Gain Wide-Band Amplifier Date : December 1998 -2- Application Note AN/98105 Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD Application Note AN/98105 SUMMARY This Application Note describes the design and the realization of the DEMO9901 Demonstration board using a TDA9901 with an application environment. The TDA9901 is a Digital Programmable Gain Amplifier (DPGA). In order to obtain the best performances, all the main recommandations which have to be applied to design the Printed Circuit Board are also described. -3- Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD Application Note AN/98105 CONTENTS 1. MAIN FEATURES OF THE TDA9901 5 2. PRINCIPLE AND DESCRIPTION 8 3. OVERALL VIEW OF THE BOARD 10 4. TECHNOLOGICAL CONCEPT 12 5. SPECIAL FEATURES OF THE TDA9901 13 5.1 ANALOG INPUT OF THE AMPLIFIER 13 5.2 REFERENCE VOLTAGES 16 5.3 ANALOG AND DIGITAL POWER SUPPLIES 18 5.4 CLOCK INPUT 19 5.5 GRAY INPUT 24 5.6 ANALOG OUTPUT 26 6. GENERAL POWER SUPPLY 27 7. PERFORMANCES 28 7.1 LOW SIGNAL BANDWIDTH 28 7.2 HARMONIC DISTORTION 29 7.3 LATCHED MODE TIMING DIAGRAM 30 7.4 TRANSPARENT MODE TIMING DIAGRAM 31 8. DEMO-BOARD FILE 31 -4- Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD Application Note AN/98105 1. MAIN FEATURES OF THE TDA9901 The TDA9901 whose the block diagram is shown on Figure 1, is a monolithic BICMOS low noise, wide-band amplifier with differential inputs and outputs. This product can work in Latched mode or Transparent mode under a single 5V supply voltage with a typical consumption of 150mW only. Therefore, the Digital part of the device can be supplied under a reduced supply voltage of 3.3V. The TDA9901 incorporates an AGC function operational between a gain of 6 to 30dB thanks to five CMOS compatible digital control steps (from 3-bit GRAY code) which can operate in transparent mode (direct control of gain setting) or in latch mode (gain setting controlled by latch signal). The TDA9901 is optimized for quick-change of gain settings while preserving a small phase and small amplitude error. Moreover, this device presents an excellent combination of the Noise Figure and good linearity for a wide input frequency range. Therefor this device can be used as simple Multi-purpose amplifier or still in the Linear AGC systems or in the professional application domains such as Radio communications, instrumentation, etc... VDDD 18 GRAY2 TE 2 GRAY1 GRAY0 19 20 CLK 1 3 CLKN DGND 17 4 DECODER LATCHES INP 6 DIGITAL PROGRAMMABLE GAIN AMPLIFIER 15 OUT 6 dB INN 7 14 OUTN 0, 6, 12, 18 or 24 dB CMVGA 5 REFERENCE VOLTAGE REFERENCE VOLTAGE 12 11 VDDA AGND -5- 16 CMADC Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD -6- Application Note AN/98105 - FIGURE 1 - Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD Application Note AN/98105 The TDA9901 is optimized for processing IF signals in Global System for Mobile communications (GSM) Base-Stations or satellite receivers whose the basic architecture of the wideband receiver is shown Figure 2. Band Filter Channel Filter LNA TDA8768 TDA9901 A DPGA Bit-Shift 12-Bit D LO Interstage Filter FS IF Local Oscillator Digital Programmable Gain ( 6 - 30 dB) Sampling Clock - FIGURE 2 - Indeed, thanks to a large bandwidth (125MHz at -3dB cut-off frequency) and dynamic gain, the TDA9901 can drive the analog inputs of an ADC in order to increase and to obtain the required dynamic range of the channels before to Analog to Digital Conversion system. On the other hand, in order to reduce the number of external components required and system cost, the TDA9901 was designed to be easily usable with the 12-bit Analog to Digital Converter type TDA8768 of Philips Semiconductors. In fact, it generates its proper common mode input DC voltage level but also the input DC common mode voltage of the TDA8768. -7- Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD Application Note AN/98105 2. PRINCIPLE AND DESCRIPTION The principle of the Demonstration board, which is described in this Application Note, is shown on Figure 3. The electrical diagram, the part list associated with the implementation scheme are given in the "Demoboard file" chapter of this Application Note. MANUAL GRAY CONTROL EXT. SWITCHING GRAY CODE G0, G1 or G2 change K1 K2 K3 G0 to G2 DVCC K4 TE CLK CMVGA IN RF TRANSFO IN TDA9901 CLKEXT OUTP OUT OUTN OUT IN VDDA 12 V GND POWER SUPPLY BLOCK 5V VDDD 3.3V DVCC DEMO9901 - FIGURE 3 - The different blocks constituting the board are the following : - A power supply constituted by a low power voltage regulator, to supply the DVCC, VDDA, VDDD on all circuitry on the board. - A 50Ω Ω RF transformers to transform the analog signal applied on the "IN" 50Ω SMA connector to symetrical differential mode on the analog inputs INP and INN of the amplifier. - A manual Gray control block to address the static voltage levels on the Gray inputs of the amplifier. -8- Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD Application Note AN/98105 - A TDA9901 Digital Programmable Gain Amplifier used to amplify the analog signal applied on the "IN" 50Ω SMA connector. - A dynamic Gray input with "GRAY" 50Ω SMA connector to change only one bit among three (code Gray definition). - An external clock input with "CLKEXT" 50Ω SMA connector to control the gain in latched mode. The Demonstration board is functional with a single + 8 to 12 Volts external power supply and the different digital input compatibilities are mentionned in the following table : CLKEXT GRAY PECL TTL TTL or CMOS CMOS or LV-CMOS AC coupling SINEWAVE In latched mode ( TE = 0 ) the clock signal is external from a 50Ω generator applied on the "CLKEXT" 50Ω SMA connector. In this case, the gain change is fixed at the rising edge of the clock signal. In transparent mode ( TE = 1 ) In transparent mode, the dynamic clock signal is not necessary, the gain change is directly controlled by the Gray input data pattern when the clock signal is high. Remark : In transparent mode, in order to limit the Electo-Magnetic Interferences level it is advised to take disable the clock source and replace this by a simple high DC level (between 2V to VCC value). -9- Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD Application Note AN/98105 3. OVERALL VIEW OF THE BOARD The whole layout of this Demoboard is shown in Figure 4. CLKEXT + 12V GRAY J1 J3 J2 TM1 G0 G1 G2 Contact Gray code selector GROUND K1 K2 K3 K4 OUTP TP 2 1 Working mode selector Clock TDA9901 IN J5 J6 J4 TM2 OUTN GROUND DEMO9901 - FIGURE 4 The different connection plugs, switches and test-points available on the board are, for : * General power supply - A connector J1 type Phoenix to connect the Demonstration-Board to an external power supply between + 8 V to 12 V and GND. * Evaluation of the TDA9901 - One analog input IN with 50Ω SMA connector J4 to connect the single-ended analog signal applied on the input RF transformer, used to produce a symetrical differential signal applied on the DPGA. -10- Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD Application Note AN/98105 - One external clock input CLKEXT with 50Ω SMA connector J2, associated at two test points TP1/2 to display the clock signal. - One external dynamic Gray input GRAY with 50Ω SMA connector J3 associated to three contact G0, G1 and G2 to change dynamically one bit among the three (G0, G1 and G2). - Three switches K2 to K4 to address the static logic level applied respectively on Gray code input pins G0, G1 and G2 of the DPGA in order to obtain the desired differential gain corresponding to the following table : GRAY INPUT DATA CODE G0 G1 G2 0 0 0 1 0 0 1 1 0 0 1 0 0 1 1 GAIN (dBV) 6 12 18 24 30 - One switch K1 to choose the Transparent or Latched working mode corresponding to the hereunder table : TE WORKING MODE 0 LATCHED 1 TRANSPARENT - Two outputs OUTP and OUTN with two SMA connectors J5 and J6 - Two ground connections TM1 and TM2. -11- Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD Application Note AN/98105 4. TECHNOLOGICAL CONCEPT The practical design has been made on a multilayer Printed Circuit Board of 3.0" x 2.7" size. The technological concept chosen to make this multilayer PCB uses five physical layers as shown Figure 5. The first and fifth layers are the signal layers, the second and fourth layers constitute the ground planes corresponding to signal layers. Moreover, the third layer situated between two ground planes has been provided especially to design the power wiring system. Microstrip matching line Ground plane Signal layer 1 W t H Supply layer εr Dielectric substrate H Ground plane Signal layer 2 - FIGURE 5 The dielectric substrate used is an Epoxy Glass resin having a relative permittivity of 4.7 and a copper thickness (t) of 35 µm. The metallized via hole technic was employed to make all necessary interconnections between layers. The global thickness of the PCB is about 64 mils (1.6 mm) with a thickness (H) between signal layers to respectively ground of 8 mils (0.2 mm). So, all the 50Ω matched lines were designed with the microstrip technology and the width (W= 12.7 mils) of these lines determined from the Kaup’s relation : W= ( 7.475H exp Z C ε r + 141 . ) 87 − t 0.8 Taking into account low switching current in the digital part of the TDA9901 is not necessary to use two separate digital and analog ground planes. On the Demonstration-Board a structure with an electrical single ground was adopted. To avoid ground planes discontinuities of the line technological structure, the supply wiring system of all circuitry has been made on the internal third layer. Moreover, in order to reduce the voltage fluctuation effects, the DC supply currents are driven to the devices by very low characteristic impedance microstrip lines having a small equivalent inductance. On the other hand, in order to satisfy the Electro-Magnetic Compatibility requirements and to ensure a good Power Supply Rejection Ratio on the different supply pins and to suppress an eventual close-in coverage risk, each supply line close to DPGA is wideband bypassed (see Chapter 5 § 3). -12- Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD Application Note AN/98105 5. SPECIAL FEATURES OF THE TDA9901 In order to obtain the optimal performances, the advised Application scheme of the TDA9901 is shown on the Figure 25 on the ”Demoboard file” chapter. However, several requirements must be satisfied about the following specific points described in this chapter. 5.1 ANALOG INPUT OF THE AMPLIFIER In order to improve the analog signal to noise ratio, a differential structure with an intrinsic low input offset voltage was designed on the TDA9901 analog input. A wideband RF transformer is used to make the adaptation between the single-ended Analog input of the DemonstrationBoard and the differential analog inputs of the DPGA as shown on Figure 6. CMVGA 1:1 C IN IN 100nF Zg R R INN - FIGURE 6 The recommended DC common mode voltage is internally fixed on the DPGA analog inputs IN and INN from the 2.7V internal reference voltage available on the CMVGA pin . A frequency decoupling of maximum 100nF was added on the middle point of the transformer secondary, to get a good "dynamic" ground. The dynamic analog signal is connected through a 220nF AC coupling to the input RF transformer via a short 50Ω microstrip matched line and a SMA plug-in connector. In fact, in order to preserve a good signal to noise ratio, a recommended low impedance matching must be located at the input transformer. So, the symetrical and differential analog signal is applied on the analog inputs INP and INN of the DPGA. The secondary load R of the RF transformer was fixed to 100Ω in order to ensure a 50Ω matching with regard to an analog virtual ground. Thereby, with a transformer ratio of n=1, the impedance brought back at the primary is equal to R value and the impedance matching to the external generator is performed with a resistor of 100Ω in parallel on the primary of the transformer. The combination of the capacitor C and the equivalent impedance (R/2) located on primary transformer form a high- -13- Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier Application Note DEMONSTRATION BOARD AN/98105 pass filter whose the -3dB cut-off frequency is determined by following equation : F3dB=1 / π R C. -14- Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD Application Note AN/98105 Note : On the other hand, by the using of a transformer ratio (n) higher than unity, the brought back impedance Zb at the primary is given by following relation : Zb = R / n2 Note : The Digital Programmable Gain Amplifier TDA9901 can be used with a single-ended AC coupled analog input, in this condition the proposed diagram is shown on Figure 7. 100nF RIN C IN INN IIH TDA9901 CMVGA INP - FIGURE 7 - In order to reduce the input noise, it is advised to employ a low RIN value. Therefore, in order to limit the offset voltage between the differential inputs of the device, the RIN value will must be computed taking into account the maximum absorbed analog input current value (55µA). In this condition the true common mode voltage value VICOM obtained on the differential inputs is given from the relation : VICOM = VCMVGA - RIN . I IH . The combination of the capacitor C and resistor RIN form a high-pass filter, consequently, the following condition 1 / C ω << RIN must be respected for the whole analog bandwidth. -15- Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD Application Note AN/98105 5.2 REFERENCE VOLTAGES In order to reduce the complexity of the systems, two reference voltages are designed inside the device. These reference voltages are directly available on specific output pins CMVGA and CMADC with a respectively typical regulated voltage value of 2.7 and 3.54 Volts. As shown Figures 6 and 7, the internal reference voltage CMVGA of 2.7V is used to ensure the Common Mode Voltage on the analog inputs of the TDA9901. The output pin CMVGA will be wideband bypassed with a minimum capacitor value of 100nF. The output reference voltage VCMADC of 3.54V supplied on CMADC pin of the device, can be used when the Digital Programmable Gain Amplifier TDA9901 will drive, a differential analog input signal to TDA8768 Analog to Digital Converter of Philips Semiconductors as shown Figure 8. 100nF TDA9901 CMADC RL RL C OUT VICOM IIH To ADC inputs OUTN C - FIGURE 8 - The output signal is AC coupling on the ADC inputs, consequently, the reference voltage VCMADC ensures the common mode voltage VICOM of the differential analog inputs of the TDA8768 through the dynamic load RL of the device. Taking into account high level analog input current IIH of the TDA8768 (about published typical value 10µA), the common mode voltage VICOM can be evaluated from the relation : VICOM = VCMADC - RL . IIH -16- Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD Application Note AN/98105 Note : The TDA9901 can drive an other ADC that TDA8768, in this case, an other common mode voltage will can be required. Consequently, the hereunder diagram shown Figure 9 can be realized in order to obtain the required common mode voltage value. 1kΩ R1 R2 1kΩ - 100nF NE5230 1kΩ TDA9901 100nF + CMADC Rp RL C RL OUT VICOM IIH To ADC inputs OUTN C - FIGURE 9 - Indeed, the reference voltage VCMADC supplied from TDA9901 is used as reference source to create an other reference voltage voltage V+ , which can be adjusted thanks to potentiometer Rp on the no-inverter input of the single supply Operational Amplifier type NE5230 of Philips Semiconductors. Consequently, we have : V+ = k .VCMADC with 0<k<1 The Op Amp. is powered from +5V supply, with a non-inverting DC gain of 2. Consequently, the common mode voltage VICOM obtained on the resistor load RL is given from the following relationship : R1 + R2 VICOM = k ⋅ VCMADC ⋅ − R L ⋅ I IH R1 -17- Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD Application Note AN/98105 5.3 ANALOG AND DIGITAL POWER SUPPLIES In order to obtain a good dynamic rejection on the DPGA supply pins, the Analog VDDA and Digital VDDD supply lines are addressed to the supply pins, of the DPGA, through two SMD bypass pi filters as shown by the schematic supply diagram of Figure 10. DVCC + 3.3V To digital part 330nF 3.3V TDA9901 VDDD 100nF 82 VDDA R BZX84C/ 3V3 5.0V 330nF 100nF AVCC + 5V - FIGURE 10 - These bypass pi filters are implanted near the DPGA to separate each power supply of the device. Moreover, the PCB layout has been designed so that the power supply line end arrives close to the VDDA and VDDD sides. These points are perfectly decoupled with 330nF and 100nF ceramic capacitors close to respective supply pin of the device. On the DemonstrationBoard, the digital part of the device is supplied under VDDD of 3.3V from stabilized voltage DVCC obtained from a Zener diode type BZX84C/3V3 of Philips Semiconductors. Therefore, in order to ensure a good stability on DVCC and VDDD voltages, a resistor R allows to limit the current in Zener diode at about to ten times as big than digital consumption of the device. -18- Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD Application Note AN/98105 5.4 CLOCK INPUT In order to obtain a changing gain in latched mode, the TDA9901 must be used with an clock signal. The differential clock inputs of the device are internally biased to ensure a TTL compatibility with a threshold voltage about 1.4V and a large equivalent input impedance (higher than 100kΩ). In fact, a flexible clocking compatibility is possible with of simple interface circuits. Consequently, the DPGA can work also with Logic Standard PECL or with the minimum condition AC driving mode as mentionned in the following table : MODE PECL AC CLK CLKN PECL 3.65 V (DC) 3.65 V (DC) PECL PECL PECL 0.5 Vp.-p 2.5 V (DC) 2.5 V (DC) 0.5 Vp.-p 0.25 Vp.-p 0.25 Vp.-p The required PECL limit levels and AC amplitude on the clock pins of the device are the following : MODE VIL VIH PECL 3.52 V 3.83 V 0.5 V p.-p AC When TTL or PECL clock signal is used, in order to reduce the Electro-Magnetic Interference Bandwidth, it is preferable to limit the clock transient values (rise and fall time higher than 0.75ns). In fact, in Radio communication Applications where an effective reduction of the Spurious Free Dynamic Range (SFDR) is very important, an AC coupling Sinewave clock signal is advised. -19- Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD Application Note AN/98105 The Demonstration-Board is designed to be functional in latched mode with a single-ended DC coupled PECL or TTL clock signal from an external 50Ω generator as shown Figure 11. 2.5V DC 50Ω 50Ω SW external clock signal L 100 µH CLKN C CLK DC-Block TDA9901 CLK L 100 µH CLKN C 100nF TDA9901 PECL external clock signal 100nF - FIGURE 11 - - FIGURE 12 - The DC offset voltage is restored on the CLKN pin from the average PECL level, thanks to a Low-pass filter LC. In order to ensure a good dynamic rejection on complementary clock input a high inductance value (100µH) associated to the decoupling capacitor C, is required. In order to ensure a good matching of the 50Ω external generator at the clock frequency (Fc ), the following condition must be respected : L ω C >> 50Ω On the other hand, to obtain an AC coupling clock mode from an external Sinewave 50Ω generator as shown Figure 12, it is possible to add an external DC-block on the CLKEXT of the Demonstration-Board. This will be connected to an external voltage source of 2.5V to ensure the offset voltage required with this clock mode. Note 1 : On the diagram of the Figure 11, the suppression of the inductance L allows to obtain directly the TTL clock compatibility. In this case, the TTL threshold is internally restored on CLKN pin which must be bypassed to ground with decoupling capacitor of 100 nF. -20- Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD Application Note AN/98105 Note 2 : Another option for AC-coupling is shown on the diagram Figure 13. +5V R C SW clock source L CLKN TDA9901 CLK R 100nF - FIGURE 13 - The dynamic equivalent clock input circuit is shown on the hereunder diagram : Z0 C CLK INPUT L SW generation clock circuit R At the frequency clock Fc , the following condition must be repected : 1 << Z IN Cω c with, Z IN = RL ω c R 2 + L2ω c 2 Therefore, if the value of the resistor R is sufficiently high, the inductance value L will can be choose in order to obtain the matching impedance on the output generation clock circuit. -21- Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD Application Note AN/98105 Note 3 : Use Pseudo-ECL (PECL) as interfacing single-ended clock circuit is possible as shown Figure 14, where a PECL tranceiver used to drive the clock signal to DPGA. PECL levels D CLK Q PECL D L Q CLKN 100µH VBB 100nF 270Ω 100nF TDA9901 270Ω - FIGURE 14 The PECL tranceiver is fully powered under +5V and the active PECL output load will must be placed close to CLK pin of the DPGA. The offset voltage is restored on CLKN pin through the inductance L (100µH) and the decoupling capacitor (100nF) from complementary PECL output. Nevertheless, a such practical configuration can be made when the transmission line, between PECL output and CLK pin, will be lower than one inch. Beyond, the transmission line will match to 50Ω dymamic load as shown on the diagram of the Figure 15. 100nF 220Ω Z C = 50Ω PECL levels D PECL D L Q CLKN 100µH VBB 100nF CLK Q TDA9901 50Ω 100nF 270Ω - FIGURE 15 - -22- Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD Application Note AN/98105 Note 4 : A differential PECL clock mode can be also used to drive the DPGA clock input as shown Figure 16. 270Ω PECL levels CLK Q PECL D Q CLKN VBB 270Ω TDA9901 D 100nF - FIGURE 16 A low skew PECL tranceiver can be employed to transfer directly the PECL levels from output tranceiver to differential clock inputs of the device. Nevertheless, in order to preserve a duty cycle low skew on the differential clock signal, the transmission lines will must be of same lengh and sufficiently short ( 1 inch). Moreover, in order to avoid the over/undershoots on the transient clock signals, the lengh open lines located between the PECL output load and the clock pins will must be reduced as possible. Note 5 : If the practical configuration requires of long transmission lines, these must be 50Ω matched to dynamic PECL loads as before mentioned (see note 3 and figure 15). For each line the dynamic equivalent diagram is shown on the hereunder figure : R0 ZC ( 6Ω ) 50Ω PECL OUTPUT Vin = ( VOH - VOL ) VPECL 100nF -23- 220Ω ZC R0 + ZC Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD Application Note AN/98105 5.5 GRAY INPUT On the Demonstration-Board, the DPGA can be switched between two consecutive gains only with a difference of ± 6dBV between 6 to 30dBV value. Thereby, three Low Voltage CMOS compatible Gray code inputs GRAY0, GRAY1 and GRAY2 pins are specially provided on the device. So, as shown on Figure 17, thanks to three switches (K2 to K4) a static level DVCC (3V) or GROUND (0V through 50Ω resistor) according to hereunder Gray coding table, is applied on each GRAY input (GRAY0, GRAY1 and GRAY2) to fix a particular gain value. In this case the gain value can be fixed or changed manually only and no dynamic signal is applied on 50Ω Ω SMA connector (J3). GRAY INPUT DATA CODE GRAY0 GRAY1 GRAY2 0 0 0 1 0 0 1 1 0 0 1 0 0 1 1 GAIN (dB) 6 12 18 24 30 For example, Figure 17 a differential gain of 24dBV is programmed, by a changing position of K2 the gain will be reduced of 6dB. In the same way, if the position of K3 change, the gain value increase of 6dB. + 3.0V G0 GRAY K4 K2 G1 K3 J3 50 Ω 50Ω 50 Ω G2 GRAY1 TDA9901 GRAY0 GRAY2 - FIGURE 17 - -24- Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD Application Note AN/98105 On the other hand, a change gain can be also obtained dynamically from a low frequency LVCMOS compatible signal applied on GRAY SMA input (J3). Indeed, this signal can be driven to one GRAY input among the three of the device (GRAY0, GRAY1 and GRAY2) thanks to a specific contact G0, G1 or G2. Nevertheless, in this condition, the switched GRAY input must be imperatively shorted to 50Ω thanks to the relevant switch as shown on Figure 18 where a change gain of 18 to 24 dBV is obtained, by changing dynamically the level on GRAY0 input pin. + 3.0V G0 GRAY K4 K2 G1 K3 J3 50Ω 50Ω 50Ω G2 GRAY1 TDA9901 GRAY0 GRAY2 - FIGURE 18 - -25- Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD Application Note AN/98105 5.6 ANALOG OUTPUT TDA9901 On the Demonstration-Board, the output DC voltage is about 2.7V. The AC coupled outputs are loaded by minimum resistor of 680Ω referenced to the ground (higher value can be also used), as shown on Figure 19. C OUT OUTN C RL RL - FIGURE 19 - In this condition, the maximum dynamic single-ended output signal available on each High Impedance SMA connector is : 1Vp.-p. The combination of the capacitor C and the resistor load RL form a high-pass filter whose the 3dB cut-off frequency is determined by following equation : F-3dB=1 / 2 π RL C. Note : To limit the large analog banwidth of the DPGA an output band-pass filter can be added. In this case, the specified output impedance of the DPGA (typical value of 15Ω ) must be taken into account to design the output filter. -26- Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD Application Note AN/98105 6. GENERAL POWER SUPPLY The proposed electrical diagram is shown Figure 20. This circuit uses a low current adjustable voltage regulator type LM317LD of SGS-Thomson in SMD package SO8. This one allows to obtain the voltage VCC necessary to supply the VDDA and VDDD from an external power unit of 9V/0.5A, (the external voltage can be comprised between 7 and 10 Volts). The SMD type BYD17G Silicium diode D1 ensures protection for all circuitry from reverse polarities and C1 ensures a low frequency decoupling made before the supply line network distributed to regulators. Under the external power supply nominal value + 9 Volts, the consumption is lower than 200mA. 7 to 10 V D1 VCC 5V OUT VIN LM317LD GND C1 + 22µF ADJ R5 VREF 1µF 240Ω 1µF R6 750Ω - FIGURE 20 - In order to obtain a Low voltage value of VCC the value of the resistor R6 must satisfy the following relation : VCC = VREF . R5 + R6 R5 with R4 = 240Ω fixed we obtain : VCC R6 = R5 ⋅ − 1 VREF thus, R6 = 750 Ω The input and output decoupling capacitors of 1µF were implanted close to the respective pin of the regulator. -27- Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD Application Note AN/98105 7. PERFORMANCES An evaluation of the performances of the TDA9901 Digital Programmable Gain Amplifier has been made on the dynamic test bench, with Demonstration Board environment. 7.1 LOW SIGNAL BANDWIDTH An evaluation has been made for all gain values with the following conditions and measurement set-up shown Figure 21 : Analog input signal : VIN = -30 dBm = Cte Dynamic output load : RL = 680 Ω Measurement : Output single mode OUTP 1X 100 kΩ 3 pF RL IN 50 Ω SPECTRUM ANALYZER RL OUTN DEMO9901 50Ω 50Ω FET PROBE TEK- P6201 TRACKING GENERATOR TEK - TR503 50Ω TEK 496 0.1 to 1800 MHz - FIGURE 21 The results obtained at -3 dB cut-off-frequency are mentionned on the hereunder table : Programmed Gain position ( dBV ) Single Output Gain ( dBV ) Bandwidth ( MHz ) 6 12 18 24 30 0 6 12 18 24 125.0 The low signal bandwidth is totally independent of the Amplifier Gain value. -28- Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD Application Note AN/98105 7.2 HARMONIC DISTORTION The measurement set-up used to evaluate the Harmonic Distortion of the DPGA is shown on Figure 22, and the measurement conditions are the following : Analog single output signal : Vo = 1 Vp.-p = Cte. Gain position : 24dBV Dynamic output load : RL = 680Ω Measurement : Output differential mode. OUTP IN LP Filter 6th order HP8644A SYNTHETIZED SIGNAL GENERATOR Differential probe Lecroy AP033 RL 50Ω SPECTRUM ANALYZER 10X- 3pF RL OUTN DEMO9901 50Ω Power Module HP- ESA- L1500A 9kHz to 1.5GHz - FIGURE 22 The results obtained on the second and third harmonics of the different analog frequencies up to 20MHz are mentionned in the below table : FIN (MHz) H2 (dB) H3 (dB) 0.50 4.43 12.50 21.40 - 69.9 - 73.8 - 74.7 - 72.2 - 71.0 - 64.0 - 64.5 - 71.5 The Harmonic Distorsion performances are guaranted for all gain positions and 2Vp.-p differential output signal up to about 20MHz, only. -29- Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD Application Note AN/98105 7.3 LATCHED MODE TIMING DIAGRAM The timing diagram obtained with the following measurement conditions is shown on Figure 23. Analog frequency : FIN = 4.43 MHz Clock frequency : FCLK = 52 MHz Gray frequency Output signal : FGRAY = 200 kHz : V0 = 1 Vp.-p 5ns/div tp tset 0.5 V/div AC 1 V p.-p Output single 3.8 V 0.5V/div PECL clock signal DC 3.2 V - FIGURE 23 - For all changing gain, in latched mode (TE = 0) the gain change is fixed at the rising edge of the clock input and the different timing obtained are the following : Propagation delay time : tp = 5.1 ns Gain settling time : tset = 3 ns -30- Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD Application Note AN/98105 7.4 TRANSPARENT MODE TIMING DIAGRAM The timing diagram obtained with the following measurement conditions is shown on Figure 24 ( for 0 to 6dBV gain changes ) and Figure 25 ( for 18 to 24dBV gain changes ) : Analog frequency : FIN = 4.43 MHz Output signal Gray frequency : FGRAY = 200 kHz : V0 = 1 Vp.-p (single mode) 5ns/div tp t set 0.5 V/div 1 Vp.-p Output single AC 2V/div Gray code changes DC 0V Transparent mode : Gain changes 0 to 6 dBV - FIGURE 24 - In transparent mode (TE = 1), the gain settling is directly controlled by the input Gray data pattern. For a changing gain of 0 to 6dBV (or 6 to 12dBV in output differential mode) the different timings obtained are the following : Propagation delay time : tp = 6.5 ns Gain settling time : tset = 5.2 ns -31- Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD Application Note AN/98105 5 ns/div tp tset 0.5 V/div AC 1 Vp.-p Output single 2 V/div DC Gray code changes 0V Transparent mode : Gain changes 18 to 24dBV - FIGURE 25 - For a changing gain of 18 to 24dBV (or 18 to 30dBV in output differential mode) the different timings obtained are the following : Propagation delay time : tp = 5.0 ns Gain settling time : tset = 4.0 ns -32- Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD Application Note AN/98105 8. DEMO-BOARD FILE The following documents are shown on Figures 26 to 32: - Electrical diagram. - Double sided layout. - Internal ground planes. - Internal layer supply layout. - Double sided components implantation. The part list with the values and references of all components is given in the Table1. -33- 1 J1 12 V 2 J1 GND J 4 D1 22 u F A DJ R6 750 1 VI N 2 V OU T 1 3 V OU T 2 4 R1 I C2 4 5 6 8 7 6 5 D2 DVCC 3 3 TR1 MC L T 1 _ 6 T _ K K 8 1 NC2 V OU T 4 V OU T 3 NC1 L M3 1 7 L D C5 1uF 220nF C1 T M2 100 1 2 3 2 PF1 PF2 2 51 R2 1 1 2 3 4 5 6 7 8 9 10 1 5 1 R7 I C1 DA T E : 0 9 8 7 6 5 4 3 2 1 K4 100 nF R . MA U G I S J 5 OU T P J 3 GR A Y OUT N J 6 C O MP O S A N T S 47n F C3 C2 47 nF G2 G1 G0 Pa r t : Pr o j : D E MO 9 9 0 1 TDA9 9 0 1 A. L . P. A. R P HI L I PS GR A Y1 2 GR A Y2 1 V D DD 1 1 V S SD 1 C MA D C OUT 1 OU T N 1 N C4 1 V S SA 1 V D DA 1 5 1 15- 0 6- 98 Au t h o r : P HI L I P S GR A Y 0 TE CL K CL K N C MV G A I N I NN NC 1 NC 2 NC 3 K3 R9 DV C C TP2 C1 1 DV C C CL K TP1 R10 1 00uH 100 R8 T DA 9 9 0 1 M K1 1 00nF 5 1 C8 100 nF J 2 B YD1 7 G I N R5 680 6 80 C L KE X T C4 240 C7 L1 10 0nF T M1 R1 1 C6 3 V3 BZX8 4C 82 1u F C9 33 0 n F C1 0 TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD 3 30 n F V D DD VDDA VDDD V D DA -34- C13 R3 R4 K2 Philips Semiconductors Application Note AN/98105 - FIGURE 26 - Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD Application Note AN/98105 OVERSIDE LAYOUT - FIGURE 27 - UNDERSIDE LAYOUT - FIGURE 28 - -35- Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD Application Note AN/98105 INTERNAL SUPPLY PLANE - FIGURE 29 - INTERNAL GROUND PLANES - FIGURE 30 - -36- Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD Application Note AN/98105 OVERSIDE COMPONENTS IMPLANTATION - FIGURE 31 - -37- Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD Application Note AN/98105 UNDERSIDE COMPONENTS IMPLANTATION - FIGURE 32 - -38- Philips Semiconductors TDA9901 - Digital Programmable Gain Amplifier DEMONSTRATION BOARD Application Note AN/98105 REFERENCES VALUES CODE NUMBER MANUFACTURER IC1 IC2 AMPLIFIER REGULATOR TDA9901 LM 317LD PHILIPS SGS-THOMSON D1 D2 SMD DIODE SMD ZENER DIODE BYD17G BZX84C/3V3 PHILIPS - TR1 RF TRANSFORMER MCLT1-6T-KK81 MINI CIRCUIT BP1 BP2 PI FILTER 2nF - 4700- 003-S - TUSONIX - L1 SMD SELF 100µH LQH1N101K04 MURATA J1 J2 to J4 J5 - J6 EDGE 50Ω-SMA - MKSD 1.5/2-5.08 R125 426 R125 680 PHOENIX CONTACT RADIALL - K1 to K4 SWITCH 1C/2P 09 03201 02 SECME G0 to G2 2.54 - STRAP M7566-06 HARWIN TP1 - TP2 TM1 TM2 TEST POINT BOLT HOLD 3850358102400 3110415000530 COMATEL - C1 C2 - C3 C4 C5 - C6 C7 - C8 C9 - C10 C11 - C13 SMD 220nF SMD 47nF 22µF/16V SMD 1µF SMD 100nF SMD 330nF SMD 100nF C0805 293D226X9016D C1812 C0805 - PHILIPS SPRAGUE PHILIPS - R1 - R2 R3 - R4 R5 R6 R7 to R10 R11 SMD 100Ω SMD 680Ω SMD 240Ω SMD 750Ω SMD 51Ω SMD 82Ω 0805 - PHILIPS - - TABLE 1 - -39-