INTEGRATED CIRCUITS DATA SHEET TDA9901 Wideband differential digital controlled variable gain amplifier Product specification Supersedes data of 1998 Apr 15 File under Integrated Circuits, IC02 1999 Oct 08 Philips Semiconductors Product specification Wideband differential digital controlled variable gain amplifier TDA9901 FEATURES GENERAL DESCRIPTION • 130 MHz, −3 dB small signal bandwidth The TDA9901 is a wideband, low noise amplifier with differential inputs and outputs. The TDA9901 incorporates an AGC function with digital control. The TDA9901 is optimized for fast switching between different gain settings, preserving small phase and amplitude error. • Digitally controlled gain • TTL/CMOS compatible digital inputs (3.3 or 5 V) • TTL single ended or differential clock input with PECL compatibility The TDA9901 presents an excellent combination of low noise and good linearity for a wide input frequency range. • 24 dB gain control range • Five steps of 6 dB plus 6 dB fixed gain The TDA9901 is optimized for processing IF signals in GSM base stations. It is also suited for many other applications as a general purpose digitally controlled variable gain amplifier. • 30 dB gain maximum • High impedance differential inputs • Low impedance differential outputs • High power supply rejection The TDA9901 is able to operate from 4.75 to 5.25 V supply for the analog part and from 3.0 to 5.25 V for the digital part. • 125 nV/√Hz output voltage noise density at 30 dB gain • Fast gain settling • Dual control modes: transparent or latched. APPLICATIONS • Linear AGC systems • IF amplifier in IF conversion systems (e.g. base stations or satellite receivers) • Instrumentation • Multi-purpose amplifier • Driver for differential ADCs (e.g. TDA8768). QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. VDDD digital supply voltage 3.0 3.3 5.25 V IDDA analog supply current − 30 36 mA IDDD digital supply current − 3.0 5.0 mA Gdif differential gain Ptot total power dissipation 5.25 UNIT analog supply voltage −3 dB small signal bandwidth 5.0 MAX. VDDA B−3dB 4.75 TYP. V minimum gain 5.7 6.11 6.46 dB maximum gain 29.3 30.5 31.5 dB Vo(dif)(p-p) = 0.125 V; Tamb = 25 °C 110 130 − MHz − 160 216 mW ORDERING INFORMATION TYPE NUMBER TDA9901TS 1999 Oct 08 PACKAGE NAME DESCRIPTION VERSION SSOP20 plastic shrink small outline package; 20 leads; body width 4.4 mm SOT266-1 2 Philips Semiconductors Product specification Wideband differential digital controlled variable gain amplifier TDA9901 BLOCK DIAGRAM VDDD TE handbook, full pagewidth 18 GRAY2 GRAY1 19 20 2 GRAY0 CLK CLKN VSSD 1 3 17 4 DECODER LATCHES TDA9901 IN INN 6 15 7 14 6 dB 0, 6, 12, 18 or 24 dB CMVGA 5 REFERENCE GENERATOR 11 REFERENCE GENERATOR 8, 9, 10, 13 16 12 MGM962 VDDA n.c. Fig.1 Block diagram. 1999 Oct 08 3 OUT OUTN VSSA CMADC Philips Semiconductors Product specification Wideband differential digital controlled variable gain amplifier TDA9901 PINNING SYMBOL PIN DESCRIPTION GRAY0 1 digital control signal bit 0 input (LSB) TE 2 transparent enable input CLK 3 clock input for gain control setting CLKN 4 inverting clock input for gain control setting (active low) CMVGA 5 regulator output common mode VGA input IN 6 non-inverting analog input INN 7 inverting analog input (active low) n.c. 8 not connected n.c. 9 not connected n.c. 10 not connected VDDA 11 analog supply voltage INN 7 14 OUTN VSSA 12 analog ground n.c. 8 13 n.c. n.c. 13 not connected n.c. 9 12 VSSA OUTN 14 inverting analog output (active low) n.c. 10 OUT 15 non-inverting analog output 11 VDDA CMADC 16 regulator output common mode ADC input VSSD 17 digital ground VDDD 18 digital supply voltage GRAY2 19 digital control signal bit 2 input (MSB) GRAY1 20 digital control signal bit 1 input handbook, halfpage GRAY0 1 20 GRAY1 TE 2 19 GRAY2 CLK 3 18 VDDD CLKN 4 17 VSSD 16 CMADC CMVGA 5 TDA9901TS IN 6 15 OUT MGM963 Fig.2 Pin configuration. FUNCTIONAL DESCRIPTION The TDA9901 provides a digitally controlled variable gain function for high-frequency applications. The TDA9901 can be operated in two different modes, depending on the value at pin TE. When TE is at logic 1, the gain can be instantly controlled when the clock signal is HIGH (transparent mode). The gain is fixed during the LOW period of the clock. When TE is at logic 0 the gain of the TDA9901 is changed at the rising edge of the clock signal. 1999 Oct 08 4 Philips Semiconductors Product specification Wideband differential digital controlled variable gain amplifier TDA9901 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VDDA analog supply voltage −0.3 +7.0 V VDDD digital supply voltage −0.3 +7.0 V ∆VDD supply voltage difference between VDDA and VDDD −1.0 +4.0 V VI input voltage level −0.3 +7.0 V IO output current − 10 mA Tstg storage temperature −55 +150 °C Tamb ambient temperature −40 +85 °C Tj junction temperature − 150 °C HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS thermal resistance from junction to ambient in free air VALUE UNIT 120 K/W CHARACTERISTICS VDDA = V11 to V12 = 4.75 to 5.25 V; VDDD = V18 to V17 = 3.0 to 5.25 V; VSSA and VSSD shorted together; Tamb = −40 to +85 °C; typical values measured at VDDA = 5.0 V; VDDD = 3.3 V and Tamb = 25 °C; unless otherwise specified; note 1. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDA analog supply voltage 4.75 5.0 5.25 V VDDD digital supply voltage 3.0 3.3 5.25 V ∆VDD voltage difference between VDDA and VDDD −0.2 − +2.5 V IDDA analog supply current − 30 36 mA IDDD digital supply current − 3.0 5.0 mA Variable gain amplifier transfer characteristics B−3dB −3 dB small signal bandwidth Vo(dif)(p-p) = 0.125 V; Tamb = 25 °C 110 130 − MHz td(g) group delay time up to fi = 20 MHz; minimum gain; Tamb = 25 °C − 2.5 − ns ∆td(g) group delay difference 6 dB gain step; Tamb = 25 °C − − 300 ps 1999 Oct 08 5 Philips Semiconductors Product specification Wideband differential digital controlled variable gain amplifier SYMBOL PARAMETER TDA9901 CONDITIONS MIN. tst settling time 10 to 90% maximum − output transition; CL(max) = 5 pF on each output; Tamb = 25 °C Gstep gain step size DC input TYP. MAX. UNIT − 3.6 ns Tamb = 25 °C 5.88 6.09 6.28 dB all temperatures 5.6 6.09 6.56 dB Tamb = 25 °C 5.76 6.11 6.40 dB all temperatures 5.7 6.11 6.46 dB Tamb = 25 °C 29.9 30.5 30.9 dB all temperatures 29.3 30.5 31.5 dB gain stability as a function minimum gain of temperature maximum gain − −1.0 − mdB/°C − −7.5 − mdB/°C |∆G/∆VDD| gain stability as a function minimum gain of power supply − 15 25 mdB/V ∆Vi(offset) input offset voltage difference 6 dB gain step − 0.8 − mV F noise figure Rs = 100 Ω; fi = 20 MHz minimum gain − 29.1 − dB maximum gain − 9.9 − dB G = 6 dB − 75 − nV/√Hz G = 12 dB − 82 − nV/√Hz G = 18 dB − 97 − nV/√Hz G = 24 dB − 91 − nV/√Hz G = 30 dB − 124 − nV/√Hz 0 to 20 MHz − 57 − dB 20 to 100 MHz − 39 − dB G(min) G(max) ∆G/∆T Vn(o)(eq) PSRR(VDDA) PSRR(VDDD) CMRR 1999 Oct 08 minimum gain setting maximum gain setting equivalent output noise voltage spectral density DC input DC input Rs = 100 Ω; fi = 20 MHz; Tamb = 25 °C power supply ripple rejection of VDDA minimum gain power supply ripple rejection of VDDD minimum gain common mode rejection ratio dB 0 to 20 MHz − 67 − dB 20 to 100 MHz − 51 − dB 0 to 20 MHz − 75 − dB 20 to 150 MHz − 45 − dB 6 Philips Semiconductors Product specification Wideband differential digital controlled variable gain amplifier SYMBOL PARAMETER TDA9901 CONDITIONS MIN. TYP. MAX. UNIT Analog inputs Vi(max)(p-p) maximum input voltage (peak-to-peak value) minimum gain − 1.0 − V maximum gain − 60.4 − mV 2.0 2.7 VDDA − 1.9 V Vi(cm) common mode input voltage Ii input current − 55 − µA Ri input resistance 10 − − kΩ Ci input capacitance − − 5 pF Vi(cm) = 2.7 V Analog outputs; note 2 maximum differential output voltage (peak-to-peak value) maximum gain 2.0 − − V minimum gain 2.0 − − V Vo(cm) common mode output voltage referenced to VDDA; Tamb = 25 °C VDDA − 2.56 VDDA − 2.42 VDDA − 2.29 V ∆Vo(cm)/∆T common mode output voltage variation with temperature − −1.8 − mV/°C SRo(se) single-ended output slew rate − 275 − V/µs Ro output resistance − 15 26 Ω Co output capacitance − 3 − pF Vo(max)(p-p) Variable gain amplifier dynamic performance; CL = 5 pF; RL = 680 Ω (see Figs 6, 7, 8, 9 and 10) HD2 HD3 ∆HD3/∆T 2nd harmonic distortion 3rd harmonic distortion Vo = Vo(max) fi = 0.5 MHz − −80 −67 dBc fi = 4.43 MHz − −77 −67 dBc fi = 12.5 MHz − −76 −65 dBc fi = 21.4 MHz − −74 −62 dBc fi = 0.5 MHz − −64 −60 dBc fi = 4.43 MHz − −64 −59 dBc fi = 12.5 MHz − −62 −58 dBc fi = 21.4 MHz − −61 −57 dBc − 80 − mdB/°C Vo = Vo(max); Tamb = 25 °C 3rd harmonic distortion fi = 21.4 MHz variation with temperature Reference voltage output ADC: pin CMADC Vref(CMADC) ADC reference output voltage referenced to VDDA; Tamb = 25 °C VDDA − 1.64 VDDA − 1.45 VDDA − 1.26 V Ro(CMADC) output resistance Tamb = 25 °C − 17 26 Ω − −0.11 − mV/°C ∆Vref(CMADC)/∆T ADC reference output voltage variation with temperature 1999 Oct 08 7 Philips Semiconductors Product specification Wideband differential digital controlled variable gain amplifier SYMBOL PARAMETER TDA9901 CONDITIONS MIN. TYP. MAX. UNIT Io(CMADC)(max) maximum output current − 1.0 − mA Co(CMADC) output capacitance − 3 − pF Reference voltage output VGA: pin CMVGA Vref(CMVGA) VGA reference output voltage referenced to VDDA; Tamb = 25 °C Ro(CMVGA) output resistance Tamb = 25 °C VDDA − 2.48 VDDA − 2.30 VDDA − 2.17 V − 9 20 Ω ∆Vref(CMVGA)/∆T VGA reference output voltage variation with temperature − 1.75 − mV/°C Io(CMVGA)(max) maximum output current − 1.0 − mA Co(CMVGA) output capacitance − 3 − pF Gain switching characteristics (in latched mode); fCLK = 52 MHz; Tamb = 25°C; (see Fig.3) th input data hold time 2.0 − − ns tsu input data set-up time 3.8 − − ns tW input data pulse width 5.8 − − ns tPD1 propagation delay time − 4.2 5.9 ns tset1 gain settling time − 2.6 3.2 ns 10 to 90% full scale if ±6 dB gain change; note 3 Gain switching characteristics (in transparent mode); fCLK = 52 MHz; Tamb = 25°C; (see Fig.4) tPD2 propagation delay time tset2 gain settling time 10 to 90% full scale if ±6 dB gain change; note 4 − 6.7 9.5 ns − 5.4 6.9 ns Clock timing input: pins CLK and CLKN (see Fig.3) fCLK(max) maximum clock frequency 52 − − MHz tCPL clock LOW pulse width 4.0 − − ns tCPH clock HIGH pulse width 4.0 − − ns tr rise time − 4 − ns tf fall time − 4 − ns Digital inputs: pins TE, GRAY0, GRAY1 and GRAY2 VIL LOW-level input voltage 0 − 0.8 V VIH HIGH-level input voltage 2.0 − VDDD V IIH HIGH-level input current −10 − +10 µA IIL LOW-level input current −10 − +10 µA Ci input capacitance − − 3 pF Clock inputs in TTL mode VIL LOW-level input voltage note 5 0 − 0.8 V VIH HIGH-level input voltage note 5 2.0 − VDDD V IIH HIGH-level input current 15 − 80 µA IIL LOW-level input current −40 − −10 µA 1999 Oct 08 8 Philips Semiconductors Product specification Wideband differential digital controlled variable gain amplifier SYMBOL PARAMETER CONDITIONS MIN. − input capacitance Ci TDA9901 TYP. MAX. UNIT − 2 pF Clock inputs in differential mode VIL LOW-level input voltage VDDA = 5.0 V; note 6 3.19 − 3.52 V VIH HIGH-level input voltage VDDA = 5.0 V; note 6 3.83 − 4.12 V IIH HIGH-level input current 15 − 80 µA IIL LOW-level input current −40 − −5 µA Ci input capacitance − − 2 pF ∆Vi(CLK )(p-p) differential AC input voltage for switching CLK or CLKN (peak-to-peak value) 0.1 − 2.0 V DC voltage level = 2.5 V Notes 1. Due to on-chip regulator behaviour a warm-up time of 1 minute (typical) is recommended for optimal performance. 2. The analog output voltages are positive with respect to AGND. 3. In latching mode (TE = 0), the gain settling is latched at the rising edge of the clock input. 4. In transparent mode, the gain settling is directly controlled by the input data pattern. 5. The circuit may be used with a single TTL clock on CLK or CLKN. The non used clock pin has to be decoupled to ground with a 100 nF capacitance. 6. There are four modes of operation for the clock inputs in non TTL mode: a) PECL mode 1: (DC level vary 1 : 1 with VDDA) CLK and CLKN inputs are differential PECL levels. b) PECL mode 2: (DC level vary 1 : 1 with VDDA) CLK input is at PECL level and gain change takes place on the rising edge of the clock input signal when in latched mode. A DC level of 3.65 V has to be applied on CLKN decoupled to VSSD via a 100 nF capacitor. c) PECL mode 3: (DC level vary 1 : 1 with VDDA) CLKN input is at PECL level and gain change takes place on the rising edge of the clock input signal when in latched mode. A DC level of 3.65 V has to be applied on CLK decoupled to VSSD via a 100 nF capacitor. d) AC driving mode 4: when driving the CLK input directly and with any AC signal of minimum 0.1 V (p-p) and with a DC level of 2.5 V, the gain change takes place on the rising edge of the clock signal. When driving the CLKN input with the same signal, gain change takes place on the falling edge of the clock signal. It is recommended to decouple the CLKN or CLK input to VSSD via a 100 nF capacitor. Table 1 Input coding GREY INPUT DATA CODE STATE GAIN (dB) D2 D1 D0 0 0 0 0 minimum 1 0 0 1 minimum + 6 2 0 1 1 minimum + 12 3 0 1 0 minimum + 18 4 1 1 0 minimum + 24 Other − − − minimum + 24 1999 Oct 08 9 Philips Semiconductors Product specification Wideband differential digital controlled variable gain amplifier tr handbook, full pagewidth TDA9901 tf LOW CLK 50 % HIGH tCPH tCPL LOW GRAY0 GRAY1 gain N + 1 gain N 50 % GRAY2 HIGH tsu th OUT and OUTN 90 % gain N + 1 gain N 10 % tset1 Vo(max) 0.5Vo(max) tPD1 0V MGM964 Fig.3 Latched mode timing diagram. handbook, full pagewidth LOW GRAY0 GRAY1 gain N + 1 gain N 50 % GRAY2 HIGH OUT and OUTN gain N gain N + 1 90 % 10 % Vo(max) 0.5Vo(max) tset2 tPD2 0V MGM965 Fig.4 Transparent mode timing diagram with CLK HIGH. 1999 Oct 08 10 Philips Semiconductors Product specification Wideband differential digital controlled variable gain amplifier handbook, full pagewidth CMVGA IN FILTER 5 TDA9901 15 47 nF OUT Vi 680 Ω 6 TDA8768 (ADC) TDA9901TS 100 Ω sine wave generator 100 Ω 100 nF INN 7 680 Ω 14 42 C1(1) Vi OUTN C2(1) 47 nF D0...11 12 43 36 CLK dB (2) (3) 30 MHz FCE306 (1) C1 and C2 represent the board line capacitance. They represent about 5 pF with the TDA8768 input capacitance. Special care has to be taken to minimize this load in order to have the best dynamic performance. (2) The HD2 and HD3 of the TDA8768 is lower than that measured on the TDA9901.This measurement method is preferred to conventional methods due to its low contribution to the HD2. (3) The chain measurement shows the harmonic distortion of the TDA9901 as the measurement from TDA8768 is negligible. Fig.5 Dynamic distortion measurement diagram. FCE307 −55 HD (dBc) −60 FCE308 −55 HD (dBc) −60 handbook, halfpage handbook, halfpage −65 −65 −70 −70 (1) −75 (1) (2) −75 (2) −80 −80 −85 10−1 1 10 f (MHz) −85 10−1 102 1 10 (1) HD3 (2) HD2 (1) HD3 (2) HD2 Typical condition; 2 V (p-p) differential output. Typical condition; 2 V (p-p) differential output. Fig.6 Fig.7 Harmonic distortion as a function of frequency for minimum gain. 1999 Oct 08 11 f (MHz) 102 Harmonic distortion as a function of frequency for minimum gain plus 6 dB. Philips Semiconductors Product specification Wideband differential digital controlled variable gain amplifier FCE309 −55 HD (dBc) −60 TDA9901 FCE310 −55 HD (dBc) −60 handbook, halfpage handbook, halfpage (1) −65 −65 (1) −70 −70 −75 −75 (2) (2) −80 −80 −85 10−1 1 10 f (MHz) −85 10−1 102 1 10 (1) HD3 (2) HD2 (1) HD3 (2) HD2 Typical condition; 2 V (p-p) differential output. Typical condition; 2 V (p-p) differential output. Fig.8 Fig.9 Harmonic distortion as a function of frequency for minimum gain plus 12 dB. FCE311 −55 HD (dBc) −60 handbook, halfpage −65 (1) −70 −75 (2) −80 −85 10−1 1 10 f (MHz) 102 (1) HD3 (2) HD2 Typical condition; 2 V (p-p) differential output. Fig.10 Harmonic distortion as a function of frequency for minimum gain plus 24 dB. 1999 Oct 08 12 f (MHz) 102 Harmonic distortion as a function of frequency for minimum gain plus 18 dB. Philips Semiconductors Product specification Wideband differential digital controlled variable gain amplifier TDA9901 APPLICATION INFORMATION handbook, full pagewidth GRAY0 1 20 GRAY1 TE 2 19 GRAY2 CLK 3 18 CLKN(1) 4 17 100 nF 100 nF 3.3 V 47 µF 5 16 TDA9901TS 100 nF IN VIN 100 Ω 47 nF 6 15 7 14 n.c. 8 13 n.c. 9 12 n.c. 10 11 100 Ω INN 1:1 R1(2) OUT 47 nF OUTN n.c. 100 nF 5V MGM966 (1) Single-ended clock signal can be applied if required. (2) R1 and R2 should be at least 680 Ω. Fig.11 Application diagram. 1999 Oct 08 47 µF R2(2) 13 100 nF Philips Semiconductors Product specification Wideband differential digital controlled variable gain amplifier TDA9901 PACKAGE OUTLINE SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm D SOT266-1 E A X c y HE v M A Z 11 20 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 1.5 0.15 0 1.4 1.2 0.25 0.32 0.20 0.20 0.13 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1.0 0.75 0.45 0.65 0.45 0.2 0.13 0.1 0.48 0.18 10 0o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 90-04-05 95-02-25 SOT266-1 1999 Oct 08 EUROPEAN PROJECTION 14 o Philips Semiconductors Product specification Wideband differential digital controlled variable gain amplifier SOLDERING TDA9901 If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering The footprint must incorporate solder thieves at the downstream end. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Wave soldering Manual soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. To overcome these problems the double-wave soldering method was specifically developed. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 1999 Oct 08 15 Philips Semiconductors Product specification Wideband differential digital controlled variable gain amplifier TDA9901 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, SQFP not suitable suitable(2) HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1999 Oct 08 16 Philips Semiconductors Product specification Wideband differential digital controlled variable gain amplifier NOTES 1999 Oct 08 17 TDA9901 Philips Semiconductors Product specification Wideband differential digital controlled variable gain amplifier NOTES 1999 Oct 08 18 TDA9901 Philips Semiconductors Product specification Wideband differential digital controlled variable gain amplifier NOTES 1999 Oct 08 19 TDA9901 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 62 5344, Fax.+381 11 63 5777 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com SCA 68 © Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545004/25/02/pp20 Date of release: 1999 Oct 08 Document order number: 9397 750 05272