TDA9901 Wideband differential digital controlled variable gain amplifier Rev. 04 — 14 August 2008 Product data sheet 1. General description The TDA9901 is a wideband, low-noise amplifier with differential inputs and outputs. The TDA9901 incorporates an Automatic Gain Control (AGC) function with digital control. The TDA9901 is optimized for fast switching between different gain settings, preserving small phase and amplitude error. The TDA9901 presents an excellent combination of low noise and good linearity for a wide input frequency range. The TDA9901 is optimized for processing Input Frequency (IF) signals. It is also suited for many other applications as a general purpose digitally controlled variable gain amplifier. The TDA9901 is able to operate from 4.75 V to 5.25 V supply for the analog part and from 3.0 V to 5.25 V for the digital part. 2. Features n n n n n n n n n n n n n 130 MHz, −3 dB small signal bandwidth Digitally controlled gain Transistor-Transistor Logic (TTL) and CMOS compatible digital inputs (3.3 V or 5 V) TTL single-ended or differential clock input with Positive Emitter-Coupled Logic (PECL) compatibility 24 dB gain control range Four steps of 6 dB plus 6 dB fixed gain 30 dB gain maximum High impedance differential inputs Low impedance differential inputs High power supply rejection 125 nV/√Hz output voltage noise density at 30 dB gain Fast gain settling Dual control modes: transparent or latched 3. Applications n n n n n n Linear AGC systems Wireless infrastructure Fixed network Instrumentation Multipurpose amplifier Driver for differential ADCs (e.g. ADC1206S040/055/070 and ADC1006055/070) TDA9901 NXP Semiconductors Wideband differential digital controlled variable gain amplifier 4. Quick reference data Table 1. Quick reference data VDDA = V11 to V12 = 4.75 V to 5.25 V; VDDD = V18 to V17 = 3.0 V to 5.25 V; VSSA and VSSD shorted together; Tamb = −40 °C to +85 °C; typical values measured at VCCA = 5.0 V; VCCD = 3.3 V and Tamb = 25 °C unless otherwise specified [1]. Min Typ Max Unit VDDA Symbol Parameter analog supply voltage 4.75 5.0 5.25 V VDDD digital supply voltage 3.0 3.3 5.25 V IDDA analog supply current - 30 36 mA IDDD digital supply current - 3.0 5.0 mA Gmin minimum gain Tamb = 25 °C 5.78 6.11 6.40 dB all temperatures 5.7 6.11 6.46 dB Tamb = 25 °C 29.9 30.5 30.9 dB all temperatures 29.3 30.5 31.5 dB Vo(dif)(p-p) = 0.125 V; Tamb = 25 °C 110 130 - MHz - 160 216 mW Gmax Conditions DC input: maximum gain B_3dB −3 dB bandwidth Ptot total power dissipation [1] DC input: Due to on-chip regulator behavior a warm-up time of 1 minute (typical) is recommended for optimal performance. 5. Ordering information Table 2. Ordering information Type number TDA9901TS Package Name Description Version SSOP20 plastic shrink small outline package; 20 leads; body width 4.4 mm SOT266-1 TDA9901_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 14 August 2008 2 of 18 TDA9901 NXP Semiconductors Wideband differential digital controlled variable gain amplifier 6. Block diagram VDDD TE GRAY2 GRAY1 18 2 19 20 GRAY0 CLK CLKN VSSD 1 3 4 17 DECODER LATCHES TDA9901 IN INN 6 15 7 14 OUT OUTN 0, 6, 12, 18 or 24 dB CMVGA 5 REFERENCE GENERATOR REFERENCE GENERATOR 11 8, 9, 10, 13 16 CMADC 12 014aaa474 VDDA n.c. VSSA Fig 1. Block diagram TDA9901_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 14 August 2008 3 of 18 TDA9901 NXP Semiconductors Wideband differential digital controlled variable gain amplifier 7. Pinning information 7.1 Pinning GRAY0 1 20 GRAY1 TE 2 19 GRAY2 CLK 3 18 VDDD CLKN 4 17 VSSD CMVGA 5 16 CMADC TDA9901 TS IN 6 INN 7 14 OUTN n.c. 8 13 n.c. n.c. 9 12 VSSA n.c. 10 11 VDDA 15 OUT 014aaa475 Fig 2. Pin configuration 7.2 Pin description Table 3. Pin description Symbol Pin Description GRAY0 1 digital control signal bit 0 input (Least Significant Bit (LSB)) TE 2 transparent enable input CLK 3 clock input for gain control setting CLKN 4 inverting clock input for gain control setting (active LOW) CMVGA 5 regulator output common mode VGA input IN 6 non-inverting analog input INN 7 inverting analog input (active LOW) n.c. 8 not connected n.c. 9 not connected n.c. 10 not connected VDDA 11 analog supply voltage VSSA 12 analog ground n.c. 13 not connected OUTN 14 inverting analog output (active LOW) OUT 15 non-inverting analog output CMADC 16 regulator output common mode ADC input VSSD 17 digital ground TDA9901_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 14 August 2008 4 of 18 TDA9901 NXP Semiconductors Wideband differential digital controlled variable gain amplifier Table 3. Pin description …continued Symbol Pin Description VDDD 18 digital supply voltage GRAY2 19 digital control signal bit 2 input (Most Significant Bit (MSB)) GRAY1 20 digital control signal bit 1 input 8. Functional description The TDA9901 provides a digitally controlled variable gain function for high-frequency applications. The TDA9901 can be operated in two different modes, depending on the value at pin TE. When TE is at logic 1, the gain can be instantly controlled when the clock signal is HIGH (transparent mode). The gain is fixed during the LOW period of the clock. When TE is at logic 0 the gain of the TDA9901 is changed at the rising edge of the clock signal. 9. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDDA Conditions Min Max Unit analog supply voltage −0.3 +7.0 V VDDD digital supply voltage −0.3 +7.0 V ∆VDD supply voltage difference −0.1 +4.0 V VI input voltage VDDA − VDDD −0.3 +7.0 V IO output current - 10 mA Tstg storage temperature −55 +150 °C Tamb ambient temperature −40 +85 °C Tj junction temperature - 150 °C 10. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Value Unit Rth(j-a) thermal resistance from junction to ambient in free air 120 K/W TDA9901_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 14 August 2008 5 of 18 TDA9901 NXP Semiconductors Wideband differential digital controlled variable gain amplifier 11. Characteristics Table 6. Characteristics VDDA = V11 to V12 = 4.75 V to 5.25 V; VDDD = V18 to V17 = 3.0 V to 5.25 V; VSSA and VSSD shorted together; Tamb = −40 °C to +85 °C; typical values measured at VCCA = 5.0 V; VCCD = 3.3 V and Tamb = 25 °C unless otherwise specified [1]. Symbol Parameter Conditions Min Typ Max Unit Supplies VDDA analog supply voltage 4.75 5.0 5.25 V VDDD digital supply voltage 3.0 3.3 5.25 V ∆VDD supply voltage difference −0.2 - +2.5 V IDDA analog supply current - 30 36 mA IDDD digital supply current - 3.0 5.0 mA Ptot total power dissipation - 160 216 mW VDDA − VDDD Variable gain amplifier transfer characteristics B_3dB −3 dB bandwidth Vo(dif)(p-p) = 0.125 V; Tamb = 25 °C 110 130 - MHz td(grp) group delay time up to fi = 20 MHz; minimum gain; Tamb = 25 °C - 2.5 - ns ∆td(grp) group delay time variation 6 dB gain step; Tamb = 25 °C - - 300 ps ts settling time 10 % to 90 % maximum output transition; CL(max) = 5 pF on each output; Tamb = 25 °C - - 3.6 ns Gstep step of gain DC input: Tamb = 25 °C 5.88 6.09 6.28 dB all temperatures 5.6 6.09 6.56 dB Tamb = 25 °C 5.78 6.11 6.40 dB all temperatures 5.7 6.11 6.46 dB Tamb = 25 °C 29.9 30.5 30.9 dB all temperatures 29.3 30.5 31.5 dB Gmin Gmax ∆G/∆T minimum gain maximum gain DC input: DC input: gain variation with temperature minimum gain - −1.0 - mdB/°C maximum gain - −7.5 - mdB/°C ∆G/∆VCC gain variation with supply voltage minimum gain - 15 25 mdB/V ∆Vi(offset) offset input voltage variation 6 dB gain step - 0.8 - mV NF noise figure Rs = 100 Ω; fi = 20 MHz minimum gain - 29.1 - dB maximum gain - 9.9 - dB TDA9901_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 14 August 2008 6 of 18 TDA9901 NXP Semiconductors Wideband differential digital controlled variable gain amplifier Table 6. Characteristics …continued VDDA = V11 to V12 = 4.75 V to 5.25 V; VDDD = V18 to V17 = 3.0 V to 5.25 V; VSSA and VSSD shorted together; Tamb = −40 °C to +85 °C; typical values measured at VCCA = 5.0 V; VCCD = 3.3 V and Tamb = 25 °C unless otherwise specified [1]. Symbol Parameter Conditions Vn(o)(eq) equivalent output noise voltage G = 6 dB PSRR Typ Max Unit - 75 - nV/√Hz G = 12 dB - 82 - nV/√Hz G = 18 dB - 97 - nV/√Hz G = 24 dB - 91 - nV/√Hz G = 30 dB - 124 - nV/√Hz 0 MHz to 20 MHz - 57 - dB 20 MHz to 100 MHz - 39 - dB 0 MHz to 20 MHz - 67 - dB 20 MHz to 100 MHz - 51 - dB common mode rejection 0 MHz to 20 MHz ratio 20 MHz to 100 MHz - 75 - dB - 45 - dB minimum gain - 1.0 - V maximum gain - 60.4 - mV 2.0 2.7 VDDA − 1.9 V - 55 - µA power supply rejection ratio Min Rs = 100 Ω; fi = 20 MHz; Tamb = 25 °C minimum gain; VDDA minimum gain; VDDD CMRR Analog inputs Vi(p-p)(max) maximum peak-to-peak input voltage Vi(cm) common-mode input voltage Ii input current Ri input resistance 10 - - kΩ Ci input capacitance - - 5 pF Analog Vi(cm) = 2.7 V outputs[2] Vo(dif)(p-p)max maximum peak-to-peak differential output voltage maximum gain 2.0 - - V minimum gain 2.0 - - V VO(cm) common-mode output voltage referenced to VDDA; Tamb = 25 °C VDDA − 2.56 VDDA − 2.42 VDDA − 2.29 V ∆VO(cm)/∆T common-mode output voltage variation with temperature - −1.8 - mV/°C SRse single-ended slew rate - 275 - V/µs Ro output resistance - 15 26 Ω Co output capacitance - 3 - pF Variable gain amplifier dynamic performance; CL = 5 pF; RL = 680 Ω; see Figure 6, 7, 8, 9 and 10 α2H second harmonic level Vo = Vo(max) fi = 0.5 MHz - −80 −67 dBc fi = 4.43 MHz - −77 −67 dBc fi = 12.5 MHz - −76 −65 dBc fi = 21.4 MHz - −74 −62 dBc TDA9901_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 14 August 2008 7 of 18 TDA9901 NXP Semiconductors Wideband differential digital controlled variable gain amplifier Table 6. Characteristics …continued VDDA = V11 to V12 = 4.75 V to 5.25 V; VDDD = V18 to V17 = 3.0 V to 5.25 V; VSSA and VSSD shorted together; Tamb = −40 °C to +85 °C; typical values measured at VCCA = 5.0 V; VCCD = 3.3 V and Tamb = 25 °C unless otherwise specified [1]. Symbol Parameter α3H third harmonic level ∆α3H/∆T third harmonic level variation with temperature Conditions Min Typ Max Unit fi = 0.5 MHz - −64 −60 dBc fi = 4.43 MHz - −64 −59 dBc fi = 12.5 MHz - −62 −58 dBc fi = 21.4 MHz - −61 −57 dBc fi = 21.4 MHz - 80 - mdB/°C Vo = Vo(max); Tamb = 25 °C Reference voltage output ADC: pin CMADC Vref reference voltage referenced to VDDA; Tamb = 25 °C VDDA − 1.64 VDDA − 1.45 VDDA − 1.26 V Ro output resistance Tamb = 25 °C - 17 26 Ω ∆Vo(ref)/∆T reference output voltage variation with temperature - −0.11 - mV/°C Io(max) maximum output current - 1.0 - mA Co output capacitance - 3 - pF Reference voltage output VGA: pin CMVGA Vref reference voltage referenced to VDDA; Tamb = 25 °C VDDA − 2.48 VDDA − 2.30 VDDA − 2.17 V Tamb = 25 °C - 9 20 Ω - 1.75 - mV/°C Ro output resistance ∆Vo(ref)/∆T reference output voltage variation with temperature Io(max) maximum output current - 1.0 - mA Co output capacitance - 3 - pF Gain switching characteristics (in latched mode); fclk = 52 MHz; Tamb = 25 °C; see Figure 3 th hold time 2.0 - - ns tsu set-up time 3.8 - - ns tw pulse width 5.8 - - ns tPD propagation delay - 4.2 5.9 ns - 2.6 3.2 ns ts settling time 10 % to 90 % full scale if ±6 dB gain change [3] Gain switching characteristics (in transparent mode); fclk = 52 MHz; Tamb = 25 °C; see Figure 4 tPD ts propagation delay settling time 10 % to 90 % full scale if ±6 dB gain change [4] - 6.7 9.5 ns - 5.4 6.9 ns Clock timing input: pins CLK and CLKN (see Figure 3) fclk(max) maximum clock frequency 52 - - MHz tw(clk)L LOW clock pulse width 4.0 - - ns tw(clk)H HIGH clock pulse width 4.0 - - ns TDA9901_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 14 August 2008 8 of 18 TDA9901 NXP Semiconductors Wideband differential digital controlled variable gain amplifier Table 6. Characteristics …continued VDDA = V11 to V12 = 4.75 V to 5.25 V; VDDD = V18 to V17 = 3.0 V to 5.25 V; VSSA and VSSD shorted together; Tamb = −40 °C to +85 °C; typical values measured at VCCA = 5.0 V; VCCD = 3.3 V and Tamb = 25 °C unless otherwise specified [1]. Symbol Parameter tr tf Conditions Min Typ Max Unit rise time - 4.0 - ns fall time - 4.0 - ns Digital inputs: pins TE, GRAY0, GRAY1 and GRAY2 VIL LOW-level input voltage 0 - 0.8 V VIH HIGH-level input voltage 2.0 - VDDD V IIH HIGH-level input current −10 - +10 µA IIL LOW-level input current −10 - +10 µA Ci input capacitance - - 3 pF Clock inputs in TTL mode LOW-level input voltage [5] 0 - 0.8 V VIH HIGH-level input voltage [5] 2.0 - VDDD V IIH HIGH-level input current 15 - 80 µA IIL LOW-level input current −40 - −10 µA Ci input capacitance - - 2 pF 3.19 - 3.52 V VIL Clock inputs in differential mode VDDA = 5.0 V [6] VIH HIGH-level input voltage VDDA = 5.0 V [6] 3.83 - 4.12 V IIH HIGH-level input current 15 - 80 µA IIL LOW-level input current −40 - −5 µA Ci input capacitance - - 2 pF Vi(dif)(p-p) peak-to-peak differential DC voltage level = 2.5 V input voltage 0.1 - 2.0 V LOW-level input voltage VIL [1] Due to the behavior of the on-chip regulator a warm-up time of 1 minute (typical) is recommended for optimal performance. [2] The analog output voltages are positive with respect to VSSA. [3] In latching mode (pin TE LOW), the gain settling is latched at the rising edge of the clock input. [4] In transparent mode, the gain settling is directly controlled by the input data pattern. [5] The circuit may be used with a single TTL clock on CLK or CLKN. The unused clock pin has to be decoupled to ground with a 100 nF capacitance. [6] There are four modes of operation for the clock inputs in non-TTL mode: a) PECL mode 1: (DC level vary 1 : 1 with VDDA) CLK and CLKN inputs are differential PECL levels. b) PECL mode 2: (DC level vary 1 : 1 with VDDA) CLK input is at PECL level and gain change takes place on the rising edge of the clock input signal when in latched mode. A DC level of 3.65 V has to be applied on CLKN decoupled to VSSD via a 100 nF capacitor. c) PECL mode 3: (DC level vary 1 : 1 with VDDA) CLKN input is at PECL level and gain change takes place on the rising edge of the clock input signal when in latched mode. A DC level of 3.65 V has to be applied on CLK decoupled to VSSD via a 100 nF capacitor. d) AC driving mode 4: when driving the CLK input directly and with any AC signal of minimum 0.1 V (p-p) and with a DC level of 2.5 V, the gain change takes place on the rising edge of the clock signal. When driving the CLKN input with the same signal, gain change takes place on the falling edge of the clock signal. NXP Semiconductors recommends decoupling of the CLKN or CLK input to VSSD via a 100 nF capacitor. TDA9901_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 14 August 2008 9 of 18 TDA9901 NXP Semiconductors Wideband differential digital controlled variable gain amplifier 12. Additional information relating to Table 6 Table 7. Input coding State Gray input data code Gain (dB) Pins Gray2, Gray1, Gray0 D2 D1 D0 0 0 0 0 minimum 1 0 0 1 minimum + 6 2 0 1 1 minimum + 12 3 0 1 0 minimum + 18 4 1 1 0 minimum + 24 other - - - minimum + 24 tr tf LOW 50 % CLK HIGH tw(clk)H tw(clk)L LOW GRAY0 GRAY1 gain N gain N + 1 50 % GRAY2 HIGH tsu th Vo(max) 90 % OUT and OUTN gain N gain N + 1 10 % 0.5 Vo(max) ts tPD 0V 014aaa476 Fig 3. Latched mode timing diagram TDA9901_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 14 August 2008 10 of 18 TDA9901 NXP Semiconductors Wideband differential digital controlled variable gain amplifier LOW GRAY0 GRAY1 gain N 50 % gain N + 1 GRAY2 HIGH 90 % OUT and OUTN gain N Vo(max) gain N + 1 10 % 0.5 Vo(max) ts tPD 0V 014aaa477 Fig 4. Transparent mode timing diagram with CLK HIGH CMVGA 5 15 OUT 47 nF Vi C1(1) 680 Ω IN FILTER 100 Ω TDA9901TS ADC1206S 055 (ADC) 6 D0...11 680 Ω 100 Ω sine wave generator 42 OUTN 47 nF INN 7 Vi 14 C2(1) 100 nF dB (2) (3) 43 36 CLK 30 MHz 014aaa468 (1) C1 and C2 represent the board line capacitance. They represent about 5 pF with the ADC1206S040/055/070 input capacitance. Special care has to be taken to minimize this load in order to have the best dynamic performance. (2) The α2H and α3H of the ADC1206S040/055/070 is lower than that measured on the TDA9901. This measurement method is preferred to conventional methods due to its low contribution to the α2H. (3) The chain measurement shows the harmonic distortion of the TDA9901 as the measurement from ADC1206S040/055/070 is negligible. Fig 5. Dynamic distortion measurement diagram TDA9901_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 14 August 2008 11 of 18 TDA9901 NXP Semiconductors Wideband differential digital controlled variable gain amplifier 014aaa469 −55 HD (dBc) 014aaa470 −55 HD (dBc) (1) −65 (1) −65 (2) −75 (2) −75 −85 10−1 1 102 10 −85 10−1 1 f (MHz) (1) α3H. (1) α3H. (2) α2H. (2) α2H. Typical condition; 2 V (p-p) differential output Fig 6. Harmonic Distortion (HD) as a function of frequency for minimum gain 014aaa471 −55 102 10 f (MHz) HD (dBc) Typical condition; 2 V (p-p) differential output Fig 7. Harmonic Distortion (HD) as a function of frequency for minimum gain plus 6 dB 014aaa472 −55 HD (dBc) (1) (1) −65 −65 (2) −75 −75 (2) −85 10−1 1 102 10 −85 10−1 f (MHz) 102 10 f (MHz) (1) α3H. (1) α3H. (2) α2H. (2) α2H. Typical condition; 2 V (p-p) differential output Fig 8. Harmonic Distortion (HD) as a function of frequency for minimum gain plus 12 dB Typical condition; 2 V (p-p) differential output Fig 9. Harmonic Distortion (HD) as a function of frequency for minimum gain plus 18 dB TDA9901_4 Product data sheet 1 © NXP B.V. 2008. All rights reserved. Rev. 04 — 14 August 2008 12 of 18 TDA9901 NXP Semiconductors Wideband differential digital controlled variable gain amplifier 014aaa473 −55 HD (dBc) (1) −65 (2) −75 −85 10−1 1 102 10 f (MHz) (1) α3H. (2) α2H. Typical condition; 2 V (p-p) differential output Fig 10. Harmonic Distortion (HD) as a function of frequency for minimum gain plus 24 dB TDA9901_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 14 August 2008 13 of 18 TDA9901 NXP Semiconductors Wideband differential digital controlled variable gain amplifier 13. Application information 13.1 Application diagrams GRAY0 1 20 GRAY1 TE 2 19 GRAY2 CLK 3 18 CLKN(1) 4 17 100 nF 3.3 V 47 µF 100 nF 5 16 R1(2) TDA9901TS 100 nF IN VIN 15 7 14 n.c. 8 13 n.c. 9 12 n.c. 10 11 INN 1:1 47 µF 100 nF OUT 100 Ω 100 Ω R2(2) 47 nF 6 47 nF OUTN n.c. 100 nF 5V 014aaa478 (1) Single-ended clock signal can be applied if required. (2) R1 and R2 should be at least 680 Ω. Fig 11. Application diagram 13.2 Recommended companion chip Table 8. Recommended companion chips Type number Description Sampling frequency ADC1006S055 Single 10 bits ADC 55 MHz ADC1006S070 Single 10 bits ADC 70 MHz ADC1206S040 Single 12 bits ADC 40 MHz ADC1206S055 Single 12 bits ADC 55 MHz ADC1206S070 Single 12 bits ADC 70 MHz TDA9901_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 14 August 2008 14 of 18 TDA9901 NXP Semiconductors Wideband differential digital controlled variable gain amplifier 14. Package outline SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm D SOT266-1 E A X c y HE v M A Z 11 20 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 1.5 0.15 0 1.4 1.2 0.25 0.32 0.20 0.20 0.13 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.45 0.65 0.45 0.2 0.13 0.1 0.48 0.18 10 o 0 o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT266-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-152 Fig 12. Package outline SOT266-1 (SSOP20) TDA9901_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 14 August 2008 15 of 18 TDA9901 NXP Semiconductors Wideband differential digital controlled variable gain amplifier 15. Revision history Table 9. Revision history Document ID Release date Data sheet status Change notice Supersedes TDA9901_4 20080814 Product data sheet - TDA9901_3 Modifications: • • Correction made to ∆VDD conditions in Table 4. Corrections made to values of td(grp) and Gstep in Table 6. TDA9901_3 20080611 Product specification - TDA9901_2 TDA9901_2 19991008 Product specification - TDA9901_N_1 TDA9901_N_1 19980415 Product specification - - TDA9901_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 14 August 2008 16 of 18 TDA9901 NXP Semiconductors Wideband differential digital controlled variable gain amplifier 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] TDA9901_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 14 August 2008 17 of 18 TDA9901 NXP Semiconductors Wideband differential digital controlled variable gain amplifier 18. Contents 1 2 3 4 5 6 7 7.1 7.2 8 9 10 11 12 13 13.1 13.2 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal characteristics. . . . . . . . . . . . . . . . . . . 5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Additional information relating to Table 6 . . . 10 Application information. . . . . . . . . . . . . . . . . . 14 Application diagrams . . . . . . . . . . . . . . . . . . . 14 Recommended companion chip . . . . . . . . . . . 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 14 August 2008 Document identifier: TDA9901_4