AN2482 Application note PCLT (Programmable current limited termination) Introduction The purpose of this document is: ■ To describe the PCLT behavior (refer also to data sheet) ■ To give useful recommendations to achieve robust PCLT designs regarding EMI test (IEC 61000-4-5 and 4-4) ■ To give information on thermal behavior of PCLT in its application ■ To describe the demonstration board and recommendations for use Contents 1 2 3 PCLT Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 External biasing resistor settings 1.4 Protection against reverse polarity of power supply . . . . . . . . . . . . . . . . . 5 1.5 Opto-coupler and CMOS modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ............................... 4 Thermal dissipation calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 Normal forward polarity of all inputs case . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Reverse polarity on a single input case . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 RTH adjustment with PCB area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 Experimental Tj measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Unisolated AS-interface bus application . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 Application overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 Isolation of the sensor section and the supply from data/supply bus . . . . 10 3.3 Un-isolated connection of the PCLT with AS-Interface controller . . . . . . . 11 4 Electromagnetic compatibility (EMC) requirements . . . . . . . . . . . . . . 12 5 Demo board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 Description of the PCLT-2A demo board . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 Operating instructions of the PCLT-2A demo-board . . . . . . . . . . . . . . . . . 15 6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 February 2007 Rev 1 1/18 www.st.com PCLT Description AN2482 1 PCLT Description 1.1 Main features The PCLT (programmable current limited termination) is a dual input digital active termination device designed for 24 V DC input modules used in industrial automation. Each channel circuit terminates the connection between a high side proximity sensor and the I/O module. Figure 1. Single channel bock diagram CURRENT LIMITER I OUTPUT INTERFACE LIM LED 1 IN1 LO 60% . I LIM OPTO OUT 1 LO 30% . ILLIM IM 10% . I LIM EN OVER VOLTAGE PROTECTION VMOD MOD V DD EN 1.4V 50µA V CC IN 1 COM P CMOS LO 2mA 5V CHANNEL #1 IN2 LED 2 CURRENT REFERENCE VC CHANNEL #2 BIASING CIRCUIT OUT 2 COM S REF The advanced features of the PCLT compared to the CLT3 are: ● The current limiter circuit can be programmed through an external resistance RREF to meet type 2 (7.5 mA), type 3 and type 1 (2.5 mA) characteristics as specified in IEC 61131-2 standard. ● The possibility to drive either opto-couplers for isolated circuit or CMOS 3.3 V to 12 V for unisolated circuit. ● The additional outputs to drive status LEDs. The PCLT also features an input voltage protection. This input protection makes this device robust against electromagnetic interferences as defined in IEC 61000-4-x standards: ESD, fast transient bursts, and voltage surges. 2/18 AN2482 PCLT Description It is housed in a very low RTH exposed pad surface mount TSS0P14 package to reduce the printed board size and the cooling pad. Operating modes Figure 2. gives the input limits and operating ranges defined by IEC 61131-2 standard and a typical PCLT characteristic. Figure 2. EC61131-2 operating regions and PCLT2 characteristic 30 V 30V 25 2.1mA Tr an ON ON region si 20 tio n g re 15 io VI (V) 1.2 n 11V 10 5 TYPE 1 15 V TYPE 2 11 V TYPE 3 11 V TYPE 1 5V V OFF TYPE 2 5V TYPE 3 5V V ON OFF region 0 Iin (mA) 0 I OFF TYPE 1 TYPE 3 TYPE 2 0.5 mA 1.5 mA 2.0 mA I ON 2 mA 2 mA 6 mA In accordance with IEC 61131-2 standard, for both opto-coupler and CMOS configuration modes, when the input current is less than 2 mA (type 2) or 1.5 mA (type 3) the output circuits divert all the input current and maintain both LED and output in OFF state (VOL < 0.1 V for VMOD = 0 and 20% VMOD for VMOD > 2.9 V). When the module input voltage VI (type 2), including the 750 Ω input resistor and the reverse diode (see Figure 4.), is higher than 11 V, i.e. the PCLT input voltage VIN is higher than 5 V, both LED and output circuits are in ON states. The input current is then shared between the COMs (about 10%), the LED (about 60%), and the OUT (about 30%) pins in case of opto-coupler mode. In CMOS mode, the CMOS output level is defined by the VMOD voltage supplied by the external supply voltage VDD of the bus controller. It can be in the range of 3.3 to 12 V. The output voltage is delivering 80% of VDD for ON state and 20% of VDD for OFF state. When no LED diode is used, the LED outputs pin must be connected to the ground COMP to allow the current to flow back to the power supply. 3/18 PCLT Description 1.3 AN2482 External biasing resistor settings The PCLT operation mode can be set to the various logic input types defined by the IEC 61131-2 standard. The current reference of the input-limiting block of each channel is programmable by means of an external resistor RREF. Moreover, because the operating current range is different for each type, the external input resistor RI can be changed to improve the over-voltage robustness of the whole circuit. Table 1. defines the setting resistances for the types 1, 2, and 3 and the corresponding performances of the PCLT input and Figure 3. shows the current limiter variation versus the RREF biasing resistor. Table 1. Setting table Type 1 Setting 3 2 Unit RREF KΩ RI KΩ RC KΩ 22 2.2 10 1.2 0.75 2.2 Performances IIN MIN mA 2.2 6 IIN TYP mA 3 7.1 IIN MAX mA 4 8.5 ILED TYP mA 1.9 4 Surge with RI kV 1 0.5 ESD with RI kV Figure 3. Typical current limiter variation versus reference resistance RREF 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 ILIM / ILIM (10 kΩ) 5.0E+00 4/18 8 in contact, 15 in air (class4) RREF (kΩ) 1.0E+01 1.5E+01 2.0E+01 2.5E+01 3.0E+01 AN2482 1.4 PCLT Description Protection against reverse polarity of power supply A reverse diode should be connected between the module ground connection and the common pin COM of the PCLT2A device to protect the module against spurious reverse supply connection (refer to IEC 6131-2 section 5.3.3.1) Opto-coupler and CMOS modes The voltage VMOD applied to the selector pin MOD allows the output OUT to be configured either in an opto-coupler driver mode (VMOD < 0.75 V) (see Figure 4.) or in a CMOS output mode able to interface directly a bus controller circuit (VMOD > 2.9 V) (see Figure 5.). In CMOS mode, the VMOD pin activates a CMOS compatible buffer output able to source a minimum current of 35 µA powered by the MOD pin. Figure 4. Isolated digital input diagram with opto-coupler driving output VI VIN 2 wires sensor RI CI RI CI 3 wires sensor RC VCC VC OUT1 IN1 LED1 IN2 OUT2 VC LED2 REF MOD RREF CC COMP Reverse polarity 1N4007 Figure 5. COMS PCLT -2A Unisolated digital input diagram with programmable CMOS output PCLT-2A VI VIN IN1 2 wires sensor RI CI RI CI 3 wires sensor OUT1 VCC RC CC Supply voltage protection SM15T39 IN1 LED1 IN2 IN2 OUT2 VC LED2 REF MOD VDD COMS VSS VC R REF 1.5 COMP BUS CONTROLLER 5V SUPPLY VCC VDD Reverse polarity 1N4007 GND 5/18 Thermal dissipation calculation AN2482 2 Thermal dissipation calculation 2.1 Normal forward polarity of all inputs case Referring to the PCLT diagram defined in Figure 1., the dissipated power for both configurations can be calculated as follows: ( ) POPTO _ MODE = VC ⋅ I C + 2 VIN _ LED ⋅ 0.6 ⋅ I IN + VIN _ OUT ⋅ 0.3 ⋅ I IN + VIN ⋅ 0.1 ⋅ I IN if VMOD < 0.75V ( ) PCMOS _ MODE = VC ⋅ I C + VMOD ⋅ I DD + 2 VIN _ LED ⋅ 0.6 ⋅ I IN + VIN ⋅ 0.4 ⋅ I IN if VMOD > 2.9V VIN = VCC − VSENSOR − R IN ⋅ I IN where V SENSOR is the voltage drop of the input sensor VIN_OUT = VIN − VOUT where VOUT is the forward voltage drop of the opto coupler input VIN_LED = VIN − VLED where V LED is the forward voltage drop of the LED The worst case scenario occurs when IIN and ICC are maximum (values are given in the datasheet): IIN_MAX = 8.8mA IC_MAX = 2.0mA and when the voltage drops between PCLT input and output or LED_output. With the conditions VCC = 30 V, RREF = 10 kΩ, VSENSOR = 0 V, VOUT = 0.9 V, RIN = 750 Ω, and VOUT_LED = 1.5 V POPTO _ MODE = 430mW PCMOS _ MODE = 440mW But this normal forward input polarity is not the worst case of PCLT power dissipation. See the next section. 2.2 Reverse polarity on a single input case Each input of the PCLT circuit may be biased to a reverse polarity equal to - VCC. This case corresponds to a connection mistake or a reverse biasing that is generated by the demagnetization of a monitored inductive solenoid. The involved input can withstand a high reverse current up to 20 mA. Its corresponding opto-coupler output is then OFF and is protected by the clamping input diode. The other input remains operational, and some power is dissipated in their clamping protections. The losses in reverse input polarity configuration (see Figure 6.) are: Pdis _ PCLT = PTOTdelivered − Pdis _ RC − Pdis _ RIN1 − Pdis _ RIN 2 Pdis _ PCLT = 566mW 6/18 AN2482 Thermal dissipation calculation Figure 6. Reverse input polarity configuration Vcc = + 30V 2.2kW 3.6mA VC IN1 I1 = + 30V VCL= 38 V 9.7mA IREG N OUT1 750 W 1N4007 GND (0V) COM 750 W I2 = -30V 13.3mA IN2 OUT2 IREG4 PCLT-2 Taking into account this dissipated power worst case (reverse polarity on a single input) and with an ambient temperature of 85° C the thermal resistance must be lower than 115° C/W. The PCLT datasheet specifies a 100° C/W RTH(JA) with a copper area of 1.25cm2 ensuring a safer cooling. RTH adjustment with PCB area Figure 7. gives the relative junction to ambient thermal resistance as a function of the copper surface used as a heat sink (FR4 epoxy PCB, 35 µm for the thickness of the copper). The RTHJA can be deceased down to100° C/W with a 1.25 cm² copper area. Figure 7. Thermal resistance variation versus copper area (35 µm layer thickness; 50 vias/cm2 and 300 µm diameter in double layer) Rth(jA)/Rth(1.25cm2) 150% 140% 130% 120% Rth(j-a)(%) 2.3 110% 100% 90% PCB single layer 80% PCB double layer 70% Copper area (cm²) 60% 0 0.5 1 1.5 2 2.5 3 3.5 4 7/18 Thermal dissipation calculation 2.4 AN2482 Experimental Tj measurement The purpose is to estimate easily and experimentally the junction temperature TJ from the case temperature TC measurement. The case temperature is measured here with a Sander probe (K type, rounded contact, area 500 µm) as shown on Figure 8. Figure 8. TCASE measurements Type K Sander probe TSSOP14 exposed pad with 3.6 x 3 mm pad soldered Copper area on both sides with metalized holes Copper strip to power the PCLT The PCLT has been submitted to two representative powers (380 mW and 670 mW), it has been soldered on different copper area sizes from 0.1 cm2 (exposed pad size) to 2 cm2 per side. The case and junction temperatures have been measured at three room temperatures, +25° C, +55° C and +85° C using only natural convection. The junction temperature is calculated by means of an input diode protection used as a temperature sensor. According to these experimental results, Figure 9. gives an evaluation of the junction temperature as a function of the case temperature for three ambient temperatures. Figure 9. Junction temperature versus case and ambient temperatures Tj (° C) 125 Tj versus Tc Tj = 1.30 x Tc - 0.3O x Ta 105 Ta = 85° C Ta = 55° C 85 Ta = 25° C 65 Operational area not possible (Tj < Tc) 45 Tc (° C) 25 8/18 25 35 45 55 65 75 85 95 105 115 125 AN2482 Thermal dissipation calculation Junction and ambient temperatures can be found from the assembly model shown in Figure 10. Figure 10. Assembly model RTH_CA RTH_CA RTH_JC RTH_JC TAA T T TCC P P11 T TJJ T J = junction temperatur e T A = ambient temperatur e TC = case temperatur e ( = P1 (RTH _ JC ) T J − T A = P1 RTH _ JC + RTH _ CA T J − TC T J = TC + (T J − T A ) ) RTH _ JC (RTH _ JC + RTH _ CA ) ⎛ RTH _ JC ⎞ R ⎟ − T A TH _ JC T J = TC ⎜1 + ⎜ ⎟ RTH _ CA ⎠ RTH _ CA ⎝ RTH _ JC assu min g : = 0.30 in accordance to the experiment al results, the relation becomes : RTH _ CA T J = 1.30 • TC − 0.30 • T A The accuracy of the TJ results are in the range of 5% 9/18 Unisolated AS-interface bus application AN2482 3 Unisolated AS-interface bus application 3.1 Application overview The AS-Interface bus is a low-end field bus for actuators and sensors in manufacturing and industrial automation. Its electrical architecture uses an unshielded 2-wire yellow cable that transports both the 24 V power supply of the field nodes and the serial bidirectional data communication. Figure 11. Simplified architecture of AS-interface Bus AS-i MASTER I/O SLAVE I/O SLAVE I/O SLAVE AS-i SLAVES The data communication is achieved with a current carrier modulation superimposed over the power wires. Therefore, the power bus terminals are filtered in order to maintain identical and calibrated differential and common mode impedances measured by both master and slave units. 3.2 Isolation of the sensor section and the supply from data/supply bus The PCLT can be designed as an interface between a proximity sensor and its associated slave controller unit. The sensor power supply is generated from the bus power supply with a filter and a regulator that are inserted in the slave unit. In the same manner, the sensor logic signal is isolated from the AS-Interface power supply bus to avoid any degradation of the data transmission. A conventional way to achieve the interface with the PCLT and the AS-Interface controller is to insert an opto-coupler between the AS-Interface controller and the PCLT that runs in opto-coupler mode as shown on Figure 4. (MOD pin grounded). 10/18 AN2482 Un-isolated connection of the PCLT with AS-Interface controller To remove the opto-coupler in lower cost versions, the operation of the PCLT has been extended to fit the AS-Interface application. A precaution is required on its interface with the bus controller: the impedance between the two circuits must be high in order to maintain the isolation. To achieve this isolation impedance level, the PCLT runs in CMOS mode (MOD = VCC) and the buffer operation is extended up to VCC = 12 V. In the application, the VCC voltage is generated with a Zener diode reference fed from the sensor bus. Because of the buffer voltage increase, it becomes possible to insert a high impedance between the PCLT output and the AS-Interface bus controller input. Typically a 100 kΩ resistor is designed while keeping a 5 V CMOS operation on the input of the bus controller. Figure 12. shows the application diagram where the PCLT is connected to the slave bus controller through a 100 kΩ resistor. The logic signal is transmitted with a low level of less than 20% of the VDD supply voltage and a high level of at least 3.5 V. This high level is defined by the voltage drop across the 100 kΩ pull down resistor. (35 µA times 100 kΩ). Figure 12. Un-isolated AS-Interface slave controller unit using the PCLT 30V Vreg 22nF 1 14 10 9 LED 10KÙ 7 SLAVE AS-I 100KÙ PCLT 12V CTRLER 4.7nF 750Ù sensor ASiP 100KÙ VCCsensor 2.2 KÙ VCC 2.2KÙ 28V 33nF 3.3 Unisolated AS-interface bus application ASiN 11/18 Electromagnetic compatibility (EMC) requirements 4 AN2482 Electromagnetic compatibility (EMC) requirements The input and supply pins are designed to withstand electromagnetic interferences. They are protected by a clamping diode that is connected to the COMP common pin. Combined with the serial input resistance RI, this clamping diode is effective against the fast transient bursts (±4 kV, IEC 61000-4-4) and the voltage surges (±1kV, IEC 61000-4-5). EMC test procedures are fully described in AN1608 CLT3-4BT6 application note. Refer to it to get detailed information. It covers IEC 61000-4.2 standard for ESD tests, IEC 61000-4.4 standard for fast transient burst tests, IEC 61000-4.5 standard for surge tests, IEC 61000-4-6 standard for conducted disturbance tests. IEC 61131-2 standard for programmable controllers specifies (see section 7.3.3 of the standards document) a low profile requirement for digital inputs with: ● High energy Surge = 0.5 kV ● Fast Transient Burst = 1 kV ● Electrostatic Discharge = 4 kV ● Radio Frequency Interference = 3 Vrms. But designers are requiring now improved robustness levels: ● 4 kV EFT burst; ● 500 V at least in surge ● ESD 15 kV air ● 10Vrms for conducted RFI. The PCLT demo board described here sustains the levels given on Table 2. 12/18 AN2482 Table 2. Electromagnetic compatibility (EMC) requirements PCLT Immunity tests results Minimum requirements of international standards Test conditions Levels Tests conditions Levels Air discharge ±8 kV RC = 2.2 kΩ RIN = 750 Ω ±15 kV RC = 2.2 kΩ RIN = 750 Ω ±8 kV RIN = 750 Ω CIN = 22 nF RC = 2.2 kΩ CC =33 nF ±4 kV ESD test IEC61000-4-2 Burst test IEC61000-4-4 Contact discharge ±4 kV Analog Input ±1kV DC power line Analog Input Surge test IEC61000-4-5 dc power line Conducted disturbance test 150 kHz to 80 MHz IEC61000-4-6 Reverse input polarity test Robustness of the PCLT demo board 42 Ω: 0.5 µF differential and common mode ±2 kV ±0.5 kV 2 Ω; 18 µF differential mode ±0.5 kV 12 Ω; 9 µF common mode ±1 kV 22 nF capacitors 3 Vrms AM±80% Analog Input -Vcc applied to one input during 10 s No failure, no disturbance. RIN = 750 Ω ±0.5 kV RIN = 1.2 kΩ ±1 kV ±1 kV dc power line behavior of the PCLT No failure, no disturbance. No failure, temporary disturbance. RC = 2.2 k ±1 kV 150 kHz to 80 MHz RIN = 750 Ω 10 Vrms C = 22 nF AM±80% At the input -30 Vdc applied to one input, +30 Vdc on the others No failure, No disturbance. No failure 13/18 Demo board AN2482 5 Demo board 5.1 Description of the PCLT-2A demo board This demonstration board allows the PCLT evaluation. It can be easily inserted in a real application, between sensors and digital bus controller. The LEDs monitors the logic state of each PCLT input. The demonstration board schematics are shown on Figure 13. and Figure 14. It has been designed to present both opto-coupler and CMOS modes for type 2. The bill of material is given in Table 3. For the opto-coupler driving mode, the PCLT pin 10 has been grounded, while for the CMOS driving mode the user has to supply the PCLT pin 10 through the OUTPUT_B connector. The copper surface under the CLT device improves the thermal dissipation capability of the exposed pad TSSOP14 package. The copper area (cooling pad) on the PCB demo board is around 1cm², this decreases the package RTHJA below 110° C/W. Figure 13. Electrical diagram of opto-coupler diving mode UA Rin_A1 750R LED_A1 1 IN1 LED1 9 Cout 2 LED2 8 6 3 ISO1A ILD213 LED_A2 100nF ISO1B ILD213 5 3 IN2 Rin_A2 750R 4 Rc_A 2.2k 0 0R VDD_A OUT2 12 8 COMp Cin_A2 22nF 7 4 VDD 10 1 Cin_A1 22nF 1 2 3 4 2 In1 In2 Vcc Com VDD_A OUT1 14 INPUT_A 5 VC 7 REF Cc_A 33nF Rref_A 10k D1 Dnw1 30k COMs PCLT-2A 11 Dnw2 30k 13 OUTPUT_A SM4005 VDD_A 1 2 3 4 Opto1 Opto2 Vdd Gnd Figure 14. Electrical diagram of CMO driving mode UB Rin_B1 750R LED_B1 1 IN1 LED1 9 INPUT_B In1 In2 Vcc Com OUT1 14 Cin_B1 22nF 1 2 3 4 OUTPUT_B 2 4 VDD 10 COMp Cin_B2 22nF Rc_B 2.2k LED2 8 LED_B2 5 VC 7 REF Cc_B 33nF D2 SM4005 14/18 VDD_B OUT2 12 3 IN2 Rin_B2 750R VDD_B Rref_B 10k COMs PCLT -2A 11 13 1 2 3 4 Out1 Out2 Vdd Com AN2482 Demo board Table 3. Quantity Reference Part Package / comments 1 4 RIN_(A1, A2, B1, B2) 750 ±1% CMS MMB0207 2 2 RC_(A, B) 2.2k ±1% CMS MMB0207 3 2 RREF_(A, B) 10k ±1% CMS 0805 4 4 CIN_(A1, A2, B1, B2) 22n ±5% CMS 0805 5 2 CC_(A, B) 33n ±5% CMS 0805 6 1 COUT 100n ±5% CMS 0805 7 2 D1, D2 BYD17J CMS SOD-80 8 2 DNW(1, 2) 33k ±% CMS 1206 9 1 0R 0 ±5% CMS 1206 10 4 LED_(A1, A2, B1, B2) Green CMS PLCC-2 11 1 Opto-coupler ILD213 SOIC-8 12 4 Bent connectors (INPUT_(A, B),OUTPUT_(A, B) 13 2 PCLT-2A 14 4 Nylon spacer Item 5.2 Bill of material 4 pins/connector Bottom assembly PCLT2A TSSOP14 Operating instructions of the PCLT-2A demo-board This section provides some basic advice on using the demonstration board to evaluate the PCLT product. 5.2.1 Input connectors The INPUT_A, INPUT_B connectors give access to: ● the 2 input signals of the module (In1, In2) ● the PCLT power supply (VCC and Com_A, Com_B). It is then easy to connect this module directly to any type of sensor, especially those specified by the EN60947-5-2 standard. The Vcc power supply is typically 24 V DC (30 V max). 5.2.2 Output connectors The OUTPUT_A connector gives access to: ● the 2 opto-coupler outputs of the module (Opto1, Opto2) ● the opto-coupler collector power supply (Vdd and Gnd) which is typically 5 V DC (this voltage has to be compatible with micro controllers being used; 12 V max). It is then easy to connect the output of the module directly on a digital bus controller. 15/18 Demo board AN2482 The OUTPUT_B connector gives access to: ● the 2 PCLT2 CMOS compatible outputs (out1, out2) ● the VDD supply (Vdd and Com), which is typically 5 V DC, can be in the range from 3.3 V to 12 V (This voltage has to be compatible with micro controllers being used) This application allows a direct CMOS compatible connection to the digital bus controller but without any galvanic isolation. 5.2.3 Schematics components The 22 nF input capacitors are used in order to improve the noise immunity of the whole module. Their function is to filter the high frequency electrical noise, and to secure the off state of the module. Adding a 33 nF capacitor on VC pin ensures high immunity against electrical noise such as the one described in the IEC 61131-2 standard. The input resistors are used to limit the current that could appear in case of voltage surge clamped by the PCLT. These resistors can then withstand the high over voltage that may be applied to the module during surge tests. The LEDs resistor value shall be set according to the input power supply value used, and the normal current of displaying LEDs. A resistor array can be used to control these low power LEDs (reduction of the PCB size). The D1 diode used between the COM of the input power supply, and the COM of the PCLT-2A device can be a general purpose component such as a 1000 V, 1 A rectifier. The opto-coupler must be chosen according to its input diode drop voltage. This drop voltage must not disturb the operation of the PCLT (see PCLT datasheet, “Absolute ratings table” for more details about VOM). Figure 15. Demo board assembly - top view 16/18 Figure 16. Demo board photograph AN2482 6 Conclusion Conclusion This application note illustrates how designers can maximize PCLT performance in its application especially in the field of thermal behavior and EMI robustness. Designed for I/O module in factory automation, the PCLT is a low-loss EMI-proof solution showing high usage flexibility. Designers can develop a wide variety of input types in isolated and un-isolated versions. To illustrate PCLT performance and advantages, a bread board is also proposed with an optimized lay-out. With its robust protection and its current limiter, the PCLT is a low-loss EMI-proof solution for highly integrated module interfacing with proximity sensors. 7 Revision history Date Revision 08-Feb-2006 1 Changes Initial release. 17/18 AN2482 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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