PCLT-2A Dual current limited over-voltage protected digital termination Applications ■ Type 1, 2 and 3 logic input termination for industrial automation ■ AS-Interface bus input termination ■ I/O termination in programmable logic controller ■ Proximity detector interface ■ Decentralized Input / Output modules TSSOP14 Exposed pad ■ IEC61000-4-5 voltage surge, Level 3 – ± 500 V with 42 Ω series resistor in differential mode – Criteria B: temporary disruption ■ IEC61000-4-4 transient burst immunity – ± 4 kV peak voltage; 5 kHz repetitive rate – Criteria A: fully functional ■ IEC61000-4-6 conducted Radio Frequency Interference immunity – 10 VRMS voltage – Criteria A: fully functional ■ Input protection against -30 V reverse polarity ■ Ambient temperature: -25 to 85 °C Features ■ 2 channel topology – Low side input with common ground ■ Wide range input DC Voltage: – VI = - 0.3 to 30 V with RI = 0 Ω – VI = - 30 to 35 V with RI = 750 Ω ■ ■ Current limiter: – 3 to 7.5 mA programmable reference – ILIM = 6.1 mA to 8.8 mA with RREF = 10 kΩ – ILIM = 2.8 mA to 4.3 mA with RREF = 22 kΩ – Narrow limiter spread: < 17 % – Temperature compensated operation Output drive: – No output activation below 2 mA input current – 1.5 mA minimum output activating current in opto-coupler mode – Programmable CMOS output mode option (VMOD > 2.9 V) ■ LED drive for sensor status: 4.4 mA typical with RREF = 10 kΩ ■ Input protection (RI = 750 Ω CIN = 22 nF) ■ IEC61000-4-2 electrostatic discharge ESD, Level 4 – In contact, ± 8 kV; in air, ± 15 kV – Criteria B: temporary disruption November 2005 Benefits ■ Enable input to meet type1, 2 and 3 characteristics of IEC61131-2 standard ■ Compatible operation with 2 & 3 wires proximity sensor according EN60947-5-2 standard ■ Flexible configuration driving either opto coupler, or CMOS bus controller input, or 12 V AS-interface network ■ Reduced overall dissipation ■ Enhanced functional reliability ■ Compact with high integration ■ Surface Mount Package for highly automated assembly ■ Insensitive to the on state sensor impedance Rev 1 1/18 www.st.com 18 PCLT-2A 1 Characteristics 1 Characteristics 1.1 IEC61000-4 standard compliance application diagrams Figure 1. Isolated digital input diagram with opto-coupler driving output VI VIN OUT1 IN1 2 wires sensor RI CI RI CI LED1 3 wires sensor RC VCC VC IN2 OUT2 VC LED2 REF MOD RREF CC COMP Reverse polarity 1N4007 Figure 2. COMS PCLT-2A Un-isolated digital input diagram with programmable CMOS output PCLT-2A VI VIN IN1 2 wires sensor 3 wires sensor RI CI RI CI RC CC IN2 IN2 OUT2 VC LED2 REF MOD VDD COMS VSS RREF Supply voltage protection SM15T39 IN1 LED1 VC VCC OUT1 COMP BUS CONTROLLER Reverse polarity 1N4007 VDD GND VCC 2/18 5V SUPPLY PCLT-2A 1.2 1 Characteristics PCLT-2A Pinout and current limited termination block diagram Figure 3. Pinout Figure 4. IN1 1 14 OUT1 COMP 2 13 COMS IN2 3 12 OUT2 Termination block diagram CURRENT LIMITER ILIM OUTPUT INTERFACE LED1 IN1 LO 60% . I LIM OPTO 4 11 COMS VC 5 10 MOD N.C. 6 9 LED1 REF 7 10% . I LIM EN OVER VOLTAGE PROTECTION COMP LED2 8 VMOD MOD VDD 50µA EN 1.4 V VCC IN1 COMP N.C.: Not Connected OUT1 LO 30% . I LIM CMOS LO 2mA 5V CHANNEL #1 IN2 LED2 CURRENT REFERENCE VC CHANNEL #2 OUT2 BIASING CIRCUIT COMS REF Static characteristic of a type-2 digital input using PCLT-2A 30 30 VF = 0.7V; R I = 750W VI = V IN + V F + RI x IIN 25 RI 6.1 8.5 8.8 20 ON D VI (V) 1.3 15 11 10 11 OFF 5 2 0 0 2 6 30 IIN (mA) 3/18 PCLT-2A 1 Characteristics 1.4 Absolute ratings Symbol Pin Parameter name & conditions Value Unit VCC VC Power supply steady state voltage, RC = 2.2 kΩ - 0.3 to 35 V VC VC Supply steady state voltage, RC = 0 kΩ - 0.3 to 30 V VIN IN Input steady state voltage, RI = 0 kΩ - 0.3 to 30 V V IN Input steady state voltage, RI = 750 Ω -30 to 32 VI (Note: 1) Input repetitive pulse voltage, RI = 750 Ω -30 to 35 V Input maximum forward current RI = 750 Ω RC = 2.2 kΩ 10 mA Input maximum reverse current RI = 750 Ω RC = 2.2 kΩ (Note 2) 20 mA Maximum applied CMOS supply voltage 14 V Maximum applied output voltage, VMOD < 0.75 V 2.5 V Maximum applied output voltage, VMOD > 2.9 V 14 V - 4 to 7 mA - 25 to 150 °C IIN IN VMOD MOD VOM OUT, LED IOM OUT, LED TJ ALL 1.5 Output driver current Junction temperature range Recommended operating conditions Symbol Pin Parameter name & conditions Value Unit VCC VC Power supply steady state voltage, RC = 2.2 kΩ 19 to 35 V VC VC Power supply voltage range 14 to 27 V VI (Note1) IN Input repetitive pulse voltage RI = 750 Ω RC = 2.2 kΩ - 30 to 30 V VMOD Operating CMOS mode voltage range 2.9 to 5.5 V MOD 13.5 V Operating Ambient temperature range - 25 to 85 °C Operating Junction temperature range - 25 to 150 °C TAMB TJ Maximum operating 12V Analog voltage ALL Note: 1 VI = VIN + VF + RI x IIN with VIN = voltage at the PCLT-2A input pin; VCC = VC + RC x ICC with VC = voltage at the PCLT-2A power supply pin. 2 Respect to the reverse polarity test of one input as shown on Figure 12. 4/18 PCLT-2A 1.6 1 Characteristics Electromagnetic compatibility ratings TJ=25 °C, RI = 750 Ω RC = 2.2 kΩ , & reverse diode connected (unless otherwise specified) Symbol IN VCC VESD Value Node Parameter name & conditions Unit ESD protection, IEC 61000-4-2, per input, in air ± 15 kV ESD protection, IEC 61000-4-2, per input, in contact ±8 kV ESD protection, IEC 61000-4-2, per input, in air, RI = 0 Ω ±3 kV ESD protection, IEC 61000-4-2, per input, in contact, RI = 0 Ω ±3 kV ±4 kV VPPB VI Total Peak Pulse Voltage Burst, IEC61000-4-4 CC = 33 nF, CI = 22 nF, F = 5 kHz (Note 1) VPP VI Peak Pulse Voltage Surge, IEC61000-4-5, R = 42 Ω (Note 2) ± 500 V VPP VI Peak Pulse Voltage Surge, IEC61000-4-5, R = 42 Ω RI = 1200 Ω (Note 2) ± 1000 V VPP VCC Peak Pulse Voltage Surge, IEC61000-4-5, R = 2 Ω (Note 2) ± 1000 V Note: 1 Test diagram described on Figure 1 using the application PCB with a normalized capacitive coupling clamp 2 Test diagram described on Figure 1 1.7 Symbol RTH JA Thermal resistance Parameter name & conditions Thermal resistance Junction to ambient Board copper surface = 1.25 cm², copper thickness = 35 µm, single face Value 100 Unit °C/W 5/18 PCLT-2A 1 Characteristics 1.8 DC electrical characteristics (TJ = 25 °C, VCC = 24 V, RREF = 10 kΩ RC = 2.2 kΩ and referred to COM pin voltage, unless otherwise specified) Symbol Pin Name Conditions Min Typ Max Unit Input limiting current VIN = 4.5 to 26 V VOUT = 0.9 to 1.5 V VLED = 1.5 to 2.5 V TAMB =-25 to 85 °C RREF = 10 kΩ 6.1 7.6 8.8 mA Input limiting current VIN = 5.5 to 26 V VOUT = 0.9 to 1.5 V VLED = 1.5 to 2.5 V TAMB =-25 to 85 °C RREF = 22 kΩ 2.8 3.6 4.3 mA Low current input voltage IIN = 100 µA 1.5 3 V Current limitation ILIM ILIM VLOW IN IN IN Current limiter activation voltage IIN=6 mA - 2.6 - V IIN=2 mA, RREF=22 kΩ - 2.3 - V 31 38 - V VMOD = 0 V, VI = 5 V, (Note 1) - 10 40 µA VMOD = 0 V, IIN=2 mA, (Note 2) - 10 40 µA IIN = 2 mA 0.1 0.2 V VMOD = 0 V, IIN = 2 mA 0.02 0.1 V 20 % VMOD V Input & Supply Protection VCL IN, VC Clamping voltage IIN = 7 mA, tP = 1 ms, RREF open Output interface operation IOFF OUT LED Off state output current VOFF LED Off state LED voltage VOFF ION VON ION 6/18 OUT Off state output voltage VMOD > 2.9 V, IIN = 2 mA OUT OUT LED On state opto-coupler current On state output voltage On state LED current VMOD = 0 V, VOUT = 1.5 V VIN =4.5 V 1.5 2 mA VMOD = 0 V, VIN = 5.5 V, RREF = 22 kΩ , VOUT = 1.5 V 0.5 0.9 mA VMOD > 2.9 V RREF = 10 kΩ , VIN > 4.5 V RREF = 22 kΩ VIN > 5.5 V 80%. VMOD VIN = 4.5 V, VLED = 2.5 V (Note 3) 3.5 4.4 mA VIN = 5.5 V, RREF = 22 kΩ VLED = 2.5 V 1.4 2.1 mA PCLT-2A Symbol 1 Characteristics Pin Name Conditions Min Typ Max Unit 2.9 V 50 65 µA Output operation selection circuit VTH MOD MOD Opto-CMOS threshold I OUT OUT CMOS output current VMOD = 12V Supply current VCC = 30V 1.5 2 mA VMOD = 5V, VIN open 0.25 0.35 mA VMOD = 12V, VIN open 0.4 0.8 mA 0.75 35 Power supply circuit IC VC IDD MOD CMOS supply current Note: 1 According to application diagram ( Figure 1) with the use of a RI = 750 Ω resistor a reverse diode from COM to GND (VF = 0.7 V) and an opto-coupler (RLED (0V) = 15 kΩ , VF=1.2 V). 2 Same as note 1 above, but RI= 0 . 3 When no LED diode is used, connect LED pin to the COMP ground. 1.9 Switching electrical characteristics (TJ=25°C, VCC = 24 V, RC = 2.2kΩ, CI = 0 and COM pin voltage referred unless otherwise specified) Symbol Pin Name Conditions Min Typ Max Unit FMAX IN-OUT Input to output operating frequency Duty cycle = 50% 5 kHz TPLH IN-OUT Input Lo to Hi propagation time CI = 0 16 µs CI = 0, VMOD = 0 V 0.1 CI = 0, VMOD = 5 V COUT = 50 pF 7.6 TPHL IN-OUT Input Hi to Lo propagation time µs 7/18 PCLT-2A 1 Characteristics 1.10 Functional characteristics Figure 5. Variation of the input-output propagation delay time TPLH at rising edge versus the supply voltage VCC with RC = 2.2 kΩ TPLH (µs) 19 18.5 18 17.5 17 16.5 16 15.5 15 14.5 VC (V) 14 10 Figure 6. 12 14 16 18 20 22 24 26 28 Typical current limiter variation versus junction temperature ILIM / ILIM at Tj = 25 °C 1.01 1.00 0.99 Vin = 27.5 V 0.98 0.97 Vin = 5 V 0.96 0.95 Tj (°C) 0.94 -40 8/18 -20 0 20 40 60 80 100 120 140 PCLT-2A Figure 7. 1 Characteristics Typical current limiter variation versus reference resistance RREF ILIM (mA) 10 9 Vc = 27 V, Vin = 25 v, Vout = 0.9 V, Vled = 1.5 V 8 7 6 5 4 3 2 RREF (kΩ) 1 0 0 Figure 8. 5 10 15 20 25 30 Typical limiter activation voltage variation versus junction temperature VLOW (V) 3.0 2.5 Iin = 6.1 mA Iin = 2.2 mA 2.0 Tj (°C) 1.5 -25 Figure 9. 0 25 50 75 125 100 150 Thermal resistance variation versus copper area (35 µm layer thickness; 50vias/cm2 and 300 µm via diameter in double layer) 150% Rth(j-a)/Rth(1.25 cm2) 140% 130% 120% 110% 100% 90% PCB single layer PCB double layer 80% 70% Copper area (cm ² ) 60% 0 0.5 1 1.5 2 2.5 3 3.5 4 9/18 2 Functional description 2 PCLT-2A Functional description The PCLT-2A is a dual input termination device designed for 24 V DC automation applications. It achieves the front-end circuitry of a digital input module (I/O) in industrial automation. Available in a two channels configuration, it offers a high-density termination by minimizing the conducting dissipation and the external components count. It is housed in a surface mount package to reduce the printed board size. Made of an input voltage protection, a serial current limiting circuit and an output interface, each channel circuit terminates the connection between the logic input and its associated high side sensor or switch. The PCLT-2A is a current limited dual channel circuit compatible with the type 2 (7.5 mA) or type 3 (3 mA) characteristic of the IEC61131-2 standard. An external resistance RREF allows the limiting current value to be adjusted from 3 to 7.5 mA. The unique structure of the PCLT limiter allows its activation threshold to be low and insensitive to the output voltage up to 2.5 V. Each input voltage clamping block protects the module input against electromagnetic interferences such as those described in the IEC61131-2 standard and IEC61000-4-2 (ESD), 4-4 (transient burst), 4-5 (voltage surge) and 4-6 (conducted radio frequency interferences) standards. The supply input is also designed with such a protection structure. The current limiting circuit connected between the input and the output pins is compensated all over the temperature range. Thanks to its low tolerance, the current limitation allows reducing drastically the dissipation of the input compared to a resistive input. Furthermore, the PCLT2 is housed into a very low RTH exposed pad TSSOP14 package that allows the PCB cooling pad to be reduced: the overall module becomes smaller and the hot spot effect is reduced. The output block of each termination channel transfers the input logic state to a logic output and a Light Emitting Diode (LED) that allows this state to be checked visually. 2.1 The VMOD pin The voltage VMOD applied to the selector pin MOD allows the output OUT to be configured either in an opto-coupler driver for VMOD less than 0.75 V or in a CMOS output able to interface directly a bus controller circuit for VMOD higher than 2.9 V. In CMOS mode, the VMOD pin activates a CMOS compatible buffer output, able to source up to a 50 µA current powered by the MOD pin. 2.2 OFF state In accordance with IEC61131-2 standard, for both opto-coupler and CMOS configuration modes when the input current is less than 2 mA (type 2) or 1.5 mA (type 3) the output circuits divert all the input current and maintain both LED and output in OFF state. 10/18 PCLT-2A 2.3 3 Surge voltage test circuit ON state When the module input voltage VI, including the 750 Ω input resistor and the reverse diode, is higher than 11V corresponding to a PCLT input voltage VIN of 5V, both LED and output circuits are in ON state. The input current is then shared between the internal circuitry, the LED (about 60 %), and the driver output (about 30 %) in case of opto-coupler mode. In CMOS mode, the CMOS level is defined by the VMOD voltage that is equal the supply voltage VDD of the bus controller: it can be 3.3 V or 5 V. The output voltage is delivering 80 % of VDD for high state and 20 % VDD for low state. When no LED diode is used, the LED outputs pin must be connected to the ground COMP of the circuit to allow the current to flow back to the power supply. 3 Surge voltage test circuit The input and supply pins are designed to withstand electromagnetic interferences. They are protected by a clamping diode that is connected to the common pin COM. Combined with the serial input resistance RI, this clamping diode is effective against the fast transient bursts (±4 kV, IEC61000-4-4) and the voltage surges (±1 kV,IEC61000-4-5). This topology allows the surge voltage to be applied from each input to other inputs, the ground and the supply contacts in differential or common modes (see figure 10). Thanks to its high resistance RC = 2.2 kΩ and the conventional power supply protection that uses a clamping diode such as the SM15T39C Transil™, the supply pin VC withstands ±1000 V surge voltage according to IEC61000-4-5 (see figure 11). Figure 10. Input pin IN voltage surge test circuit VPP = ±500 V with 42 Ω VCC RC VC Figure 11. Supply pin VC voltage surge test circuit PCLT-2 RC VCC VC RI VPP IN1 I VPP RI PCLT-2 RI IN1 ±1kV 2Ω IN2 RI RI IN2 SM15T39C ±1 kV 42 Ω VPP GND GND COM COMP 5 nF 5 nF PE/FE PE/FE TM: Transil is a trademark of STMicroelectronics 11/18 PCLT-2A 4 Input reverse polarity robustness 4 Input reverse polarity robustness Each input of the PCLT circuit may be biased to a reverse polarity equal to - VCC. This case corresponds to a connection mistake or a reverse biasing that is generated by the demagnetization of a monitored inductive solenoid. The involved input withstands the high reverse current up to 20 mA; its opto-coupler is OFF and is protected by the conducting input diode. The input remains operational, and some extra dissipation should be take place in their clamping protections. Figure 12. Current sharing in the PCLT device when IN2 is biased at -30 V and IN1 at +30 V. Vcc = + 30V 3.6mA 2.2 kΩ IN1 9.7mA VC VCL= 38 V IREG N OUT1 I1 = + 30V 750 Ω OPTO 1 1N4007 GND (0V) COM OPTO 2 750 Ω I2 = --30V 13.3mA IN2 IREG4 OUT2 PCLT-2 Considering the supply operation, a reverse blocking diode can be connected between the module ground and the common pin COM to protect the PCLT device against any spurious reverse supply connection. Then, the whole module supply voltage rating is extended to ± 30 V. 12/18 PCLT-2A 5 5 Programming of the PCLT-2A according to the input type requirement Programming of the PCLT-2A according to the input type requirement The operation of the PCLT-2 can be set to the various logic input types defined in the IEC61131-2 standard. The current reference of the input-limiting block of each channel is programmable thanks to an external resistor RREF. Moreover, because the operating current is different for each type, the external input resistor RI can be changed to improve the overvoltage robustness of the whole circuit. Table 1 describes the input characteristics requirements according to the IEC standard, and Table 2 the resistance values for the 1, 2, and 3 types and the corresponding performances of the PCLT input. Table 1. IEC61131-2 requirements for logic input Type 1 3 2 State Parameter Unit OFF IOFF MAX mA 0.5 1.5 2 VOFF MAX V 5 15 @ IOFF 5 11 @ IOFF 5 11 @ IOFF ION MIN mA 2 2 6 VON MIN V 15 11 11 1 3 2 ON Table 2. PCLT-2A setting for each type of logic input Type Setting Unit RREF kΩ 22 22 10 RI kΩ 2.2 1.2 0.75 RC kΩ 2.2 PERFORMANCES IIN MIN mA 2.8 2.8 6.1 IIN TYP mA 3.6 3.6 7.6 IIN MAX mA 4.3 4.3 8.8 ILED TYP mA 2.1 2.1 4.4 SURGE w/RI kV >1 1 0.5 ESD with RI kV 8 in contact, 15 in air (class 4) 13/18 PCLT-2A 6 Unisolated ASI-interface bus application diagram 6 Unisolated ASI-interface bus application diagram 6.1 AS-Interface Bus application overview The AS-Interface bus is a low-end field bus for actuators and sensors in manufacturing & industrial automation. Its electrical architecture uses an unshielded 2-wire yellow cable that transports both the 24 V power supply of the field nodes and the serial bi-directional data communication. Figure 13. Simplified architecture of AS-Interface bus. AS-i MASTER I/O SLAVE I/O SLAVE I/O SLAVE AS-i SLAVES The data communication is achieved with a current carrier modulation superimposed over the power wires. Therefore, the power bus terminals are filtered in order to maintain identical and calibrated differential and common mode impedances measured by both master and slave units. 6.2 Isolation of the sensor section and the supply from data/supply bus The PCLT can be designed as an interface between a proximity sensor and its associated slave controller unit. The sensor power supply is generated from the bus power supply with a filter and a regulator that are inserted in the slave unit. In the same manner, the sensor logic signal is isolated from the AS- Interface power supply bus to avoid any degradation of the data transmission. A conventional way to achieve the interface with the PCLT and the AS- Interface controller is to insert an opto-coupler between the AS-Interface controller and the PCLT that runs in optocoupler mode as shown on figure 1 (MOD=0). 14/18 PCLT-2A Un-isolated connection of the PCLT with AS-Interface controller To remove the opto-coupler the operation of the PCLT has been extended to fit the AS-Interface application. A precaution is required on its interface with the bus controller: the impedance between the two circuits must be high in order to maintain the impedance isolation. To achieve this impedance isolation, the PCLT runs in CMOS mode (MOD=VCC) and the buffer operation is extended up to VCC = 12 V. In the application, the VCC voltage is generated with a Zener diode reference fed from the sensor bus. Because of the buffer voltage increase, it becomes possible to insert high impedance between the PCLT output and the AS-Interface bus controller input. Typically a 100kΩ resistor is designed while keeping a 5 V CMOS operation on the input of the bus controller. Figure 14 shows the application diagram where the PCLT is connected to the slave bus controller through a 100 kΩ resistor. The logic signal is transmitted with a low level of less than 20% of the VDD supply voltage and a high level of at least 3.5 V defined by the PCLT output buffer limiting its current to 35 µA minimum and the 100 kΩ pull down resistor (0.035 mA times 100 kΩ). Figure 14. AS-Interface slave controller unit using the PCLT in an un-isolated manner. 30V Vreg 22nF 1 14 10 9 LED 10 kΩ 7 SLAVE AS-I 100 kΩ PCLT2 12V CONTROLLER 4.7nF 750 Ω sensor ASiP 100 kΩ VCCsensor 2.2 kΩ VCC 2.2 kΩ 28V 33nF 6.3 6 Unisolated ASI-interface bus application diagram ASiN 15/18 PCLT-2A 7 Package mechanical data 7 Package mechanical data DIMENSIONS REF. Millimeters Min. k C 0.25 mm Gauge plane Typ. A L Inches Max. Min. Typ. Max. 1.2 0.047 0.15 0.002 0.006 A1 0.05 A2 0.8 b 0.19 0.3 0.007 0.012 c 0.09 0.2 0.003 0.008 D 4.9 5.0 5.1 0.193 0.197 0.200 L1 1.0 A E 7 E 6.2 6.4 6.6 0.244 0.252 0.260 A1 E1 4.3 4.4 4.5 0.169 0.173 0.177 b e A2 E2 8 e L 0.65 0.45 0.6 0.025 0.75 0.018 0.024 0.029 D aaa C D1 14 1 PIN 1 INDENTIFICATION L1 k 1.0 0° aaa 8° 0.004 D1 3.6 0.142 E2 3.0 0.118 0.40 3.10 0.65 3.00 0° 0.1 6.80 4.40 0.70 0.039 8° Figure 15. Footprint 1.20 dimensions in mm 16/18 1.05 0.031 0.039 0.041 C Seating plane E1 PCLT-2A 8 8 Ordering information scheme Ordering information scheme PCLT - 2 A T4 P = current limiter programmability from 3 mA to 7 mA 2 = Number of Integrated channels A = EMC level: 500v according to IEC61000-4-5 for type 2 1000v according to IEC61000-4-5 for type 3 T4 = Package TSSOP14 9 Ordering information Ordering Code Marking Package Weight Base Qty Delivery Mode PCLT-2AT4 PCLT-2AT4 TSSOP14(1) 0.057g 96 Tube PCLT-2AT4-TR PCLT-2AT4 TSSOP14(1) 0.057g 2500 Tape & reel 1. Exposed pad version 10 Revision history Date Revision 16-Nov-2005 1 Changes Initial release. 17/18 PCLT-2A 10 Revision history Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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