cd00200596

AN2785
Application note
L6393 half bridge gate driver
Introduction
The L6393 is a versatile high-voltage gate driver IC particularly suited to motor driving
applications. It simplifies the design of control systems for a wide range of motor
applications such as home appliances, industrial drives, DC motors and fans.
Developed using BCD offline technology, the device can operate with voltage rails up to
600 V. The gate driver provides all the functions and current capability necessary for
high-side and low-side power MOS and IGBT driving.
The L639x are high voltage half-bridge gate drivers. These devices can be used in all
applications where high voltage shifted control is necessary. The devices have a driver
current capability best suited for motor driving ratings and they are also equipped with
patented internal circuitry which replaces the external bootstrap diode. This feature is
achieved by means of a high-voltage DMOS synchronously driven with the low-side gate
driver.
The L6393 is an half-bridge driver with several functionalities such as externally adjustable
dead-time, shut-down function and an uncommitted comparator. The outputs can be driven
by a special logic input interface particularly suitable for phase/brake functions. The device
is available in DIP-14 or SO-14 packages.
Figure 1.
L6393 application block diagram
BOOTSTRAP DRIVER
VCC
4
UV
DETECTION
FLOATING STRUCTURE
from LVG
14
BOOT
UV
DETECTION
H.V.
HVG
DRIVER
PHASE
1
S
LEVEL
SHIFTER
13
HVG
12
OUT
Cboot
R
LOGIC
BRAKE
3
SHOOT
THROUGH
PREVENTION
VCC
SD
TO LOAD
LVG
DRIVER
LVG
2
10
CPOUT
6
5V
COMPARATOR
+
9
CP+
8
CP-
-
DT
5
DEAD
TIME
GND
December 2009
7
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1/51
www.st.com
Contents
AN2785
Contents
1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
UVLO function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
Dead time function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1
6
CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.1
6.2
Basic topology: single half-bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.1.1
VCC supply pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.1.2
BOOT (floating) supply pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1.3
Logic input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1.4
Dead time pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1.5
Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1.6
Gate driver outputs: gate lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Full-bridge topology: single-phase fan motor driver . . . . . . . . . . . . . . . . . 15
6.2.1
Current mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.2.2
Voltage mode - example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2.3
Voltage mode - example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3
Full-bridge topology: brush DC motor driver . . . . . . . . . . . . . . . . . . . . . . 21
6.4
Gate driving: principle of working with inductive loads . . . . . . . . . . . . . . . 23
7
Induced turn-on phenomenon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8
How to increase the gate driver output current capability . . . . . . . . . 34
9
Below-ground voltage on the OUT pin . . . . . . . . . . . . . . . . . . . . . . . . . 36
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9.1
Below-ground voltage phenomenon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9.2
How to reduce the below ground spike voltage . . . . . . . . . . . . . . . . . . . . 38
9.3
Issues related to the below-ground voltage phenomenon . . . . . . . . . . . . 41
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Contents
9.4
9.3.1
VBOOT voltage safe operating condition . . . . . . . . . . . . . . . . . . . . . . . . 41
9.3.2
Bootstrap capacitor overcharging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Functionality of L6393 outputs in below-ground condition . . . . . . . . . . . . 44
9.4.1
Steady-state (DC) conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.4.2
Transient conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.4.3
Below-ground voltage spikes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10
Layout suggestions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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List of figures
AN2785
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
on OUT pin
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
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L6393 application block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Input configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
L6393 gate driver outputs in UVLO condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Timing waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Typical dead time vs DT resistor value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
External charge pump. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Typical schematic of power half-bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Layout suggestions for the gate driving circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Application circuit for current mode FAN controller using two L6393 drivers . . . . . . . . . . . 16
Current modulation (flowing in the shunt resistor) changing the Vth signal . . . . . . . . . . . . 17
L6393 application circuit for voltage mode FAN controller (logic output hall sensor) . . . . . 19
L6393 application circuit for voltage mode FAN controller (linear hall sensor) . . . . . . . . . . 20
Waveform related to the VM application circuit with linear hall sensor . . . . . . . . . . . . . . . . 21
L6393 application circuit for brush DC motor controller (current mode) . . . . . . . . . . . . . . . 22
Gate driver output buffers: equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Hard and soft switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Turn-ON hard switching details with induction load: gate charge and plateau phase . . . . 26
Total equivalent circuit for turn-ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Turn-OFF hard switching details with induction load: gate charge and plateau phase. . . . 28
Total equivalent circuit for turn-OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Power dissipation during switching (approximation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Rgate dimensioning criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Induced turn ON phenomenon - circuital description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Block diagram of output current capability enhancement using external current buffers . . 34
Example of a gate driving circuit with current buffers to increase current capability. . . . . . 35
Below-ground voltages in L6393 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Transient peak forward voltage vs. dIF/dt of STTH1L06 diode . . . . . . . . . . . . . . . . . . . . . . 37
Use of OUT resistor to limit the below ground voltage spike on OUT pin. . . . . . . . . . . . . . 39
Use of combination of OUT resistor and OUT diode to limit the below ground voltage spike
40
Bootstrap overcharging due to below-ground voltage on OUT pin . . . . . . . . . . . . . . . . . . . 42
Different bootstrap network characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
L6393 safe operating range when OUT pin is below ground voltage (in steady state). . . . 44
Driver functionality in below-ground voltage condition on OUT pin . . . . . . . . . . . . . . . . . . 44
OUT below-ground voltage in transient conditions: limited boot overcharging . . . . . . . . . 46
Example of below-ground voltage spike . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Layout suggestion for a H-bridge power system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Doc ID 14785 Rev 1
AN2785
1
Pin description
Pin description
Table 1.
Pin description
Pin n.
Pin name
Type
1
PHASE
I
Driver logic input (active high)
2
SD
I
Shut-down logic input (active low)
3
BRAKE
I
Driver logic input (active low)
4
VCC
P
Lower section supply voltage
5
DT
I
Dead time setting
6
CPOUT
O
Comparator output (open drain)
7
GND
P
Ground
8
CP-
I
Comparator negative input
9
CP+
I
Comparator positive input
O
Low side driver output
10
LVG
(1)
11
NC
12
OUT
(1)
13
HVG
14
BOOT
Function
Not connected
P
High side (floating) common voltage
O
High side driver output
P
Floating section (bootstrap) supply voltage
1. The circuit provides less than 1 V on the LVG and HVG pins (at Isink = 10 mA), with VCC > 3 V. This allows
omitting the “bleeder” resistor connected between the gate and the source of the external MOSFET
normally used to hold the pin low; the gate driver also ensures low impedance in SD condition.
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Logic inputs
2
AN2785
Logic inputs
In the L6393 IC the two input signals (PHASE and BRAKE) are fed into an AND logic port
and the resulting signal is in phase with the high-side output HVG and in opposition of phase
with the low-side output LVG. This means that if BRAKE is held high, the PHASE signal
drives the half bridge in phase with the HVG output and in opposition of phase with the LVG
output. If BRAKE is set to low, the low-side output LVG is always ON and the high-side
output HVG is always OFF, regardless of the PHASE signal. This kind of logic interface
provides the possibility of controlling the power stages using the PHASE signal to select the
current direction in the bridge and the BRAKE signal to perform current slow decay on the
low sides or even a brake function on the low-side power transistors in case of multi-phase
power bridges (for example, full or 3-phase bridges).
From the point of view of logic operations, the two signals PHASE and BRAKE are
completely equivalent, meaning that the two signals can be exchanged without changing the
behavior on the resulting output signals (see the block diagram in Figure 1 on page 1).
Note:
The dead time between the turn OFF of one power switch and the turn ON of the other
power switch is defined by the resistor connected between the DT pin and ground.
Figure 2.
Input configurations
LEVEL
SHIFTER
PHASE
HVG
DEAD
TIME
BRAKE
LVG
SD
All the logic inputs are provided with hysteresis (~1 V) for low noise sensitivity and are
TTL//CMOS 3.3 V-compatible. Thanks to this low voltage interface logic compatibility, the
L6393 can be used with any kind of high performance controller, such as microcontrollers,
DSPs or FPGAs.
As shown in the block diagram of Figure 1 the logic inputs have internal pull-down resistors.
The purpose of these resistors is to set a proper logic level in case, for example, there is an
interruption of the logic lines or the controller outputs are in tri-state conditions: if logic inputs
are left floating, the gate driver outputs LVG and HVG are set high and low respectively. The
internal resistors are:
6/51
●
PHASE logic input: 375 kΩ (typ.) pull-down.
●
BRAKE logic input: 375 kΩ (typ.) pull-down.
●
SD logic input: 500 kΩ (typ.) pull-down.
Doc ID 14785 Rev 1
AN2785
Logic inputs
Table 2.
L6393 truth table
Inputs
Note:
Outputs
SD
Phase
BRAKE
LVG
HVG
L
X
X
L
L
H
L
L
H
L
H
L
H
H
L
H
H
L
H
L
H
H
H
L
H
X: don’t care.
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UVLO function
3
AN2785
UVLO function
The L6393 supply voltage VCC is continuously monitored by an under-voltage lock-out
(UVLO) circuitry, which turns off the IC outputs when the supply voltage goes below the
VCC_thOFF threshold (see L6393 datasheet for values) and turns on the device when the
supply voltage goes above the VCC_thON voltage. A hysteresis of about 1.5 V is provided for
noise rejection purposes. The high voltage floating supply BOOT is also provided with a
similar under-voltage lock-out circuitry. When the L6393 is in a UVLO condition, both gate
driver outputs are set to low, setting the half-bridge power switches to high impedance.
Figure 3 shows the I-V characteristics of the output buffers at different VCC values.
Figure 3.
L6393 gate driver outputs in UVLO condition
L6393 output buffer characteristic in UVLO condition
ILVG/HVG
(mA)
VCC = 15V
VCC = 9V
VCC = 7V
100
VCC = 6V
90
80
VCC = 5V
70
60
VCC = 4V
50
40
30
VCC = 3V
20
10
VCC = 2V
VCC = 0V
0
1
VCC = 1V
2
3
4
5
NOTE: when VCC < VLVG/HVG
the body diode of the p-channel (source)
turns ON and clamps the VLVG/HVG voltage
TEST CIRCUIT
GATE DRIVER
OUTPUT BUFFER
(LS/HS)
VCC/BOOT
p-channel
(source)
OFF
LVG/HVG
ON
+
VCC
+
VLVG/HVG
n-channel
(sink)
GND/OUT
8/51
ILVG/HVG
A
Doc ID 14785 Rev 1
VLVG/HVG
(V)
AN2785
Dead time function
To avoid any possible cross-conduction between the power MOSFETs/IGBTs of the half
bridge, the L6393 provides a dead time. The dead time function is a safety time introduced
by the device between the falling edge transition of one driver output and the rising edge of
the other output. The dead time can be adjusted externally through the value of the DT
resistor connected between pin 5 and pin 7 as indicated in Figure 5. A 100 nF ceramic
capacitor in parallel to this resistor is recommended for noise immunity. Figure 4 provides
details of the dead time.
Figure 4.
Timing waveforms
PHASE
BRAKE
LVG
DTLH
DTLH
DTHL
DTHL
HVG
Figure 5.
Typical dead time vs DT resistor value
3.5
3
2.5
DT (us)
4
Dead time function
2
1.5
1
0.5
0
0
50
100
150
200
250
300
Rdt (kOhm)
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9/51
Bootstrap driver
5
AN2785
Bootstrap driver
A bootstrap circuitry is needed to supply the high voltage section. This function is normally
accomplished by a high-voltage fast recovery diode (Figure 6 a). In the L6393 a patented
integrated structure replaces the external diode. It is realized with a high-voltage DMOS
driven synchronously with the low-side driver (LVG), with a diode in series, as shown in the b
part of Figure 6 on page 11. An internal charge pump (Figure 6 b) provides the DMOS
driving voltage.
5.1
CBOOT selection and charging
To choose the proper CBOOT value the external MOS can be seen as an equivalent
capacitor. This capacitor CEXT is related to the total gate charge of the MOS.
Equation 1
CEXT =
Q GATE
VGATE
The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage
loss. It must be:
Equation 2
CBOOT >> CEXT
For example, if Qgate is 30 nC and Vgate is 10 V, CEXT is 3 nF. With CBOOT = 100 nF, the
drop would be 300 mV.
If HVG has to be supplied for a long time, the CBOOT selection must also take into account
the leakage and quiescent losses.
For example, since the HVG steady state consumption is lower than 200 µA, if HVG TON is
5 ms then CBOOT has to supply 1 µC to CEXT. This charge on a 1 µF capacitor means a
voltage drop of 1 V.
The internal bootstrap driver gives a great advantage: the external fast-recovery highvoltage diode can be avoided (it usually has great leakage current). This structure works if
VOUT is close to GND (or lower) while LVG is on. The charging time (Tcharge) of CBOOT is the
time in which both conditions are fulfilled and it has to be long enough to charge the
capacitor.
The bootstrap driver introduces a voltage drop due to the DMOS RDS(on). At a low frequency
operation this drop can be neglected, but if the frequency is increased the drop must be
taken into account.
The following equation is useful to compute the drop on the bootstrap DMOS.
Equation 3
VDROP = ICHARGE ⋅ RDSON → VDROP =
Q GATE
⋅ RDSON
TCHARGE
where Qgate is the gate charge of the external power MOS, RDS(on) is the ON resistance of
the bootstrap DMOS and TCHARGE is the charging time of the bootstrap capacitor.
10/51
Doc ID 14785 Rev 1
AN2785
Bootstrap driver
For example: given the typical value of 120 Ω for RDS(on) and using a power MOS with a
total gate charge of 30 nC, the drop on the bootstrap DMOS is about 1 V if the TCHARGE is
6 ms. In fact:
Equation 4
VDROP =
30nc
⋅ 120Ω ≈ 0.7
5μs
VDROP has to be considered when the voltage drop on CBOOT is calculated: if this drop is too
high, or the circuit topology does not allow a sufficient charging time, an external diode can
be used.
When operating at very low frequencies, the high side driver ON time of the high-side driver
can be very long. Therefore the CBOOT voltage can drop because of HVG steady-state
consumption. To avoid extremely large capacitors (> 1-2 µF), an external charge pump can
be added (see Figure 7 as example). It is mandatory for the diodes to have a low parasitic
capacitance since C1 and C2 should be greater than the capacitance of the diodes. The
oscillator has to work in order to balance the high-voltage side consumption, and the
minimum frequency is fixed by the values of C1 and C2 (with C1 = C2 = 33 pF then f > 250
– 300 kHz).
Figure 6.
Bootstrap driver
DBOOT
BOOT
VCC
BOOT
VCC
H.V.
HVG
H.V.
HVG
CBOOT
CBOOT
OUT
OUT
TO LOAD
TO LOAD
LVG
LVG
a
b
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11/51
Bootstrap driver
Figure 7.
AN2785
External charge pump
HV
VBOOT
Cboot
200nF
HVG
L639x
OUT
LOAD
330pF
LVG
GND
C1
33pF
C2
33pF
VCC
HCF4069UB
Cx
12/51
Doc ID 14785 Rev 1
AN2785
Application examples
6
Application examples
6.1
Basic topology: single half-bridge
A typical schematic for one half-bridge is shown in Figure 8.
Figure 8.
Typical schematic of power half-bridge
H.V.
+
15V
-
+
10 uF
25V
CVCC1
CVCC2
100 nF
25V
VBOOT
VCC
GND
DH
L6393
100 uF
400V
STGP10NC60HD
0 Ω 0.25W
OUT
TO LOAD
BRAKE
SD
33 Ω 0.25W
RGH_OFF
1N4148
+
HS
RGH_ON
HVG
PHASE
FROM CONTROLLER
CHV
100 nF
25V
FROM CONTROLLER
FROM CONTROLLER
CBOOT
LS
RGL_ON
LVG
33 Ω 0.25W
DL
1N4148
STGP10NC60HD
RGL_OFF
0 Ω 0.25W
DT
47 kΩ
0.25W
RDT
100 nF
25V
CDT
CPOUT
CP+
CP-
The half-bridge comprises two power switches such as IGBTs (or MOSFETs), one high-side
and one low-side. When the high-side switch is ON, it brings the output voltage of the halfbridge to the HV bus voltage, which can be a high DC voltage power supply with large power
availability, while the low-side switch shorts the output to the power ground voltage when it is
ON. Thanks to the internal floating structure for the high-side switch driving, n-type IGBTs
(or n-channel MOSFETs) can be used. The gate driver works exactly like a digital/analogpower interface between the controller and the power stage. Note that it is usually
recommended (not mandatory) to have some gate resistances between each power switch
gate and the corresponding gate driver output, in order to limit current during the gate
charge.
6.1.1
VCC supply pin
Regarding the VCC pin, a local filtering of the supply voltage very close to the L6393 IC is
recommended. Generally, the suggestion is to use two capacitors, one electrolytic with a
greater value (CVCC1 = 10 µF, for example), which has a great energy capability but also a
non-negligible ESR (so is quite slow in providing the current) and a second smaller ceramic
capacitor (CVCC2 = 100 nF) which has a lower ESR value but a lower energy capability. The
first capacitor works mainly as the bulk energy storage while the second is able to supply the
dynamic current spikes required by the commutations of the device, so is better for highfrequency decoupling of the IC supply voltage.
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Application examples
6.1.2
AN2785
BOOT (floating) supply pin
To supply the high-side floating section of the gate driver, the bootstrap capacitor must be
placed between the BOOT pin 14 and the OUT pin 12. For a detailed description of the
proper dimensioning of the bootstrap capacitor, refer to Chapter 5. The capacitor must be
placed as close as possible to the related IC pins. The bootstrap diode required for the
charge of the bootstrap capacitor is integrated inside the L6393 device.
6.1.3
Logic input pins
The logic input pins must be connected to the controller with the guidelines provided in
Chapter 2. If the application environment is very noisy and the logic input voltage is low (for
example, 3.3 V), it can be useful to place some small RC network (not showed in Figure 8)
in series with the logic input lines, in order to avoid false input triggering due to external
noise.
6.1.4
Dead time pin
The resistance value on the DT pin must be selected as per the indications in Chapter 4 and
in Figure 5. It is recommended to connect a capacitor with a value of at least 100 nF
between the DT and GND pins, as close as possible to the IC and with short PCB tracks.
6.1.5
Comparator
The comparator is completely uncommitted and both the two input pins are externally
available. Attention must be paid to the output pin CPOUT, which is inverted with respect to
the comparator inputs due to the open-drain transistor connected to the output.
6.1.6
Gate driver outputs: gate lines
The gates of the power switches and the gate driver outputs can be connected directly, but
usually some gate resistors are placed in series on the gate lines in order to limit the gate
current during commutations. The final target is to control the dVOUT/dt of each half-bridge
output and then reduce the EMI. A more detailed explanation of the mechanisms behind the
dVOUT/dt control through the gate resistors is provided in Section 6.4. The following
calculations should be considered as approximated analyses of the gate charge
phenomenon, and therefore, in order to obtain the proper sizing of the gate resistor, it is
always strongly recommended to evaluate the resulting power bridge transitions through
bench analyses.
As shown in Figure 8, the gate line is split into two paths, one for the turn ON (with, in the
example, a gate resistor of 33 Ω) and the other one for the turn OFF, using a small signal
diode as path selector. Using this specific topology, the equivalent turn OFF resistance is in
a first approximation the parallel of the turn OFF and the turn ON resistances (neglecting the
diode drop). In the example, the turn OFF resistance is set to 0 Ω to provide the lowest
resistance path for the turn OFF of the IGBT. In fact, as explained in the two following
paragraphs, low impedance on the gate driver turn OFF helps to reduce the induced turn
ON phenomenon.
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Regarding the layout of such gate lines, it is always strongly recommended to place the
power IGBT (or MOSFETs) very close to the gate driver. It is important to reduce as much
as possible the lengths of such line paths as well as the areas included in the gate circuits,
because these can act as weak antennas and could catch noise from the surrounding
environment. The larger these areas, the higher the gain of such undesired antenna circuits.
Figure 9.
6.2
Layout suggestions for the gate driving circuits
Full-bridge topology: single-phase fan motor driver
This paragraph provides a set of different example circuits using L6393 ICs for driving
typical brushless single-phase permanent-magnet fan motors. The power stage topology
used is full-bridge. Refer to paragraph 6.1 and 6.4 for the proper sizing of the L6393 external
component.
The main purpose of the following examples is to show how such kinds of systems can be
controlled without any additional microcontrollers – and make the application a complete
stand-alone solution – by using the proper combination of L6393 IC gate drivers and a very
limited set of external components.
6.2.1
Current mode
An application circuit with full-bridge topology controlled in current mode through two L6393
devices is shown in Figure 10.
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Figure 10. Application circuit for current mode FAN controller using two L6393
drivers
Rotation Detection
FG
Logic Output
HALL Sensor
Signal Inverter
RD
+5V
+5V
+5V
COMPARATOR
PHASE
H
PHASE
+
_
Full Bridge Power Stage
Vbus
Logic + Drivers
Logic + Drivers
HVG
HVG
Motor Load
PHASE
SD
BRAKE
PHASE
SD
SD
BRAKE
LVG
LVG
Torque Input
with minimum
threshold limiter
+5V
COMPARATOR
BRAKE
SD
+12V
+
_
Vth
PWM Current Control
OFF Time
EQUIVALENT CIRCUIT USING L6393 DRIIVERS
+5V
Logic Output
HALL Sensor
+5V
H
CP+
HVG
CP-
+5V
VCC
FG
+12V
RD
OUT
L6393
SD
LVG
BRAKE
DT
CPOUT
GND
PHASE
VBOOT
CP+
Torque Input
with minimum
threshold limiter
Vth
+5V
VCC
+12V
Over Current
Disable Time
Dead Time
Setting
HVG
CP-
+12V
+12 ÷ 600V
VBOOT
PHASE
Rotation Detection
OUT
L6393
SD
LVG
BRAKE
DT
CPOUT
GND
Dead Time
Setting
SD
In the application circuit shown in Figure 10, the fan rotor position information is provided by
the Hall sensor (with logic output) through a logic signal having the same frequency and the
same phase of the rotor. This signal can be used to select which diagonal of the full-bridge
must be turned ON starting from a certain rotor position. In fact, the targeted fan motor is a
typical single-phase BLDC motor that requires synchronous driving with the rotor position.
This operation is very simply implemented with the L6393 IC gate driver thanks to its logic
signal management: the PHASE signal is in phase with the high-side output and in
opposition of phase with the low-side output. This means that in order to turn ON a certain
full-bridge diagonal the hall sensor signal can be directly fed to the PHASE input of one
L6393 and the inverted signal to the PHASE input of the other L6393.
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In the example of Figure 10 the logic inversion of the hall signal is provided by a comparator
which acts as a logic inverter. The comparator is directly available in one of the two L6393
drivers. The remaining comparator, belonging to the other L6393 IC, can be used as in the
example to provide a PWM current control by comparing the sense voltage coming from the
shunt resistor to a certain threshold voltage Vth, and by connecting the open-drain output of
the comparator with both the two BRAKE inputs of the two L6393s. The analog input signal
Vth is limited by the resistive divider and the small signal diode to a fixed minimum level.
With this kind of current mode control, the reference signal Vth regulates directly the torque
applied to the fan motor and then indirectly the speed. The type of current control obtained
with this architecture is a peak current control with constant OFF time, dimensioned by the
RC network on the open-drain output of the sense comparator. Note that the active pulldown of the BRAKE signal operated by the PWM comparator decreases the load current
during the OFF time in “slow decay” mode, because the load is shorted by the bridge. If “fast
decay” is desired, the PWM signal can be applied to the SD pins of the two drivers.
Figure 11 shows the waveform of the load current (flowing in the shunt resistor) and the Vth
torque reference signal.
Figure 11. Current modulation (flowing in the shunt resistor) changing the Vth
signal
The rotation detection circuit works as a high-pass filter and can detect if the fan rotor is
moving or not. In the event of a stall, the RD output goes to ground and provides information
on the fan’s stall condition.
Note that several different combinations of the circuitry available in the L6393 can be used.
For example, if the inverted hall signal is already available (or is implemented using a small
BJT or any other circuitry), the first comparator belonging to one of the two L6393s can be
used for any other purpose.
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Application examples
6.2.2
AN2785
Voltage mode - example 1
A different approach could be used to drive a single-phase BLDC fan: the voltage mode
control. In the following example, an application circuit using the voltage mode approach is
provided. This solution does not control the load current as in the previous circuit, but
directly controls the duty cycle of the voltage applied to the load connected to the full-bridge.
Additionally, the motor current is limited for protection purposes. As in the previous example,
the diagonal of the full-bridge is selected by feeding the single-phase Hall Effect sensor
signal directly to the PHASE input of one L6393 and the inverted signal to the PHASE input
of the other L6393. Unlike the circuit shown in Figure 10, in this particular example the
PHASE inversion is provided by a simple bipolar transistor since the two L6393 available
comparators are already used for other purposes. Note that the PHASE inversion, as other
analog/digital functions, can be obtained using various combinations of the features of the
L6393 drivers or, where needed, some external components. The PWM voltage control is
implemented using one L6393 comparator which compares the voltage coming from a
triangle generator with an external voltage reference. As in the previous circuit, the external
reference threshold is also limited to a minimum value by the network composed by a
resistive divider plus a small signal diode (see Figure 12). The result of the PWM
comparator is fed into the BRAKE inputs of the two L6393s. As mentioned previously, the
pull-down of the two BRAKE inputs provides a “slow decay” mode for the current control,
shorting the motor load through the two low sides. If “fast decay” is required, the PWM signal
can be applied to the SD pins of the two drivers. The remaining comparator can be used to
implement a simple over-current protection obtained by reading the shunt resistor voltage
between the low sides and ground. The open-drain output of the comparator can be
connected directly to the two SD pins of the L6393s so as to set to high impedance the fullbridge stage after over-current detection. The RC network on this open drain output sets a
disable time after the fault detection. If over-current protection is not needed, one of the
integrated comparators can be used for other purposes (such as triangle waveform
generation, for example).
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Figure 12. L6393 application circuit for voltage mode FAN controller (logic output
hall sensor)
Rotation Detection
FG
Signal Inverter
Logic Output
HALL Sensor
RD
+5V
+5V
BIPOLAR
TRANSISTOR
PHASE
PHASE
PHASE
H
Full Bridge Power Stage
+12V
Triangle Generator
Vbus
PWM Comparator
Logic + Drivers
Logic + Drivers
+5V
HVG
HVG
Motor Load
PHASE
COMPARATOR
BRAKE
SD
PHASE
SD
SD
+
BRAKE
_
+5V
+12V
SD
LVG
LVG
Speed Input
with minimum
threshold limiter
SD
Over Current
Protection
COMPARATOR
SD
+
_
Vlim
Vth
EQUIVALENT CIRCUIT USING L6393 DRIIVERS
+5V
Logic Output
HALL Sensor
Rotation Detection
+5V
H
+12V
CP+
HVG
CP-
OUT
VCC
+12V
+5V
+12 ÷ 600V
VBOOT
PHASE
FG
RD
L6393
SD
LVG
BRAKE
DT
CPOUT
GND
PHASE
VBOOT
Dead Time
Setting
Triangle Generator
CP+
Vlim
VCC
+12V
+12V
Simplified Minimum
Speed Generation
HVG
CP-
+5V
Over Current
Disable Time
OUT
L6393
SD
LVG
BRAKE
DT
CPOUT
GND
Dead Time
Setting
Vth
The same circuit for rotation detection as the one shown in Figure 11 can be used in this
case.
6.2.3
Voltage mode - example 2
Figure 13 provides another application of the L6393. As in the previous example, the control
type is voltage mode, but the main difference is that the Hall Sensor has an analog
differential linear output and it must be converted into a digital signal to be fed into the gate
drivers’ input logic. The conversion is provided by one comparator belonging to one of the
two L6393s in the application. The other L6393 comparator is used to implement an overcurrent protection, similarly to the circuit shown in Figure 12. The remaining circuitry is
similar to the previous example. In this particular case, for higher accuracy, the circuitry
providing the minimum speed value is implemented using an op-amp in an ideal rectifier
configuration.
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Figure 13. L6393 application circuit for voltage mode FAN controller (linear hall
sensor)
Signal Inverter
Sensor Comparator
+5V
+5V
Linear HALL Sensor
BIPOLAR
TRANSISTOR
+5V
COMPARATOR
L6393
H
+
_
Full Bridge Power Stage
+12V
Vbus
Triangle Generator
Logic + Drivers
PWM Comparator
Logic + Drivers
+5V
HVG
HVG
Motor Load
PHASE
COMPARATOR
BRAKE
SD
PHASE
SD
SD
+
_
+5V
Minimum Speed Generation
RMI
Over Current
Protection
COMPARATOR
L6393
SD
SD
+
_
Vlim
Vth
EQUIVALENT CIRCUIT USING L6393 DRIIVERS
+5V
Linear HALL Sensor
+5V
H
CP+
HVG
CP-
OUT
VCC
Rotation Detection
+12V
+5V
RD
L6393
SD
FG
LVG
BRAKE
DT
CPOUT
GND
PHASE
VBOOT
CP+
+12V
Triangle Generator
Vlim
Over Current
Disable Time
VCC
+12V
+5V
Dead Time
Setting
HVG
CP-
+5V
+12 ÷ 600V
VBOOT
PHASE
Minimum Speed Generation
OUT
L6393
SD
LVG
BRAKE
DT
CPOUT
GND
Dead Time
Setting
PWM Comparator
OPAMP
RMI
Vth
Figure 14 shows some waveforms related to the presented circuit.
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SD
BRAKE
LVG
LVG
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Application examples
Figure 14. Waveform related to the VM application circuit with linear hall sensor
Output
current
RD signal
PWM generation
with minimum
speed
Sinewave
HALL signals
Current
protection
6.3
Full-bridge topology: brush DC motor driver
This section provides a further sample circuit using L6393 ICs to drive a typical brush DC
motor. Again, the power stage topology used is full-bridge. Considering that the voltage
mode control circuit is a simplification of the one implementing current mode control, only
this last example is shown in the application circuit depicted in Figure 15.
The direction of the brush DC motor is selected by the DIRECTION signal, which is directly
connected to the PHASE input of one driver and, once inverted, to the PHASE input of the
other L6393 driver. The inversion of the PHASE signal is implemented using one L6393
comparator. The torque applied to the DC motor is controlled by the Vth signal which works
as reference signal for a peak current control implemented using the other available L6393
comparator. The type of control is a peak current control with constant OFF time. It is
possible to control the torque and thus indirectly also the speed of the motor, assuming that
the load torque and the bus voltage remain constant.
The suggested circuit makes it possible to implement a simple brush DC motor driver using
just two L6393s, a few simple passive components and a power full-bridge.
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Figure 15. L6393 application circuit for brush DC motor controller (current mode)
Signal Inverter
+5V
+5V
COMPARATOR
PHASE
DIRECTION
PHASE
+
_
Full Bridge Power Stage
Vbus
Logic + Drivers
Logic + Drivers
HVG
HVG
Motor Load
PHASE
SD
BRAKE
PHASE
SD
SD
BRAKE
LVG
LVG
Torque Input
with minimum
threshold limiter
+5V
COMPARATOR
BRAKE
SD
+12V
+
_
Vth
PWM Current Control
OFF Time
EQUIVALENT CIRCUIT USING L6393 DRIIVERS
+5V
CP+
HVG
CP-
+5V
VCC
+12V
Vth
+12V
Torque Input
with minimum
threshold limiter
OUT
L6393
SD
LVG
BRAKE
DT
CPOUT
GND
PHASE
VBOOT
CP+
Over Current
Disable Time
VCC
+12V
OUT
L6393
SD
LVG
BRAKE
DT
CPOUT
GND
SD
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Dead Time
Setting
HVG
CP+5V
+12 ÷ 600V
VBOOT
PHASE
DIRECTION
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Setting
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6.4
Application examples
Gate driving: principle of working with inductive loads
This section provides a more detailed description of the power IGBT (or MOSFET) gate
driving with inductive loads. The following explanations and calculations are only intended to
provide a general understanding of the physical principles behind the phenomenon of the
dVOUT/dt control through the gate current limitation performed by the gate resistors. The
purpose is to help the application designer using L6393 ICs to understand the various ways
in which different parameters of the gate driver system act on the power transitions, and
thus identify the main effects on which to focus.
Calculations and formulae should be considered as qualitative indications and not for an
accurate quantitative use since, as explained in the above paragraph, they are the result of a
first approximation study. The experimental verification of the design choices is always
recommended.
The description distinguishes and explores the two main actors of the gate driver system: on
the one hand the inner structure of the gate driver output buffers is described, and on the
other hand the switching mechanism of a generic IGBT (or MOSFET) is detailed.
Figure 16 provides a simplified view of the L6393 gate driver output buffers. Each one can
be considered as a CMOS push-pull stage where a p-channel MOSFET works as source
driver while an N-channel MOSFET works as sink driver. The structure is similar for both the
low side and the high side, and the behavior can be considered the same. In fact, the highside driver can be thought of as a floating buffer having as supply the VBOOT voltage and as
reference the OUT pin. The CBOOT capacitor represents the floating supply voltage source
of the high-side driver. During the charge of the power switch gate, each source/sink
MOSFET can be considered (in first approximation, for simplicity) as if it would be in the
ohmic region, so it can be represented as an equivalent resistor with a value equal to its
RDSon. Thanks to this approximation, one can use a simplified equivalent circuit for the turn
ON and the turn OFF commutation (see Figure 16). Regarding the turn ON, this gate charge
circuit has two resistors in series (RGATE_ON and RDSon_SOURCE) and a supply voltage
which is VCC for the low side and Vboot-Vout for the high side. Regarding the turn OFF, the
equivalent circuit is composed of just two resistors (RGATE_OFF and RDSon_SINK) connected
to the source of the power switch.
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Figure 16. Gate driver output buffers: equivalent circuit
GATE DRIVER OUTPUT: EQUIVALENT CIRCUIT FOR TURN-ON
HVG or LVG
OUTPUT DRIVER
BOOT or VCC
OUT or HVbus
RDSon_source
RGATE
Vge
RGATE
RDSon_source
Vge
+
HVG/LVG
(Vboot-Vout) or VCC
OUT or GND
GATE DRIVER OUTPUT: EQUIVALENT CIRCUIT FOR TURN-OFF
HVG or LVG
OUTPUT DRIVER
BOOT or VCC
OUT or HVbus
Vge
RGATE
RDSon_sink
HVG or LVG
RDSon_sink
Vge
RGATE
OUT or GND
This first simplification is related to the inner structure of the gate driver circuitry. The
following section focuses on the side of the power bridge and its commutations.
In a common half-bridge composed of a high-side and low-side switch, the transitions of the
power IGBTs (or MOSFETs) are not all similar, but they can be distinguished into two main
types: soft switching and hard switching (Figure 17). The key element in the dynamics of the
transitions is the direction of the current flowing in the power IGBT (or MOSFET) under
evaluation, which depends on the direction of the load current with respect to the half bridge.
Essentially, if the current goes in the same direction as the power switch, the commutation is
hard. If the current goes in the opposite direction, the commutation is soft.
Figure 17. Hard and soft switching
HARD SWITCHING
CURRENT GOING IN THE BRIDGE
+
LOW SIDE SWITCHING
OFF
OFF
ON
OFF
ON
ON
OFF
Iload
SOFT SWITCHING
CURRENT GOING OUT FROM THE BRIDGE
+
HIGH SIDE SWITCHING
CURRENT GOING OUT FROM THE BRIDGE
+
LOW SIDE SWITCHING
ON
OFF
OFF
OFF
OFF
CURRENT GOING IN THE BRIDGE
+
HIGH SIDE SWITCHING
ON
OFF
ON
ON
OFF
Iload
Iload
ON
OFF
OFF
Iload
when the power switches ON
the diode is already turned ON
As shown in Figure 17, hard switching occurs when the high side is commutating and the
load current is outgoing from the bridge or when the low side is commutating and the load
current is ingoing to the bridge. This type of transition is called hard because the power
switch turns ON when the related Vce (Vds) is at the maximum; Vce (Vds) goes back to the
maximum during turn OFF (Vce is close to zero while the switch is steadily ON): the
transition is completely managed by the switch that, during the commutation, dissipates
energy.
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On the other hand, if the switch turns ON when its Vce is already close to zero or Vce keeps
staying close to zero after turn OFF, the transition is soft and, during the commutation, the
switch dissipates almost no energy. This last condition occurs when the free-wheeling diode
of the switch is bringing the current because the diode is in the same direction as the load
current.
As a general rule, one should consider that the dynamics of the transition (dVOUT/dt, Vce
rise/fall time etc.) is always managed and controlled by the power switch in hard switching,
while its companion switch is necessarily in soft switching (because it is in the opposite
direction with respect to the load current). Considering this and in order to understand the
mechanism of the power IGBT (MOSFET) transition, the hard switching transition is further
described below. Note that all of the following descriptions always consider an inductive load
connected to the half-bridge stage output.
Figure 18 depicts the dynamics of the hard switching for the turn ON transition.
The first graph is related to the gate charge curves of the power IGBT (or MOSFET). This is
a typical graph available in the datasheet of every IGBT or MOSFET, and describes the
dependence of the amount of charge required by the IGBT gate on the voltage drop
between the gate and the emitter (or source). The second graph shows the collector current
(Ic) and Vce voltage versus time. The third graph shows the working point of the IGBT
traced on the various Ic vs. Vce characteristic curves for different Vge voltages. For a single
turn ON transition, four main phases related to the power IGBT (MOSFET) commutation can
be distinguished. On the left side of Figure 18, the IGBT conditions for each phase are
described. During phase T1, the gate begins to be charged, but the power IGBT is still not
conducting because Vge is below the IGBT threshold. In this state the IGBT current is zero
and its Vce is at the maximum, while Vge is gradually increasing. In phase T2, the Vge
voltage goes above the IGBT threshold and the IGBT starts to bring part of the load current,
while Vce remains fixed at the maximum level because the free-wheeling diode of the
companion IGBT is still bringing the rest of the load current, and therefore is still in
conduction, clamping in this way the Vce voltage. Both in T1 and T2 phases, the gate
current contributes to charge the equivalent Cge parasitic capacitance of the IGBT. In the Ic
vs. Vce characteristic plot, the T2 phase is the vertical section of the working curve trace,
because the IGBT is moving on its own characteristic with a constant Vce and an increasing
current, while its Vge is increasing too. When the amount of current flowing in the IGBT is
equal to the load current, the diode turns OFF and the Vce voltage starts to decrease
because it is no longer clamped by the free-wheeling diode of the other IGBT. The working
point on the Ic vs Vce curve reaches the lload value and starts to move horizontally on the Ic
constant curve in the direction of the decreasing Vce voltages. This is the T3 phase, usually
called plateau phase. This name comes from the fact that the gate charge curve is
horizontal for the whole T3 phase, until Vce reaches the Vce_sat value corresponding to the
Iload current. Note that the Vge voltage is constant although the gate current flowing in the
IGBT gate is not zero: the reason is that the whole gate current is used to charge the Cgc
(Miller) parasitic capacitance which then experiences a dV/dt on its terminals because the
Vce voltage is decreasing after the diode turn OFF. In a first approximation, if the Cgc was
constant (it is actually not), the dVOUT/dt could be calculated as follows:
I
⎛ dVOUT ⎞
= SOURCE
⎜
⎟
CGC
⎝ dt ⎠FALL
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The above formula shows that the source current coming from the gate driver can directly
control the dVOUT/dt of the power half-bridge. This calculation is just a first approximation
since, typically, the Cgc miller capacitance value is not constant but depends on the Vce
voltage: Cgc is not linear. The main effect of the Cgc’s abrupt variation is that the actual
slope of the out transition is composed of two different dVOUT/dt slopes, one faster and the
other slower (with respect to the value obtained by the above formula). See Figure 18. In
this document, only the first approximation approach will be used.
Figure 18. Turn-ON hard switching details with induction load: gate charge and
plateau phase
TURN-ON (hard switching)
GATE CHARGE CURVES
T1
Vge
OFF
Qg
diode ON
Vge_max
Vge
Qge
Qgc
Isource
plateau
Cge
Vce
=
HVbus
Ic = 0
Vgs_p
Ton
Vth
T2
OFF
t, Q
diode ON
Vce, Ic
Vge
HVbus
Isource
Ic
APPROX.
Vce
=
HVbus
Cge
Iload
REAL
T3
OFF
T2
Cgc
T3
Ton
Cgc = Isource
diode OFF
t
T1
dVce
dt
T4
Isource
Tfall
Vge = Vge_p
Cge
Ic vs Vce CHARACTERISTICS
Ic
Vge = Vge_max
Vce
Ic
=
Iload
PLATEAU
PHASE
Tfall
T4
Iload
T4
Vge = Vge_p
T3
OFF
diode OFF
plateau
T2
Vge
Vge
Isource
Cge
Vce_sat
HVbus
Vce
WORKING
CURVE
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=
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Vce = Vce_sat
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Application examples
Due to the Cgc’s non-linearity the IGBT (or MOSFET) datasheet also reports the equivalent
total amount of charge required during the different gate charge phases: the total gate
charge Qg required for turning ON the IGBT (or MOSFET) completely, the Qge required for
increasing the Vge up to the plateau voltage and the Qgc required during the whole plateau
phase. This last amount of charge is also called plateau charge. The time required to
provide the complete plateau charge is the Tfall time and this is the same time necessary for
completing the Vce transition. For Ton time is intended the time delay between the
beginning of the gate charge and the full conduction of the IGBT (or MOSFET), when the
power switch current equals the full load current. So:
TFALL =
Q GC
ISOURCE
It is now possible to merge the equivalent gate driver output circuit reported in Figure 16 and
the considerations about the different gate charge phases in the total equivalent circuit
reported in Figure 19.
Figure 19. Total equivalent circuit for turn-ON
Ton
RDSon_source
Vboot/VCC
+
Tfall
RGATE
Isource
RDSon_source
Vge
Vboot/VCC
+
RGATE
Isource
+
Vge_p
Cge =
Qge
Vge_p
= Ciss_min
From the above circuit the value of the transition times could be calculated (the following
formulae are related to the low-side transition, but the same are also suitable for the highside by changing “VCC” with “VBOOT-VOUT”).
⎛
⎞
VCC
⎟⎟
TON = (RDSon _ source + R GATE ) ⋅ CISS _ min ⋅ ln⎜⎜
⎝ VCC − Vge _ p ⎠
TFALL =
Q GC
ISOURCE
= Q GC ⋅
(RDSon _ source + RGATE )
VCC − Vge _ p
CISS_min is used because when the Vce (or Vds) of the power IGBT (or MOSFET) is
maximum (equal to HVbus), the CISS (which depends on the Vce) shows its minimum
value.
During the turn-OFF of the power IGBT (or MOSFET), the behavior is the same as for the
turn-ON but in reverse time order. Figure 20 provides the gate charge characteristics and
Vce vs. Ic curves.
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Figure 20. Turn-OFF hard switching details with induction load: gate charge and
plateau phase
TURN-OFF (hard switching)
T1
GATE CHARGE CURVES
Vge
OFF
diode OFF
Qg
Vge_max
Vge
Qge
Qgc
Isink
Cge
plateau
Vgs_p
Ic
=
Iload
Vce = Vce_sat
Toff
Vth
T2
dVce
dt
OFF
t, Q
Vce, Ic
Cgc = Isink
diode OFF
Cgc
HVbus
Isink
APPROX.
Vge = Vge_p
Cge
Final tail
only for
IGBTs
Iload
Vce
Ic
=
Iload
PLATEAU
PHASE
REAL
Trise
T3
OFF
diode ON
t
Vge
T1
T2
Toff
Trise
T3
T4
Isink
Iload
Vce
=
HVbus
Cge
Ic vs Vce CHARACTERISTICS
Ic
Ic
Vge = Vge_max
T1
T4
Vge = Vge_p
T2
OFF
plateau
diode ON
T3
Vge
Vge
Isink
Cge
HVbus
Vce_sat
Vce
Ic = 0
Vce
=
HVbus
WORKING
CURVE
The rising dVOUT/dt and Trise can be calculated as follows.
I
⎛ dVOUT ⎞
= SINK
⎜
⎟
⎝ dt ⎠RISE CGC
TRISE =
Q GC
ISINK
As discussed above the equivalent gate driver output circuit can be represented as in
Figure 21.
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Application examples
Figure 21. Total equivalent circuit for turn-OFF
Trise
RDSon_sink
Toff
RGATE
Isink
RDSon_sink
+
RGATE
Isink
Vge
Vge_p
Cge = Ciss_max
Given the equivalent circuits in Figure 21 and the approximations on the power IGBT’s
(MOSFET) switching behavior, the timings are the following.
⎛ VCC ⎞
⎟⎟
TOFF = (RDSon _ sin k + RGATE ) ⋅ CISS _ max ⋅ ln⎜⎜
⎝ Vge _ p ⎠
TRISE =
(R
+ R GATE )
Q GC
= Q GC ⋅ DSon _ sin k
ISINK
Vge _ p
As above, CISS_max is used because when the Vce (or Vds) of the power IGBT (or
MOSFET) is minimum (equal to Vce_sat), the CISS (which depends on the Vce) shows its
maximum value.
Even if they are just approximations, Tfall and Trise are very important values to be
estimated because they provide an indication about the power dissipation during the
switching of the power IGBT (or MOSFET), which can be approximated as indicated in
Figure 22.
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Application examples
AN2785
Figure 22. Power dissipation during switching (approximation)
POWER DISSIPATION FOR SWITCHING
turn ON
turn OFF
Vce, Ic
Vce, Ic
HVbus
HVbus
approx.
approx.
Iload
Iload
real
real
t
t
T1
T2
T3
Ton
T4
T1
T2
Toff
Trise
T3
T4
T3
T4
Tfall
Iload
HVbus
Pdiss_sw
Pdiss_sw
HVbus
Iload
conservative
approximation
conservative
approximation
real
real
t
t
T1
T2
T3
Ton
T4
T1
T2
Toff
Trise
Tfall
T2 is typically very short
compared to T3
T3 is typically very short
compared to T2
Since the T2 time for the turn ON and T3 time for the turn OFF are much shorter compared
to respectively Tfall and Trise, the approximated instantaneous amount of energy dissipated
during the commutation can be calculated as the triangular area having as base the Tfall or
Trise time, and as height the product between the maximum Vce voltage (equal to HVbus)
and the Iload current value, as follows:
EDISS _ SW ≅
PDISS _ SW ≅
(HVBUS ⋅ ILOAD ) ⋅ (TFALL + TRISE )
2
(HVBUS ⋅ ILOAD ) ⋅ (TFALL + TRISE ) ⋅ fSW
2
The term fSW represents the switching frequency of the power IGBT (or MOSFET).
In summary, using the results obtained by these approximated calculations, it is clear that
the main consideration when dimensioning the gate resistor values is the trade-off between
the electromagnetic emissions and the power dissipated during power IGBT (or MOSFET)
switching, as shown in Figure 23.
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Application examples
Figure 23. Rgate dimensioning criteria
Pdiss_sw
Electromagnetic
emissions
Maximum allowed EMI
Rgate dimensioning trade off
Rgate
Rgate has an influence on the power dissipation on the one side and on the EMI effects on
the other side, therefore the best trade-off must be chosen during the application’s design-in
phase.
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Induced turn-on phenomenon
7
AN2785
Induced turn-on phenomenon
One possible phenomenon to be analyzed is the induced turn ON that could happen on a
turned OFF power IGBT (or MOSFET) when its companion on the same half-bridge is
switching on. This phenomenon is due to the current injected on the gate by the Miller
parasitic capacitance (Cgc), which causes an undesired voltage increase on the gate of the
power IGBT (or MOSFET) which should be kept well turned OFF. Induced gate voltage
depends on the absolute value of the parasitic capacitance Cgc, its relative ratio with Cge,
the value of the dVOUT/dt of the half-bridge and the value of the equivalent (turn OFF)
resistance between the emitter (or the source) and the gate. Figure 24 shows this
phenomenon.
Figure 24. Induced turn ON phenomenon - circuital description
low side hard switching
high side hard switching
Vs
Vs
injected
current
HVG
HVG
OUT
induced
voltage
dVout/dt
dVout/dt
OUT
injected
current
LVG
LVG
induced
voltage
PGND
PGND
Note that typically the induced turn ON phenomenon does not cause a complete turn ON of
the power MOSFET, so it is hard to have a destructive cross-conduction on the half bridge
during commutations. Nevertheless, a weak conduction of the opened power switch might
increase the power dissipation of the power stage, increasing then the overall temperature
of the power MOSFETs and reducing the efficiency. This is the reason why this
phenomenon deserves particular attention also in terms of thermal performances of the
power application.
This phenomenon could be reduced in the following ways.
a) By reducing the resistance path between the gate and emitter (source). Reducing
as much as possible the gate resistance in which the injected current flows results
in a lower voltage drop on the gate. The drawback could be an increase of the
dVOUT/dt during the turn OFF of the power IGBT (or MOSFET) which commutates
in hard-switching and then an increase of the electrical noise and EMI issues (as
explained in the previous paragraph the power IGBT or MOSFET in hard-switching
is always the one which has the channel in the same direction as the current). On
the other hand, the dVout/dt during turn OFF is usually lower than the one during
turn ON because the plateau voltage is closer to the source voltage than the
supply voltage of the driver, resulting in a lower gate current for the discharge of
the gate charge.
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Induced turn-on phenomenon
b)
c)
By reducing the maximum dVOUT/dt. This reduction can be achieved by increasing
the gate resistor value that limits the gate current for the turn ON of the power
MOSFET. The drawback is a consequent increase of the switching time, which
means dissipating more power during commutations.
By using a MOSFET/IGBT with a lower Cgd/Cgs (or Cgc/Cge for IGBTs) ratio.
This solution is not always the easiest, but it could be the best strategy when the
induced turn ON phenomenon is dominant.
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How to increase the gate driver output current capability
8
AN2785
How to increase the gate driver output current
capability
In some cases, certain applications may require more gate driver output current capability.
This requirement can be found in systems where the power rating is higher than
approximately 1 kW. In such applications in fact, typically the power MOSFET/IGBTs have a
big gate charge which contributes to slow down the power switch transition (the dVOUT/dt),
increasing the power dissipation during each commutation. Note that also in applications
with power ratings higher than 1 kW, the output current capability of the L6393 may be
enough if the power dissipation for commutation is acceptable (the power dissipation due to
RDSON or VCESAT is not dependent on the gate current). However, if the limitation of such
power contribution is a constraint, the dVOUT/dt of each transition must be increased by
enhancing the current capability of the gate driver.
A simple way to increase the current capability of the gate driver outputs is to insert, in
series with the two gate lines of one half-bridge gate driver IC, two external current buffers
(Figure 25).
Figure 25. Block diagram of output current capability enhancement using external
current buffers
CURRENT
BUFFERS
H.V.
VBOOT
HVG
GATE
DRIVER
OUT
TO LOAD
VCC
LVG
GND
Typically, the current buffers are implemented using bipolar NPN-PNP push-pull noninverting (emitter follower configuration) structures. Figure 26 shows a typical circuit using a
gate driver with bipolar push-pull current buffers.
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How to increase the gate driver output current capability
Figure 26. Example of a gate driving circuit with current buffers to increase current
capability
Very close to push-pull stage
H.V.
VBOOT
GATE
DRIVER
100 nF
25V
HVG
+
15V
-
VCC
+
10 uF
25V
100 nF
25V
STS01DTP06
100 nF
25V
+
100 uF
400V
0-10 Ω
0.25W
0-10 Ω
0.25W
GND
OUT
VCC
TO LOAD
STS01DTP06
100 nF
25V
LVG
0-10 Ω
0.25W
0-10 Ω
0.25W
Very close to push-pull stage
In the example above, the ST devices STS01DTP06 are dual NPN-PNP complementary
bipolar transistors rated for 1 A current and available in the small SO-8 package. The two
push-pull structures are placed on each gate driving path and must be provided with a
decoupling capacitor very close to the device pins (as shown in Figure 26).
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Below-ground voltage on the OUT pin
9
AN2785
Below-ground voltage on the OUT pin
A typical phenomenon found in a great number of power applications is the below ground
voltage experienced by the OUT pin that can sometimes be very high. Contrary to popular
belief, the real problem in the below-ground voltage is not in the maximum absolute value of
the OUT pin, rather the voltage on BOOT pin and the over-charging of the bootstrap
capacitance. This paragraph explains in detail the root causes of the below-ground voltages
and describes actual issues that could result from the phenomenon.
9.1
Below-ground voltage phenomenon
In power applications that use half-bridge topologies and typically driving loads with a
significant inductive component, the output of the power half-bridge systematically
experiences a below-ground voltage transition, which can be seen in a dynamic contribution
as a greater undershoot spike and in a static contribution as a below-ground static voltage
with lower absolute value (Figure 27 b). This phenomenon happens when the bridge carries
out a so-called hard-switching transition towards the low voltage level and the load current is
outgoing (from the bridge to the load): when the high-side switch turns off, the output current
tends to remain quite constant due to the inductive component of the load, and then has to
flow through the low-side freewheeling diode, which turns on going from a high-voltage
reverse condition to a forward condition. It is evident that until the output bridge voltage has
not reached the “zero” value, the diode is turned off, so the output transition is dominated by
the high-side turn-off commutation. After the output voltage reaches a zero voltage level, the
diode can turn on and it begins to bring the whole load current in a very brief time, so the
high dIF/dt causes the well-known forward peak voltage, which is the main contribution to
the undershoot spikes. Other contributions to dynamic below-ground voltage are the spikes
due to the high dI/dt experienced by the parasitic inductances in series with the freewheeling diode located along the turn-off current path of the half bridge (Figure 27).
Figure 27. Below-ground voltages in L6393
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Below-ground voltage on the OUT pin
The overall below-ground voltage on the OUT pin can be calculated as follows.
Equation 5
V OUTmin ≥ static = – ( R SENSE ⋅ I LOAD + V F )
Equation 6
dIF
VBGV _ spike = VFPK + LPARASITIC ⋅
+ VOUT min_ static
144244
3
dt
1444
424444
3 static
contribution
dynamic
contribution
Where:
●
VFPK is the free-wheeling diode transient peak forward voltage; it depends mainly on
the device technology and on the dIF / dt of the current in the diode. Typical values may
range from some volts to more than 10 V. Figure 28 shows the VFP vs. dIF/dt of the
STTH1L06 diode.
●
dIF / dt is the current slope in the low side IGBT/MOSFET and may have a value from
some tens to some hundreds of A/µs. Its value depends mainly on the power switch
characteristics and in part on the driving current.
●
LPARASITIC represents the sum of all parasitic inductances on the current path and
mainly depends on the PCB layout. In general, during the design of the power
application it is important to pay attention to the layout of the power bridges in order to
limit this parameter. Typical values of a good layout are in the order of some tens of nH.
Note that it is also useful to use RSENSE resistors with low parasitic inductance for the
same reason.
●
RSENSE * ILOAD product is the value of the VSENSE voltage and is typically less than 1 V,
also for thermal dissipation issues on the same resistor.
●
VF is the forward voltage of the free-wheeling diode and is usually less than 2 V.
Figure 28. Transient peak forward voltage vs. dIF/dt of STTH1L06 diode
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Below-ground voltage on the OUT pin
9.2
AN2785
How to reduce the below ground spike voltage
In order to reduce the below ground spike, the following action should be taken:
●
Reduce the parasitic inductances (see Figure 27).
●
Reduce the dIF/dt by slowing down the turn-off of the high side IGBT/MOSFET.
In most of application the two previous strategies result to be enough to reduce properly the
below ground spike voltage, increasing the robustness of power system and then the margin
for safe operation of the application. On the other hand in some cases, where the below
ground spike voltage is significantly higher, the above suggestions may be not sufficient to
limit that value and then it could be useful to add some external components to improve
further the noise robustness of the power stage section:
●
Add a small resistor (2÷10 Ω typically) in series to the OUT line (see Figure 29). The
series resistor has the positive effect of limiting the spike voltage on the BOOT pin,
thanks to the filtering effect of such resistor coupled with the bootstrap capacitor. Note
that, in order to obtain an effective filtering effect, the OUT resistor must be placed
between the minus terminal of bootstrap capacitor and the output of the power stage,
as indicated in Figure 29.
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Below-ground voltage on the OUT pin
Figure 29. Use of OUT resistor to limit the below ground voltage spike on OUT pin
V
BOOT
OUT
HB_OUT
0
VBOOT without Rout
VCC
DBOOT
RBOOT
t
BOOT
H.V.
CBOOT
HVG
RGH_ON
DH
HS
RGH_OFF
HB_OUT
OUT
ROUT
RGL_ON
LS
LVG
DL
RGL_OFF
Note that this resistor is in series with both the turn ON and the turn OFF path, so it must be
considered in the sizing of overall turn-ON and turn-OFF resistance.
In case neither the OUT resistor would not be enough to limit the below ground voltage, the
following final resolving action could be taken:
●
Add a high voltage fast diode (e.g. STTH1L06) between the GND pin and the OUT pin
(very close to the device pins) in order to clamp directly on the gate driver OUT pin the
below ground voltage spike. Note that, in any case, this diode must be used together
with the OUT resistance suggested in the previous tip, because it must be avoided that
the diode brings the very large load current during low side recirculation, in order to
increase the clamping action of the diode itself (see following Figure 30).
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Below-ground voltage on the OUT pin
AN2785
Figure 30. Use of combination of OUT resistor and OUT diode to limit the below
ground voltage spike on OUT pin
V
BOOT
OUT
HB_OUT
0
t
VCC
DBOOT
RBOOT
BOOT
H.V.
CBOOT
RGH_ON
HS
HVG
DH
RGH_OFF
HB_OUT
OUT
ROUT
RGL_ON
LS
LVG
DL
GND
RGL_OFF
DOUT
Note that ROUT resistor is also in series with the charging path of the bootstrap capacitor. Its
effects may be more evident during the first charge of the bootstrap capacitor, when it is
completely discharged and a significant charging current may flow into the ROUT resistor,
producing an additional voltage drop between ground and OUT pin. Because during the
bootstrap charging the HVG pin is set to low level, the OUT pin and the HVG pin are shorted
together and have the same voltage, so the voltage drop due to ROUT results directly
transferred to the VGE (or VGS) of the high side IGBT (or MOSFET). Then the risk is that a
weak turn ON of the high side power switch, when the low side power switch is already ON,
could cause a cross-conduction in the power half bridge. Actually in most of cases this
doesn’t represent an issue for the proper working of the application, because the typical
intrinsic resistance RBOOT (~120 Ω) in series to the internal bootstrap diode is much higher
than the ROUT commonly used and the voltage drop on ROUT is negligible.
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9.3
Below-ground voltage on the OUT pin
Issues related to the below-ground voltage phenomenon
The issues resulting from significant below-ground voltages on the OUT pin are not related
to the maximum absolute voltage values that the OUT pin is able to withstand, but related
mainly to the voltage value of the BOOT pin, which is indirectly bound with the OUT pin
voltage. There are two main issues to be carefully taken in consideration, both related to the
absolute maximum ratings of the IC.
●
VBOOT absolute minimum voltage.
●
VBOOT-VOUT absolute maximum voltage.
9.3.1
VBOOT voltage safe operating condition
Electrically, the OUT pin could stand safely below ground of many volts without problems,
but the BOOT pin cannot. The absolute value of the VBOOT voltage must not go steadily
below -0.3 V in order to avoid the turn-on of the built-in junction between the BOOT pin and
the IC gate driver substrate (connected to GND), normally in reverse condition. The turn-on
of this junction could in fact cause a very high current that could in turn cause damage to the
device.
9.3.2
Bootstrap capacitor overcharging
Another important point to consider is the overcharging of the bootstrap capacitor. Even
before the OUT pin approaches the zero voltage value, the bootstrap diode (internal or
external) tends to tie VBOOT close to the VCC supply voltage; since the OUT pin is below
ground, the bootstrap capacitor is overcharged through the current coming from the
bootstrap diode and then the VBOOT - VOUT voltage increases. It is very important that the
bootstrap overcharging does not overcome the recommended maximum value for the
VBOOT - VOUT voltage (see the relevant datasheet), because the high-side floating section of
the gate driver could be damaged.
Note that a significant overcharging of the bootstrap capacitor is really only possible through
the static contribution of the below-ground voltage, because the dynamic below-ground
voltage is very brief and the overcharging transition is limited by the time constant RC of the
bootstrap capacitor and by the overall resistance in series with the bootstrap diode.
Figure 31 shows the overcharging phenomenon in detail.
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Below-ground voltage on the OUT pin
AN2785
Figure 31. Bootstrap overcharging due to below-ground voltage on OUT pin
VBOOT - VOUT
VBOOT
BOOTSTRAP NETWORK
&
BELOW GROUND VOLTAGE
VCC
DBOOT
RBOOT
BOOT
Time constant of this transition:
RBOOT * CBOOT >> Tspike typically
VCC
VOUT
VBOOT - VOUT
VBOOT - VOUT
overcharged
during static BGV
befor overcharge
OUT
0V
VBGV_static
t
VBGV_spike
VBOOT - VOUT
during BGV spike
VOUT
Tspike < 100ns
typically
Note that in the L6393 IC gate driver the internal DMOS in series with the integrated
bootstrap diode is only fully turned on when the LVG is ON. In fact, when the LVG is OFF, the
gate of the bootstrap DMOS is biased at VCC voltage. This means that if the VBOOT is pulled
down by the bootstrap capacitor (due to a below-ground voltage on the OUT pin) at about 3
V (typical value) below the VCC voltage, the DMOS turns on again. Figure 32 shows some
different (internal and external) bootstrap network characteristics.
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Below-ground voltage on the OUT pin
Figure 32. Different bootstrap network characteristics
Regarding the below-ground voltage spike, typically this undershoot voltage has a very brief
duration (less than 100 ns), therefore it is not enough to further overcharge the bootstrap
capacitor since the time constant of the bootstrap charging is equal to the product of the
CBOOT and the RBOOT resistance in series with the diode. Moreover, the higher this
resistance, the lower the risk of bootstrap overcharging during BVG spikes.
For example, with an RBOOT of 120 Ω and a CBOOT equal to 100 nF, the associated time
constant would be about 12 µs, much higher than the typical below-ground voltage spike
duration: with the internal bootstrap diode it is very difficult to overcharge the floating section
up to dangerous voltages in the very short duration of the undershoot spike. More attention
must be paid to the below-ground voltage of the VBOOT during this spike, because, as
already explained above, the internal junction VBOOT to substrate could turn on; for very
short periods (some tens of nanoseconds) this is typically not a problem.
Figure 33 summarizes the main conditions to avoid any issues related to the below-ground
voltage phenomenon in steady-state. As explained in Section 9.1, typically the static belowground voltage is hardly higher than 2 V, so for most applications these constraints are not
usually necessary.
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Below-ground voltage on the OUT pin
AN2785
Figure 33. L6393 safe operating range when OUT pin is below ground voltage (in
steady state)
Vcc
Vcc-Vboot
Vboot
Vboot > - 0.3V
0V
Vboot-Vout < 20V
below ground
voltage on Vout
Vout
9.4
Functionality of L6393 outputs in below-ground condition
The L6393 IC gate driver makes use of a level shifter in order to send the set-reset
information to the high-side floating section. The level shifter, shown in Figure 34, is mainly
composed of two high-voltage switches, for set/reset signals, driven by the low-voltage
section and linked to two pull-up resistors connected to the BOOT pin.
Figure 34. Driver functionality in below-ground voltage condition on OUT pin
Vcc
Vcc
Vcc-Vboot
Vboot
Vboot
Vboot
Level
Shifter
Vboot > 5V
Vboot-Vout
0V
for full
functionality
of level shifter
High Side
floating
section
set
Low Side
section
gnd
HVG
reset
gnd
Vout
below ground voltage on Vout
Vout
The two level-shifted signals are then fed into a logic latch in the high-side floating section,
providing the logic state for the high-side gate driver (HVG output).
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Below-ground voltage on the OUT pin
The L6393 IC provides the full switching functionality of the high-side section until the level
shifter is operating. Because the two pull-up resistors are connected to the floating supply
VBOOT of the high-side floating section, the driver still works properly if the OUT voltage
begins to go below ground. This means that the operating limit for the level-shifter structure
has to be referred to the absolute value of the BOOT voltage with respect to ground. In fact,
the BOOT voltage can be considered as the supply of the level-shifter block. The minimum
operating value of the level-shifter supply is 5 V, so the VBOOT value must be at least 5 V.
The VBOOT - VOUT voltage can have any value in the range of 12.4 V ÷ 20 V. If the BOOT
voltage is between 0 and 5 V, the functionality of the level shifter is not certain, but internal
structures should not be damaged.
The following section provides some examples.
9.4.1
Steady-state (DC) conditions
When the LVG is OFF, the bootstrap diode only turns on when the BOOT voltage is about
2 V below VCC (worst case: minimum voltage drop value), so it could overcharge the
bootstrap capacitor up to a maximum voltage of about VCC - 2 V - VOUT. In order to not
overcome the value of 20V on the VBOOT - VOUT voltage, the OUT pin could be forced
permanently to the value of VCC - 2 V - 20 V; the L6393 IC would still operate safely, making
the HVG output switching as the HIN logic input.
Table 3.
Minimum VOUT in DC condition providing safe and full operation of the
high-side section
Example 1
Example 2
Example 3
VCC
12.5
15
17
VBOOT
10.5
13
15
VOUT (min)
-9.5
-7
-5
VBOOT - VOUT (max)
20
20
20
In any case it must be emphasized, as already explained in the previous paragraph, that in
most applications the static below-ground voltage of the OUT pin is very rarely lower than
approximately - 2 V.
9.4.2
Transient conditions
If the time during which the OUT pin goes below ground is limited, the bootstrap overcharge
will probably not overcome the safe operating range (20 V) of VBOOT - VOUT, even if the
VOUT voltage is lower than the limit of VCC - 2 V - 20 V mentioned in the previous
paragraph. In such a case, the gate driver and the high-side section are fully operational if
the VBOOT voltage remains above 5 V, as explained previously for the proper functioning of
the high-side level shifter. In any case, the logic state is maintained as long as the VBOOT
remains above ground.
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Below-ground voltage on the OUT pin
AN2785
Figure 35. OUT below-ground voltage in transient conditions: limited boot
overcharging
VO UT
VB OOT
VB OOT - V OUT
VCC
VB OOT - VO UT
bef or ov erc harge
V B OOT - VOU T
V B OOT - VOU T
s afe operating
max imum range
(20V )
real
overc harge
V BO OT - V OU T
v irtual final v alue
in s t eady st ate
0V
VB GV _st ati c
t
V BGV _s pike
VOU T
High side O FF time
HVG
HIN
9.4.3
Below-ground voltage spikes
As explained in the previous section, the dynamic contribution of the below-ground voltage
on the OUT pin does not have enough time to overcharge the bootstrap capacitor. This fact
usually excludes the risk of exceeding the recommended maximum value of 20 V for the
VBOOT -VOUT voltage, but on the other hand it increases the danger of pulling the BOOT pin
down below ground, then violating its absolute minimum rating. As mentioned above, for
safe operation of the IC gate driver, this phenomenon should be avoided. However, note that
applicative bench tests have shown that the L6393 also works with below-ground spikes on
the OUT pin that well exceed -50 V (see Figure 36).
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Below-ground voltage on the OUT pin
Figure 36. Example of below-ground voltage spike
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Layout suggestions
10
AN2785
Layout suggestions
Typically, for power applications using high voltages and large load currents, the board
layout of all circuits related to the power stage is important. Board layout includes different
aspects, such as track dimensions (length and width), circuit areas, but also the proper
routing of the traces and the optimized reciprocal arrangement of the various system
elements and power sources in the PCB area.
There are several reasons for paying attention to the layout, which include all the EMI
issues, both induced and perceived by the application, over-voltage spikes due to parasitic
inductances along the PCB traces, proper connection of the sense blocks and the logic
inputs of the L6393 device.
Figure 37 provides some layout guidelines and suggestions for a full-bridge application.
Figure 37. Layout suggestion for a H-bridge power system
MINIMIZE
MINIMIZE
THE LENGHT OF THIS AREA
THESE PATHS
TRACKS SWITCHING WITH HIGH VOLTAGE
TRANSITIONS SHOULD BE KEPT FAR FROM
THE LOGIC AND SENSING LINES
H.V.
L6393
L6393
HVG
inputs
control signals
phase 1
OUT
LOAD
phase 2
LP1
LP1
BULK
CAPACITOR
LVG
uC
GND
GND
(IF USED) LP2
CHOSE RSENSE
WITH LOW
PARASITIC
INDUCTANCE
LP3
DRIVER GROUND
MINIMIZE
TO LIMIT
THE BELOW
GROUND SPIKE
ON OUT PIN
+
LP2
LP3
LP4
LP4
SIGNAL GROUND
POWER GROUND
MINIMIZE TO LIMIT THE NOISE
ON THE INPUT LOGIC SIGNALS AND ON THE
ANALOG OPAMP OUTPUT
LP5
NOT CRITICAL
As explained in Section 6.1.6, the gate driving PCB traces should be designed as short as
possible and the circuit area should be minimized to avoid sensitivity of such structures to
surrounding noise. Typically, a good power system layout keeps the power IGBTs (or
MOSFETs) of each half-bridge as close as possible to the related gate driver.
Figure 37 shows a set of parasitic inductances related to the different circuit tracks. The
various inductance groups may have undesired effects which should be limited as much as
possible. Moreover, note that Figure 37 emphasizes parasitic inductances located on the
lines usually managing high voltages and fast current transitions, which are very noisy.
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Layout suggestions
The group of LP1, LP2 and LP3 parasitic inductances is located along the low-side path of
each half-bridge, between the OUT pin and the GND of the related driver, and provides an
undesired contribution to the issue of below-ground voltage spikes on each OUT pin of the
L6393 (described in Section 9.1). In fact, at the beginning of the current recirculation on the
low-side switches, the current may experience a high dI/dt which is able to produce, on
those parasitic inductances, significant voltage spikes. Those spikes add up with the voltage
drop of the low-side diode and of the RSENSE (when present) and have a negative sign, so
the overall voltage drop between OUT and GND may be significant. The suggestion is to
limit as much as possible each contribution to this phenomenon by limiting the length of
tracks LP1, LP2 and LP3 and by using an RSENSE resistor with low intrinsic inductance. LP1
may be reduced by connecting the OUT line directly to the collector (or drain) of the low-side
IGBT (or MOSFET), LP2 may be reduced by placing the RSENSE resistor as close as
possible to the emitter (or source) of the low-side IGBT (or MOSFET). The LP3 may be
minimized by connecting the GND line (also called driver ground) of the related gate driver
directly to the RSENSE resistor.
LP4 represents the parasitic inductance located between the ground connections of each
gate driver (driver ground) and the ground connection of the application controller (also
called signal ground). Due to its location, this parasitic inductance introduces noise which is
experienced by the input logic signals and by the L6393 comparator output signal. In fact,
each phase of the bridge causes high currents (with high dI/dt) to flow on these paths,
causing voltage noise which drops between the gate driver ground and the controller
ground. This noise between the two grounds is directly added to all logic and analog voltage
signals between the gate driver and the micro-controller, including the input logic signals
and the analog output of the related comparator. It is recommended to minimize this noise
by reducing as much as possible the distance between the signal ground and the driver
ground (for each gate driver in the system). In general, it is recommended to connect the
signal ground to the various driver grounds through a star connection, in order to improve
the balancing and symmetry for any kind of driving topology.
Note:
Ground loops must be avoided; only a single path must connect two different ground nodes.
The LP5 parasitic inductance is not usually critical because it stands between the minus
terminal of the bulk capacitor and the signal/power ground: the spikes on this parasitic
element have little influence on other system nodes.
Another useful suggestion is to respect some distance between the lines that switch with
high-voltage transitions and the signal lines sensitive to electrical noise. The tracks of each
OUT phase bringing significant currents and high voltages should be separated from the
logic lines and analog sensing circuits of the comparators.
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Revision history
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Revision history
Table 4.
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Document revision history
Date
Revision
01-Dec-2009
1
Changes
Initial release.
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