L6393 Half-bridge gate driver Features ■ High voltage rail up to 600 V ■ dV/dt immunity ± 50 V/nsec in full temperature range ■ Driver current capability: – 290 mA source, – 430 mA sink 3/ ■ Switching times 75/35 nsec rise/fall with 1 nF load ■ 3.3 V, 5 V CMOS/TTL inputs comparators with hysteresis ■ Integrated bootstrap diode ■ Uncommitted comparator ■ Adjustable dead-time ■ Compact and simplified layout ■ Bill of material reduction ■ Flexible, easy and fast design Application ■ Motor driver for home appliances ■ Factory automation ■ Industrial drives and fans ■ HID ballasts ■ Power supply units Table 1. $)0 Description The L6393 is a high-voltage device manufactured with the BCD “OFF-LINE” technology. It is a single chip half-bridge gate driver for N-channel power MOSFET or IGBT. The high side (floating) section is designed to stand a voltage rail up to 600 V. The logic inputs are CMOS/TTL compatible down to 3.3 V for easy interfacing microcontroller/DSP. The IC embeds an uncommitted comparator available for protections against overcurrent, overtemperature, etc. Device summary Order codes Package L6393N DIP-14 Packaging Tube L6393D SO-14 L6393DTR August 2010 Tape and reel Doc ID 14497 Rev 4 1/19 www.st.com 19 Contents L6393 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 Waveforms definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8 Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.1 CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2/19 Doc ID 14497 Rev 4 L6393 1 Block diagram Block diagram Figure 1. Block diagram "//4342!0$2)6%2 6## &,/!4).'3425#452% "//4 56 $%4%#4)/. FROM,6' 56 $%4%#4)/. (6' $2)6%2 0(!3% ,%6%, 3()&4%2 3 2 (6' ,/')# "2!+% 3(//4 4(2/5'( 02%6%.4)/. 6## 3$ #0/54 /54 ,6' $2)6%2 ,6' 6 #/-0!2!4/2 #0 #0 $4 $%!$ 4)-% '.$ ".W Doc ID 14497 Rev 4 3/19 Pin connection 2 L6393 Pin connection Figure 2. Pin connection (top view) 0(!3% "//4 3$ (6' "2!+% /54 6## .# $4 ,6' #0/54 #0 '.$ #0 !-V Table 2. Pin description Pin N# Pin name Type Function 1 PHASE I Driver logic input (active high) 2 SD (1) I Shut down input (active low) 3 BRAKE I Driver logic input (active low) 4 VCC P Lower section supply voltage 5 DT I Dead time setting 6 CPOUT O Comparator output (open drain) 7 GND P Ground 8 CP- I Comparator negative input 9 CP+ I Comparator positive input 10 LVG (1) O Low side driver output 11 NC 12 OUT P High side (floating) common voltage 13 HVG (1) O High side driver output 14 BOOT P Bootstrapped supply voltage Not connected 1. The circuit provides less than 1 V on the LVG and HVG pins (@ Isink = 10 mA), with VCC > 3 V. This allows omitting the “bleeder” resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low; the gate driver assures low impedance also in SD condition. 4/19 Doc ID 14497 Rev 4 L6393 3 Truth table Truth table Table 3. Truth table Inputs Note: Outputs SD PHASE BRAKE LVG HVG L X X L L H L L H L H L H H L H H L H L H H H L H X: don’t care In the L6393 IC the two input signals PHASE and BRAKE are fed into an AND logic port and the resulting signal is in phase with the high side output HVG and in opposition of phase with the low side output LVG. This means that if BRAKE is kept to high level, the PHASE signal drives the half-bridge in phase with the HVG output and in opposition of phase with the LVG output. If BRAKE is set to low level the low side output LVG is always ON and the high side output HVG is always OFF, whatever the PHASE signal. This kind of logic interface provides the possibility to control the power stages using the PHASE signal to select the current direction in the bridge and the BRAKE signal to perform current slow decay on the low sides. From the point of view of the logic operations the two signals PHASE and BRAKE are completely equivalent, that means the two signals can be exchanged without any change in the behavior on the resulting output signals (see the Figure 1 on page 3). Note: The dead time between the turn OFF of one power switch and the turn ON of the other power switch is defined by the resistor connected between DT pin and the ground. Doc ID 14497 Rev 4 5/19 Electrical data L6393 4 Electrical data 4.1 Absolute maximum ratings Table 4. Absolute maximum ratings Value Symbol Parameter Unit Min max VCC Supply voltage -0.3 21 V VOUT Output voltage Vboot - 21 Vboot + 0.3 V Vboot Bootstrap voltage -0.3 620 V Vhvg High side gate output voltage VOUT - 0.3 Vboot + 0.3 V Vlvg Low side gate output voltage -0.3 VCC + 0.3 V Vcp+ Comparator positive input voltage -0.3 VCC + 0.3 V Vcp- Comparator negative input voltage -0.3 VCC + 0.3 V Vi Logic input voltage -0.3 15 V Vod Open drain voltage -0.3 15 V Allowed output slew rate 50 V/ns Ptot Total power dissipation (TA = 25 °C) 800 mW TJ Junction temperature 150 °C 150 °C dVOUT/dt TSTG Storage temperature -50 Note: ESD immunity for pins 12, 13 and 14 is guaranteed up to 1 kV (human body model) 4.2 Thermal data Table 5. Symbol Rth(JA) 6/19 Thermal data Parameter Thermal resistance junction to ambient max. Doc ID 14497 Rev 4 SO-14 DIP-14 Unit 165 100 °C/W L6393 4.3 Electrical data Recommended operating conditions Table 6. Recommended operating conditions Symbol Pin VCC 4 VBO (1) Parameter Test condition Min Max Unit Supply voltage 10 20 V 14-12 Floating supply voltage 9.8 20 V 580 V -9 (2) Vout 12 DC Output voltage VCP- 8 Comparator negative input voltage VCP+≤ 2.5V Vcc V VCP+ 9 Comparator positive input voltage VCP-≤ 2.5V Vcc (3) V fsw Switching frequency HVG, LVG load CL = 1 nF 800 kHz TJ Junction temperature 125 °C (3) -40 1. VBO = Vboot - Vout 2. LVG off. VCC = 10 V. Logic is operational if Vboot > 5 V, refer to AN2785 for more details. 3. At least one of the comparator's input must be lower than 2.5V to guarantee proper operation. Doc ID 14497 Rev 4 7/19 Electrical characteristics L6393 5 Electrical characteristics 5.1 AC operation VCC = 15 V, TJ = +25 °C Table 7. Symbol AC operation electrical characteristics Pin Parameter Test condition Min Typ Max Unit 50 125 200 ns 50 125 200 ns 50 125 200 ns 30 ns AC operation ton toff tsd 1,3 vs 10, 13 tf Vout = 0 V Vboot = Vcc CL = 1 nF Vi = 0 to 3.3 V see Figure 3 on page 9 Delay matching, HS and LS turn-on/off 5 Dead time setting range (1) Matching dead time (2) MDT tr High/low side driver turnoff propagation delay 2 vs Shut down to high/low side 10, propagation delay 13 MT DT High/low side driver turn-on propagation delay 10, 13 RDT = 0, CL = 1 nF 0.1 0.18 0.25 RDT = 37 kΩ, CL = 1 nF, CDT = 100 nF 0.48 0.6 0.72 RDT = 136 kΩ, CL = 1 nF, CDT = 100 nF 1.35 1.6 1.85 RDT = 260 kΩ, CL = 1 nF, CDT = 100 nF 2.6 3.0 3.4 RDT = 0 Ω; CL = 1 nF 80 RDT = 37 kΩ; CL = 1 nF; CDT = 100 nF 120 RDT = 136 kΩ; CL = 1 nF; CDT = 100 nF 250 RDT = 260 kΩ; CL = 1 nF; CDT = 100 nF 400 ns Rise time CL = 1 nF 75 120 ns Fall time CL = 1 nF 35 70 ns 1. See Figure 4 on page 9 2. MDT = I DTLH - DTHL I see Figure 5 on page 12 8/19 μs Doc ID 14497 Rev 4 L6393 Electrical characteristics Figure 3. Timing PHASE IN 50% 50% BRAKE tr tf 90% HVG 90% 10% 10% ton PHASE IN toff 50% 50% BRAKE tf tr 90% 90% LVG 10% 10% ton toff 50% SD tf 90% LVG/HVG 10% tsd Figure 4. Typical dead time vs. DT resistor value 3.5 3 Approximated formula for Rdt calculation (typ.): Rdt[kΩ] = 92.2 · DT[μs] - 16.6 DT (us) 2.5 2 1.5 1 0.5 0 0 50 100 150 200 250 300 Rdt (kOhm) Doc ID 14497 Rev 4 9/19 Electrical characteristics 5.2 L6393 DC operation VCC = 15 V; TJ = +25 °C Table 8. Symbol DC operation electrical characteristics Pin Parameter Test condition Min Typ Max Unit 1.2 1.5 1.8 Low supply voltage section Vcc_hys Vcc UV hysteresis Vcc_thON Vcc UV turn ON threshold 9 9.5 10 Vcc_thOFF Vcc UV turn OFF threshold 7.6 8 8.4 110 150 Iqccu V V 4 VCC = 7 V; SD = 5 V; PHASE and Undervoltage quiescent supply current BRAKE = GND; RDT = 0 Ω; CP + = GND; CP - = 0.5 V µA Iqcc VCC = 15 V; SD = 5 V; PHASE and BRAKE = GND; RDT = 0 Ω; CP + = GND; CP - = 0.5 V Quiescent current 600 1000 Bootstrapped supply voltage section (1) VBO_hys VBO UV hysteresis 0.8 1.0 1.2 V VBO_thON VBO UV turn ON threshold 8.2 9 9.8 V VBO_thOFF VBO UV turn OFF Threshold 7.3 8 8.7 V 40 100 IQBOU IQBO ILK RDSon 14 Undervoltage VBOOT quiescent current VBO = 7 V SD = 5 V; PHASE and BRAKE = 5 V; RDT = 0 Ω; CP + = GND; CP - = 0.5 V VBOOT quiescent current VBO = 15 V SD = 5 V; PHASE and BRAKE = 5 V; RDT = 0 Ω; CP + = GND; CP - = 0.5 V High voltage leakage current Vhvg = Vout = Vboot = 600 V Bootstrap driver on resistance (2) LVG ON µA 140 210 10 120 Ω Driving buffers section Iso Isi High/low side source short circuit 10, current 13 High/low side sink short circuit current VIN = Vih (tp < 10 µs) 200 290 mA VIN = Vil (tp < 10 µs) 250 430 mA Logic inputs Vil Vih 10/19 1, Low logic level voltage 2, 3 High logic level voltage 0.8 2.25 Doc ID 14497 Rev 4 V V L6393 Table 8. Symbol IPHASEh Electrical characteristics DC operation electrical characteristics (continued) Pin PHASE logic “1” input bias current PHASE = 15 V PHASE logic “0” input bias current PHASE = 0 V BRAKE logic “1” input bias current BRAKE = 15 V BRAKE logic “0” input bias current BRAKE = 0 V SD logic “1” input bias current SD = 15 V SD logic “0” input bias current SD = 0 V Min Typ 20 40 Max Unit 100 1 20 40 100 3 IBRAKEl ISDh Test condition 1 IPHASEl IBRAKEh Parameter µA 1 10 30 100 2 ISDl 1 1. VBO = Vboot - Vout 2. RDSon is tested in the following way: RDSon = [(VCC - VCBOOT1) - (VCC - VCBOOT2)] / [I1(VCC,VCBOOT1) - I2(VCC,VCBOOT2)] where I1 is pin 14 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2. Table 9. Symbol Vio Sense comparator Pin Input offset voltage 6 td_comp SR Test conditions Min Typ -15 Max Unit 15 mV 8, 9 Iib Vol Parameter 6 Input bias current VCP+ = 1 V 1 µA Open drain low level output voltage Iod = - 3 mA 0.5 V Comparator delay Rpu = 100 kΩ to 5 V; VCP- = 0.5 V 90 130 ns Slew rate CL = 180 pF, Rpu = 5 kΩ 60 Doc ID 14497 Rev 4 V/µs 11/19 Waveforms definition 6 L6393 Waveforms definition Figure 5. Dead time waveform definition PHASE BRAKE LVG DTLH DTLH DTHL HVG 12/19 Doc ID 14497 Rev 4 DTHL L6393 7 Typical application diagram Typical application diagram Figure 6. Application diagram %227675$3'5,9(5 9&& 89 '(7(&7,21 )/2$7,1*6758&785( IURP/9* %227 89 '(7(&7,21 +9 +9* '5,9(5 3+$6( /(9(/ 6+,)7(5 6 +9* 287 &ERRW 5 /2*,& %5$.( 6+227 7+528*+ 35(9(17,21 9&& 6' 72/2$' /9* '5,9(5 /9* &3287 9 &203$5$725 &3 &3 '7 '($' 7,0( *1' !-V Doc ID 14497 Rev 4 13/19 Bootstrap driver 8 L6393 Bootstrap driver A bootstrap circuitry is needed to supply the high voltage section. This function is normally accomplished by a high voltage fast recovery diode (Figure 7.a). In the L6393 a patented integrated structure replaces the external diode. It is realized by a high voltage DMOS, driven synchronously with the low side driver (LVG), with diode in series, as shown in Figure 7.b. An internal charge pump (Figure 7.b) provides the DMOS driving voltage. 8.1 CBOOT selection and charging To choose the proper CBOOT value the external MOS can be seen as an equivalent capacitor. This capacitor CEXT is related to the MOS total gate charge: Q gate C EXT = -------------V gate The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss. It has to be: C BOOT » C EXT e.g.: if Qgate is 30 nC and Vgate is 10 V, CEXT is 3 nF. With CBOOT = 100 nF the drop would be 300 mV. If HVG has to be supplied for a long time, the CBOOT selection has to take into account also the leakage and quiescent losses. e.g.: HVG steady state consumption is lower than 200 µA, so if HVG TON is 5 ms, CBOOT has to supply 1 µC to CEXT. This charge on a 1 µF capacitor means a voltage drop of 1 V. The internal bootstrap driver gives a great advantage: the external fast recovery diode can be avoided (it usually has great leakage current). This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the LVG is on. The charging time (Tcharge) of the CBOOT is the time in which both conditions are fulfilled and it has to be long enough to charge the capacitor. The bootstrap driver introduces a voltage drop due to the DMOS RDSon (typical value: 120 Ω). At low frequency this drop can be neglected. Anyway increasing the frequency it must be taken in to account. 14/19 Doc ID 14497 Rev 4 L6393 Bootstrap driver The following equation is useful to compute the drop on the bootstrap DMOS: Q gate V drop = I ch arg e R dson → V drop = ------------------- R dson T ch arg e where Qgate is the gate charge of the external power MOS, RDSon is the on resistance of the bootstrap DMOS, and Tcharge is the charging time of the bootstrap capacitor. For example: using a power MOS with a total gate charge of 30 nC the drop on the bootstrap DMOS is about 1 V, if the Tcharge is 5 µs. In fact: 30nC V drop = --------------- ⋅ 120Ω ∼ 0.7V 5μS Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode can be used. Figure 7. Bootstrap driver $"//4 63 "//4 "//4 63 (6 (6' (6 #"//4 (6' 6/54 #"//4 6/54 4/,/!$ 4/,/!$ ,6' ,6' A B !-V Doc ID 14497 Rev 4 15/19 Package mechanical data 9 L6393 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Table 10. DIP-14 mechanical data mm. inch Dim. Min a1 0.51 B 1.39 Typ Min Typ Max 0.020 1.65 0.055 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 15.24 0.600 F 7.1 0.280 I 5.1 0.201 L Z Figure 8. 16/19 Max 3.3 1.27 0.130 2.54 Package dimensions Doc ID 14497 Rev 4 0.050 0.100 L6393 Package mechanical data Table 11. SO-14 mechanical data mm. inch Dim. Min Typ A a1 Max Min Typ 1.75 0.1 0.2 a2 Max 0.068 0.003 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 c1 0.019 45° (typ.) D 8.55 8.75 0.336 0.344 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 7.62 0.300 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M 0.68 S Figure 9. 0.026 8° (max.) Package dimensions Doc ID 14497 Rev 4 17/19 Revision history 10 L6393 Revision history Table 12. 18/19 Document revision history Date Revision Changes 03-Mar-2008 1 Initial release 18-Mar-2008 2 Cover page updated 17-Nov-2009 3 Updated: Cover page, Table 4 on page 6, Table 6 on page 7, Table 7 on page 8, Table 8 on page 10, Table 9 on page 11 11-Aug-2010 4 Updated: Table 1 on page 1, Table 6 on page 7 and Table 8 on page 10 Doc ID 14497 Rev 4 L6393 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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