L6390 High-voltage high/low-side driver Datasheet − production data Features ■ High-voltage rail up to 600 V ■ dV/dt immunity ±50 V/nsec in full temperature range ■ Driver current capability: – 290 mA source – 430 mA sink SO-16 DIP-16 ■ Switching times 75/35 nsec rise/fall with 1 nF load ■ 3.3 V, 5 V TTL/CMOS inputs with hysteresis Description ■ Integrated bootstrap diode ■ Operational amplifier for advanced current sensing ■ Comparator for fault protection The L6390 is a high-voltage device manufactured with BCD™ “offline” technology. It is a single-chip half bridge gate driver for N-channel Power MOSFETs or IGBT. ■ Smart shutdown function ■ Adjustable deadtime ■ Interlocking function ■ Compact and simplified layout ■ Bill of material reduction ■ Effective fault protection ■ Flexible, easy and fast design The high-side (floating) section is designed to stand a voltage rail up to 600 V. The logic inputs are CMOS/TTL compatible down to 3.3 V for easy microcontroller/DSP interfacing. The IC embeds an operational amplifier suitable for advanced current sensing in applications such as field oriented motor control. An integrated comparator is available for protection against overcurrent, overtemperature, etc. Applications ■ Motor driver for home appliances, factory automation, industrial drives ■ HID ballasts, power supply units Table 1. Device summary Order code Package Packaging L6390N DIP-16 Tube L6390D SO-16 Tube L6390DTR SO-16 Tape and reel July 2012 This is information on a product in full production. Doc ID 14493 Rev 7 1/26 www.st.com 26 Contents L6390 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 Waveforms definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 Smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8 Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9 Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9.1 CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2/26 Doc ID 14493 Rev 7 L6390 1 Block diagram Block diagram Figure 1. Block diagram BOOTSTRAP DRIVER VCC 4 from LVG HVG DRIVER 3 S LEVEL SHIFTER 15 R HVG LOGIC 5V SHOOT THROUGH PREVENTION LIN BOOT UV DETECTION UV DETECTION HIN 16 FLOATING STRUCTURE 14 OUT 1 VCC LVG DRIVER LVG SD/OD GND 2 8 11 SD LATCH SMART SD 5V COMPARATOR 10 + - CP+ + VREF DT OPOUT 5 DEAD VCC TIME OPAMP 7 + - 9 6 Doc ID 14493 Rev 7 OP+ OP- 3/26 Pin connection 2 L6390 Pin connection Figure 2. Table 2. Pin connection (top view) LIN 1 16 BOOT SD/OD 2 15 HVG HIN 3 14 OUT VCC 4 13 NC DT 5 12 NC OP- 6 11 LVG OPOUT 7 10 CP+ GND 8 9 OP+ Pin description Pin n # Pin name Type 1 LIN I 2 SD/OD (1) I/O 3 HIN I High-side driver logic input (active high) 4 VCC P Lower section supply voltage 5 DT I Deadtime setting 6 OP- I Op amp inverting input 7 OPOUT O Op amp output 8 GND P Ground 9 OP+ I Op amp non inverting input 10 CP+ I Comparator input O Low-side driver output 11 LVG (1) 12, 13 NC 14 OUT (1) 15 HVG 16 BOOT Function Low-side driver logic input (active low) Shutdown logic input (active low)/open drain (comparator output) Not connected P High-side (floating) common voltage O High-side driver output P Bootstrap supply voltage 1. The circuit provides less than 1 V on the LVG and HVG pins (@ Isink = 10 mA), with VCC > 3 V. This allows the omission of the “bleeder” resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low; the gate driver assures low impedance also in SD condition. 4/26 Doc ID 14493 Rev 7 L6390 3 Truth table Truth table Table 3. Truth table Input Note: Output SD LIN HIN LVG HVG L X X L L H H L L L H L H L L H L L H L H H H L H X: don't care. Doc ID 14493 Rev 7 5/26 Electrical data L6390 4 Electrical data 4.1 Absolute maximum ratings Table 4. Absolute maximum ratings Value Symbol Parameter Unit Min. Max. Vcc Supply voltage - 0.3 21 V Vout Output voltage Vboot - 21 Vboot + 0.3 V Vboot Bootstrap voltage - 0.3 620 V Vhvg High-side gate output voltage Vout - 0.3 Vboot + 0.3 V Vlvg Low-side gate output voltage - 0.3 Vcc + 0.3 V Vop+ Op amp non-inverting input - 0.3 Vcc + 0.3 V Vop- Op amp inverting input - 0.3 Vcc + 0.3 V Vcp+ Comparator input voltage - 0.3 Vcc + 0.3 V Vi Logic input voltage - 0.3 15 V Vod Open drain voltage - 0.3 15 V Allowed output slew rate 50 V/ns Ptot Total power dissipation (TA = 25 °C) 800 mW TJ Junction temperature 150 °C Tstg Storage temperature 150 °C dVout/dt -50 Note: ESD immunity for pins 14, 15 and 16 is guaranteed up to 1 kV (human body model). 4.2 Thermal data Table 5. Symbol Rth(JA) 6/26 Thermal data Parameter Thermal resistance junction-to-ambient Doc ID 14493 Rev 7 SO-16 DIP-16 Unit 155 100 °C/W L6390 4.3 Electrical data Recommended operating conditions Table 6. Recommended operating conditions Symbol Pin Vcc 4 VBO (1) Vout 16-14 14 Parameter Test condition Min. Max. Unit Supply voltage 12.5 20 V Floating supply voltage 12.4 20 V 580 V 800 kHz 125 °C DC output voltage fsw Switching frequency TJ Junction temperature -9 (2) HVG, LVG load CL = 1 nF -40 1. VBO = Vboot - Vout. 2. LVG off. Vcc = 12.5 V. Logic is operational if Vboot > 5 V. Refer to AN2738 for more details. Doc ID 14493 Rev 7 7/26 Electrical characteristics L6390 5 Electrical characteristics 5.1 AC operation Table 7. AC operation electrical characteristics (VCC = 15 V; TJ = +25 °C) Symbol Pin Parameter Test condition toff High/low-side driver turn-on 1 vs. 11 propagation delay 3 vs. 15 High/low-side driver turn-off propagation delay tsd 2 vs. Shutdown to high/low-side 11, 15 driver propagation delay ton tisd Comparator triggering to high/low-side driver turn-off propagation delay MT Delay matching, HS and LS turn-on/off DT 5 Matching deadtime (2) MDT tr tf Deadtime setting range (1) Vout = 0 V Vboot = Vcc CL = 1 nF Vi = 0 to 3.3 V See Figure 3. Measured applying a voltage step from 0 V to 3.3 V to pin CP+. Typ. Max. Unit 50 125 200 ns 50 125 200 ns 50 125 200 ns 50 200 250 ns 30 ns RDT = 0, CL = 1 nF 0.1 0.18 0.25 μs RDT = 37 kΩ, CL = 1 nF, CDT = 100 nF 0.48 0.6 0.72 μs RDT = 136 kΩ, CL = 1 nF, CDT = 100 nF 1.35 1.6 1.85 μs RDT = 260 kΩ, CL = 1 nF, CDT = 100 nF 2.6 3.0 3.4 μs RDT = 0, CL = 1 nF 80 ns RDT = 37 kΩ, CL = 1 nF, CDT = 100 nF 120 ns RDT = 136 kΩ, CL = 1 nF, CDT = 100 nF 250 ns RDT = 260 kΩ, CL = 1 nF, CDT = 100 nF 400 ns Rise time CL = 1 nF 75 120 ns Fall time CL = 1 nF 35 70 ns 11, 15 1. See Figure 4 on page 9. 2. MDT = | DTLH - DTHL | see Figure 5 on page 13. 8/26 Min. Doc ID 14493 Rev 7 L6390 Electrical characteristics Figure 3. Timing LIN 50% 50% tr tf 90% 90% 10% LVG 10% toff ton HIN 50% 50% tr tf 90% 90% 10% H VG 10% toff ton 50% SD tf 90% 10% LVG/H VG tsd Figure 4. Typical deadtime vs. DT resistor value $SSUR[LPDWHGIRUPXODIRU 5GWFDOFXODWLRQW\S '7XV 5GW>Nȍ@ Â'7>V@ 5GWN2KP Doc ID 14493 Rev 7 9/26 Electrical characteristics L6390 5.2 DC operation Table 8. DC operation electrical characteristics (VCC = 15 V; TJ = + 25 °C) Symbol Pin Parameter Test condition Min. Typ. Max. Unit Vcc UV hysteresis 1200 1500 1800 mV Vcc_thON Vcc UV turn-ON threshold 11.5 12 12.5 V Vcc_thOFF Vcc UV turn-OFF threshold 10 10.5 11 V Undervoltage quiescent supply current Vcc = 10 V SD = 5 V; LIN = 5 V; HIN = GND; RDT = 0 Ω; CP+=OP+=GND; OP-=5 V 90 120 150 μA Iqcc Quiescent current Vcc = 15 V SD = 5 V; LIN = 5 V; HIN = GND; RDT = 0 Ω; CP+=OP+=GND; OP-=5 V 300 720 1000 μA Vref Internal reference voltage 500 540 580 mV VBO UV hysteresis 1200 1500 1800 mV VBO_thON VBO UV turn-ON threshold 11.1 11.5 12.1 V VBO_thOFF VBO UV turn-OFF threshold 9.8 10 10.6 V Undervoltage VBO quiescent current VBO = 9 V SD = 5 V; LIN and HIN = 5 V; RDT = 0 Ω; CP+=OP+=GND; OP-=5 V 30 70 110 μA IQBO VBO quiescent current VBO = 15 V SD = 5 V; LIN and HIN = 5 V; RDT = 0 Ω; CP+=OP+=GND; OP-=5 V 30 150 210 μA ILK High-voltage leakage current Vhvg = Vout = Vboot = 600 V 10 μA Bootstrap driver onresistance (2) LVG ON Low supply voltage section Vcc_hys Iqccu 4 Bootstrapped supply voltage section (1) VBO_hys IQBOU 16 RDS(on) 120 Ω Driving buffers section Iso Isi 10/26 11, 15 High/low-side source shortcircuit current VIN = Vih (tp < 10 μs) 200 290 mA High/low-side sink shortcircuit current VIN = Vil (tp < 10 μs) 250 430 mA Doc ID 14493 Rev 7 L6390 Electrical characteristics Table 8. DC operation electrical characteristics (VCC = 15 V; TJ = + 25 °C) (continued) Symbol Pin Parameter Test condition Min. Typ. Max. Unit Logic inputs Vil Low level logic threshold voltage 0.8 1.1 V High level logic threshold voltage 1.9 2.25 V 0.8 V 260 μA 1 μA 20 μA 1 μA 100 μA 1 μA 1, 2, 3 Vih Single input voltage LIN and HIN connected together and floating HIN logic “1” input bias current HIN = 15 V IHINl HIN logic “0” input bias current HIN = 0 V ILINl LIN logic “0” input bias current LIN = 0 V ILINh LIN logic “1” input bias current LIN = 15 V ISDh SD logic “1” input bias current SD = 15 V SD logic “0” input bias current SD = 0 V Vil_S 1, 3 IHINh 110 175 3 3 6 1 10 40 2 ISDl 1. VBO = Vboot - Vout. 2. RDSON is tested in the following way: RDSON = [(VCC - VCBOOT1) - (VCC - VCBOOT2)] / [I1(VCC,VCBOOT1) - I2(VCC,VCBOOT2)] where I1 is pin 16 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2. Doc ID 14493 Rev 7 11/26 Electrical characteristics Table 9. Symbol Op amp characteristics (1) (VCC = 15 V, TJ = +25 °C) Pin Parameter Test condition Input offset voltage Vio Iio Iib L6390 Min. Max. Unit 6 mV 4 40 nA 100 200 nA 0 VCC-4 V 0.07 VCC-4 V Vic = 0 V, Vo = 7.5 V Input offset current 6, 9 Input bias current Vic = 0 V, Vo = 7.5 V (2) Input common mode voltage range Vicm VOPOUT Typ. Output voltage swing OPOUT = OP-; no load Source, Vid = +1; Vo = 0 V 16 30 mA Sink,Vid = -1; Vo = VCC 50 80 mA Slew rate Vi = 1 ÷ 4 V; CL = 100 pF; unity gain 2.5 3.8 V/μs GBWP Gain bandwidth product Vo = 7.5 V 8 12 MHz Avd Large signal voltage gain RL = 2 kΩ 70 85 dB SVR Supply voltage rejection ratio vs. VCC 60 75 dB Common mode rejection ratio 55 70 dB 7 Io Output short-circuit current SR CMRR 1. Operational amplifier is disabled when VCC is in UVLO condition. 2. The direction of input current is out of the IC. Table 10. Sense comparator characteristics (1) (VCC = 15 V, TJ = +25 °C) Symbol Pin Iib 10 Input bias current Vol 2 td_comp SR 2 Parameter Test condition Max. Unit VCP+ = 1 V 1 μA Open drain low-level output voltage Iod = - 3 mA 0.5 V Comparator delay SD/OD pulled to 5 V through 100 kΩ resistor 90 130 ns Slew rate CL = 180 pF; Rpu = 5 kΩ 60 1. Comparator is disabled when VCC is in UVLO condition. 12/26 Doc ID 14493 Rev 7 Min. Typ. V/μs L6390 Waveforms definition Figure 5. Deadtime and interlocking waveforms definition CONTROL SIGNAL EDGES OVERLAPPED: INTERLOCKING + DEAD TIME IINT ERL OCK ING LIN INT ERL OCK ING 6 Waveforms definition HIN LVG DTHL DTLH HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES SYNCHRONOUS (*): DEAD TIME HIN LVG DTLH DTHL HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES NOT OVERLAPPED, BUT INSIDE THE DEAD TIME: DEAD TIME HIN LVG DTLH DTHL HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN CONTROL SIGNALS EDGES NOT OVERLAPPED, OUTSIDE THE DEAD TIME: DIRECT DRIVING HIN LVG DTLH DTHL HVG gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) (*) HIN and LIN can be connected togheter and driven by just one control signal Doc ID 14493 Rev 7 13/26 Smart shutdown function 7 L6390 Smart shutdown function The L6390 integrates a comparator committed to the fault sensing function. The comparator has an internal voltage reference Vref connected to the inverting input, while the noninverting input is available on pin 10. The comparator input can be connected to an external shunt resistor in order to implement a simple overcurrent detection function. The output signal of the comparator is fed to an integrated MOSFET with the open drain output available on pin 2, shared with the SD input. When the comparator triggers, the device is set in shutdown state and both its outputs are set to low level leaving the half-bridge in tri-state. Figure 6. Smart shutdown timing waveforms comp Vref CP+ HIN/LIN PROTECTION HVG/LVG SD/OD open drain gate (internal) disable time Fast shut down: the driver outputs are set in SD state immediately after the comparator triggering even if the SD signal has not yet reach the lower input threshold An approximation of the disable time is given by: SHUT DOWN CIRCUIT VBIAS where: RSD SD/OD FROM/TO CONTROLLER CSD RON_OD SMART SD LOGIC RPD_SD AM12947v1 14/26 Doc ID 14493 Rev 7 L6390 Smart shutdown function In common overcurrent protection architectures the comparator output is usually connected to the SD input and an RC network is connected to this SD/OD line in order to provide a mono-stable circuit, which implements a protection time that follows the fault condition. Differently from the common fault detection systems, the L6390 smart shutdown architecture allows immediate turn-off of the outputs of the gate driver in the case of fault, by minimizing the propagation delay between the fault detection event and the actual output switch-off. In fact, the time delay between the fault detection and the output turn-off is no longer dependent on the value of the external RC network connected to the SD/OD pin. In the smart shutdown circuitry the fault signal has a preferential path which directly switches off the outputs after the comparator triggering. At the same time the internal logic turns on the open drain output and holds it on until the SD voltage goes below the SD logic input lower threshold. When such threshold is reached, the open drain output is turned off, allowing the external pull-up to recharge the capacitor. The driver outputs restart following the input pins as soon as the voltage at the SD/OD pin reaches the higher threshold of the SD logic input. The smart shutdown system provides the possibility to increase the time constant of the external RC network (that determines the disable time after the fault event) up to very large values without increasing the delay time of the protection. Any external signal provided to the SD pin is not latched and can be used as control signal in order to perform, for instance, PWM chopping through this pin. In fact when a PWM signal is applied to the SD input and the logic inputs of the gate driver are stable, the outputs switch from the low level to the state defined by the logic inputs and vice versa. In some applications it may be useful to latch the driver in the shutdown condition for an arbitrary time, until the controller decides to reset it to normal operation. This may, for example, be achieved with a circuit similar to the one shown in Figure 7. When the open drain starts pulling down the SD/OD pin, the external latch turns on and keeps the pin to GND, preventing it from being pulled up again once the SD logic input lower threshold is reached and the internal open drain turns off. One pin of the controller is used to release the external latch, and one to externally force a shutdown condition and also to read the status of the SD/OD pin. Figure 7. Protection latching example circuit VBOOT HIN LIN 3.3 / 5 V HVG VCC + VCC µC R1 20 KΩ GND DT 3.3 / 5 V SD_reset VDD GND R3 2.2 KΩ R4 20 KΩ SD_force/sense R2 1.5 K Ω OUT + LVG L6390 CP+ SD/OD OPOUT OP+ OP- To other driver/devices AM12949v1 In applications using only one L6390 for the protection of several different legs (such as a single-shunt inverter, for example) it may be useful to implement the resistor divider shown in Figure 8. This simple network allows the pushing of the SD pins of the other devices to a voltage lower than L6390 Vil, so that each device can reach its low logic level regardless of part-to-part variations of the thresholds. Doc ID 14493 Rev 7 15/26 Smart shutdown function Figure 8. L6390 SD level shifting example circuit HV BUS VBOOT HIN LIN L6390 HVG VCC - VDD GND R2 R SD_force GND DT R1 9*R VDD VCC C1 SD/OD OPOUT OUT LVG CP+ OP+ OP- C2 SD/OD C3 SD/OD R3 2*R SD_sense C1: disable time setting capacitor C2, C3: small noise filtering capacitors 16/26 L639x µC + L639x + VCC Doc ID 14493 Rev 7 AM12948v1 L6390 8 Typical application diagram Typical application diagram Figure 9. Application diagram BOOTSTRAP DRIVER VCC VCC 4 16 FLOATING STRUCTURE from LVG UV DETECTION UV DETECTION FROM CONTROLLER HIN H.V. 3 S LEVEL SHIFTER LIN 14 OUT TO LOAD 1 VBIAS GND HVG LOGIC VCC SD/OD 15 R SHOOT THROUGH PREVENTION FROM CONTROLLER 2 8 Cboot HVG DRIVER 5V FROM/TO CONTROLLER BOOT + LVG 11 SD LATCH SMART SD LVG DRIVER 5V COMPARATOR 10 + CP+ + VBIAS VREF DT 5 DEAD VCC TIME OPOUT OPAMP 7 + 9 OP+ OP- 6 TO ADC Doc ID 14493 Rev 7 17/26 Bootstrap driver 9 L6390 Bootstrap driver A bootstrap circuitry is needed to supply the high-voltage section. This function is normally accomplished by a high-voltage fast recovery diode (Figure 10.a). In the L6390 a patented integrated structure replaces the external diode. It is realized by a high-voltage DMOS, driven synchronously with the low-side driver (LVG), with diode in series, as shown in Figure 10.b. An internal charge pump (Figure 10.b) provides the DMOS driving voltage. 9.1 CBOOT selection and charging To choose the proper CBOOT value the external MOS can be seen as an equivalent capacitor. This capacitor CEXT is related to the MOS total gate charge: Equation 1 Q gate C EXT = --------------V gate The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss. It must be: Equation 2 CBOOT >>> CEXT E.g.: if Qgate is 30 nC and Vgate is 10 V, CEXT is 3 nF. With CBOOT = 100 nF the drop would be 300 mV. If HVG must be supplied for a long time, the CBOOT selection must also take the leakage and quiescent losses into account. E.g.: HVG steady-state consumption is lower than 150 μA, so if HVG TON is 5 ms, CBOOT must supply 0.75 μC to CEXT. This charge on a 1 μF capacitor means a voltage drop of 0.75 V. The internal bootstrap driver offers important advantages: the external fast recovery diode can be avoided (it usually has a high leakage current). This structure can work only if VOUT is close to GND (or lower) and, at the same time, the LVG is on. The charging time (Tcharge) of the CBOOT is the time in which both conditions are fulfilled and it must be long enough to charge the capacitor. The bootstrap driver introduces a voltage drop due to the DMOS RDSon (typical value: 120 Ω). This drop can be neglected at low switching frequency, but it should be taken into account when operating at high switching frequency. The following equation is useful to compute the drop on the bootstrap DMOS: Equation 3 Q gate V drop = I ch arg e R dson →V drop = --------------------- R dson T ch arg e 18/26 Doc ID 14493 Rev 7 L6390 Bootstrap driver where Qgate is the gate charge of the external Power MOSFET, Rdson is the on-resistance of the bootstrap DMOS and Tcharge is the charging time of the bootstrap capacitor. For example: using a Power MOSFET with a total gate charge of 30 nC, the drop on the bootstrap DMOS is about 1 V, if the Tcharge is 5 μs. In fact: Equation 4 30nC V drop = --------------- ⋅ 120Ω ∼0.7V 5μs Vdrop should be taken into account when the voltage drop on CBOOT is calculated: if this drop is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode can be used. Figure 10. Bootstrap driver DBOOT VCC BOOT BOOT VCC H.V. H.V. HVG HVG CBOOT OUT CBOOT OUT TO LOAD TO LOAD LVG LVG a b Doc ID 14493 Rev 7 D99IN1067 19/26 Package mechanical data 10 L6390 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Table 11. DIP-16 mechanical data mm Dim. Min. a1 0.51 B 0.77 Typ. 1.65 b 0.5 b1 0.25 D 20 E 8.5 e 2.54 e3 17.78 F 7.1 I 5.1 L 3.3 Z 20/26 Max. 1.27 Doc ID 14493 Rev 7 L6390 Package mechanical data Figure 11. DIP-16 package dimensions 0# Doc ID 14493 Rev 7 21/26 Package mechanical data Table 12. L6390 SO-16 narrow mechanical data mm Dim. Min. Typ. A 1.75 A1 0.10 0.25 A2 1.25 b 0.31 0.51 c 0.17 0.25 D 9.80 9.90 10.00 E 5.80 6.00 6.20 E1 3.80 3.90 4.00 e 1.27 h 0.25 0.50 L 0.40 1.27 k 0 8° ccc 22/26 Max. 0.10 Doc ID 14493 Rev 7 L6390 Package mechanical data Figure 12. SO-16 narrow package dimensions 0016020_F Doc ID 14493 Rev 7 23/26 Package mechanical data L6390 Figure 13. SO-16 narrow footprint 24/26 Doc ID 14493 Rev 7 L6390 11 Revision history Revision history Table 13. Document revision history Date Revision Changes 29-Feb-2008 1 First release 09-Jul-2008 2 Updated: Cover page, Table 2 on page 4, Table 3 on page 5, Section 4 on page 6, Section 5 on page 8, Section 9.1 on page 18 17-Sep-2008 3 Updated test condition values on Table 8 and Table 9 17-Feb-2009 4 Updated Table 7 on page 8, Table 8 on page 10, Table 9 on page 12 Added Table 4 on page 6 11-Aug-2010 5 Updated Table 1 on page 1, Table 7 on page 8, Table 9 on page 12, Table 10 on page 12 10-Jul-2012 6 Table 7 changed test conditions of DT and MDT values. Table 8 added minimum values to Iqccu-Iqcc-IQBOU- IQBO. Table 8 changed VBO_thON and VBO_thOFF minimum and maximum values. Table 9 and Table 10 added footnote to the title of the tables. Changed HVG values on page 17. Updated SO-16 narrow mechanical data. Changed Section 7 and added Figure 7 and Figure 8. 25-Jul-2012 7 Content reworked in Section 9: Bootstrap driver to improve readability, no technical changes. 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