AN4394 Application note Evaluation board for SPV1050 ULP harvester (boost architecture) Domenico Ragonese Introduction The STEVAL-ISV019V1 is an evaluation board based on the SPV1050 ultralow power energy harvester and battery charger. For any detail related to the SPV1050 features and performances please refer to the SPV1050 datasheet. The evaluation board implements the boost configuration of the DC-DC converter and has the purpose of enhancing the SPV1050 based applications development by testing the silicon performance thanks to many jumpers and test points, and by helping to find out the best system configuration to make the SPV1050 working at the most of efficiency. The STEVAL-ISV019V1 is configured to harvest energy from PV panels supplying 0.5 V ≤ VMP ≤ 2.5 V and 30 µA ≤ IMP ≤ 20 mA and charge a battery with the 3.7 V undervoltage protection threshold (VUVP) and 4.2 V end of charge voltage threshold (VEOC). Nevertheless, few easy changes on the application components (input and output resistor partitioning, CIN capacitor) allow to use a different PV panel and source (like TEG), and a battery, by setting the VMPP_SET, the VUVP and the VEOC thresholds according to the new requirements. More in detail, operating ranges can be extended as follows: VMP from 150 mV up to 5 V, IMP up to 100 mA, VUVP down to 2.2 V and VEOC up to 5.3 V. The STEVAL-ISV019V1 evaluation board is shown in Figure 1. Figure 1. STEVAL-ISV019V1 evaluation board May 2014 DocID025512 Rev 1 1/18 www.st.com Schematic and bill of material 1 AN4394 Schematic and bill of material The schematic, bill of material and gerber files can be downloaded from the Design resources tab of the STEVAL-ISV019V1 product folder on www.st.com. 2/18 DocID025512 Rev 1 - - DocID025512 Rev 1 /'2B(1 &1 73 73 73 73 & ) *1' 0336(7 033 39 & 6: 6: 5 5 5 39 - 73 & Q) 6725( 6725( *1' 033 8 /'2B(1 639 0336(7 0335() 6*1' /'2B(1 3*1' /B+9 ,1B+9 / ,1B/9 6725( 39,1 &1 73 ,1B/9 6725( 9%$77 &21) /'2 /'2 & 5 5 5 39 73 73 73 *1' (2& 893 6725( 73 & Q) & Q) %$77B2. %$77B&+* /'2 /'2 9%$77 (;7B683 &1 $09 2873876 &1 AN4394 Schematic and bill of material Figure 2. STEVAL-ISV019V1 schematic 893 (2& %$77B2. %$77B&+* 3/18 18 Schematic and bill of material AN4394 Figure 3. STEVAL-ISV019V1 application diagram %$77 %$77 73 6725( 73 / 6833/< 73 ,1B/9 &21752/ '5,9(56 ,1B+9 /B+9 5 &21752/ /2*,& 73 73 033 5 73 5 (2& 5 6725( 9 5 73 893 & /'2 & 6725( 033B6(7 0337 5 9 033B5() & /'2B(1 BBBBBBBBBB %$77B&21 BBBBBBBBBB %$77B&+* /'2B(1 &21) & & /'2 & 73 73 3*1' *1' 73 %$77 6833/< $0 4/18 DocID025512 Rev 1 Sect. Item QuanReference tity Part / value 1 1 U1 SPV1050 2 1 CN1 2-way screw connector 3 1 C1 4.7 µF Tolerance Voltage Technol. Watt info. % current 15% DC-DC input section DocID025512 Rev 1 15% 16 V Package Manufacturer Manufacturer code VFQFPN 3x3x1 20L (code A0BR) ST SPV1050 TE Connectivity 282834-2 0805 16 V 0805 Murata 4 0 C2 (DNM) 4.7 µF 5 3 J1, J2, J3 jumper 8 1 R1 0 1% 0805 VISHAY CRCW08052M7 0FKEA 9 1 R2 1.5 M 1% 0805 VISHAY CRCW08051M5 0FKEA 10 1 R3 8.2 M 1% 0805 YAGEO 232273468205 11 1 L1 22 µH 20% Coilcraft LPS4018223ML_ 12 1 C8 10 nF 15% Pitch 2.54 mm X7R Input capacitance GCM21BR71C4 75KA73L TH 0603 Input connector for PV panel or TEG Enable/disable MPPT Murata GRM188R71C1 03KA01D Resistor partitioning for MPP track/setting DC-DC inductor Voltage sampling time constant capacitance 5/18 Schematic and bill of material 16 V Murata GCM21BR71C4 75KA73L More information AN4394 Table 1. Bill of material Sect. Item QuanReference tity Part / value Tolerance Voltage Technol. Watt % current info. Battery section Manufacturer Manufacturer code More information TE Connectivity 282834-2 Connector for external supply of pin STORE 0805 TDK C2012X5R1A47 6M125AC Package DocID025512 Rev 1 13 1 CN4 2-way screw connector 14 1 C9 47 µF 20% 15 1 R4 6.2 M 5% 0805 RS RS-0805-6m25%-0.125W 16 1 R5 499 k 1% 0805 VISHAY CRCW0805499 KFKEA 17 1 R6 2.7 M 1% 0805 VISHAY CRCW08052M7 0FKEA 18 1 CN2 8-way screw connector TE Connectivity 282836-8 Connector for battery and battery status signals 19 2 C6, C7 100 nF KEMET C0603C104K4R AC Tank capacitor for LDOs LDOs section 21 2 SW1, SW2 5-pin male Stripline 23 1 CN3 4-way screw connector 10% 10 V X7R Pitch 2.54 mm 0603 Resistor partitioning for UVP, EOC, protection setting Schematic and bill of material 6/18 Table 1. Bill of material (continued) Close 2 - 3: LDO disabled Close 1 - 2: LDO enabled Floating: external control through CN3 TH TE Connectivity 282836-4 Connector for LDOs enable connection AN4394 Sect. Item QuanReference tity Part / value Tolerance Voltage Technol. Watt % current info. Package Manufacturer Manufacturer code More information List of test points DocID025512 Rev 1 25 1 TP1 True hole PV+ pin sensing and soldering 26 1 TP2 True hole MPP pin sensing and soldering 27 1 TP3 True hole MPP-SET pin sensing and soldering 28 1 TP4 True hole STORE pin sensing and soldering 29 1 TP5 True hole ULP pin sensing and soldering 30 1 TP6 True hole EOC pin sensing and soldering 31 1 TP7 True hole GND pin sensing and soldering 32 1 TP8 True hole GND pin sensing and soldering 33 1 TP9 True hole IN_LV pin sense (for probe scope) 34 1 TP10 True hole GND pin sensing (for probe scope) AN4394 Table 1. Bill of material (continued) Schematic and bill of material 7/18 System setup 2 AN4394 System setup The system setup that can be used for the evaluation of the SPV1050 device is shown in Figure 4: Figure 4. Measurement system setup The supply system emulates the I-V characteristic of a PV panel and it is composed by a power supply VGEN, to determine VOC, and a resistor RIN, to determine IMP and VMP. Considering the typical electrical parameters of a PV panel (VOC, VMP, IMP, ISC), the supply system has to be set as following: VGEN = VOC RIN = (VOC - VMP)/IMP At the output stage a real battery can be connected to the BATT pin. The battery can be emulated by a power supply with a resistor (RBATT) in series. 8/18 DocID025512 Rev 1 AN4394 3 Layout Layout From Figure 5 to Figure 7 show the component placement and the layout (top and bottom views) of the STEVAL-ISV019V1. Figure 5. Layout - silkscreen view Figure 6. Layout - top view Figure 7. Layout - bottom view DocID025512 Rev 1 9/18 18 Layout AN4394 The following indications must be followed in the PCB routing: The same ground plane has to connect the exposed pad and the pins PGND and GND. The capacitor on the STORE pin must be placed as close as possible to the pin. The capacitors on the LDO1 and LDO2 pins must be placed as close as possible to the respective pins. Details on the recommended layout solution are shown in Figure 8 and Figure 9. Figure 8. Ground plane detail 10/18 Figure 9. Component placement detail DocID025512 Rev 1 AN4394 4 Component selection Component selection This section describes the application rules to be followed for properly selecting the components around the SPV1050 device. 4.1 MPPT setting The “Maximum Power Point” (MPP) is set through the input resistor partitioning R1, R2 and R3. As a preliminary rule, the voltage on the MPP pin (VMPP), which depends on the voltage supplied by the selected source (VIN), must be ≤ VUVP (which is set by the output resistor partitioning R3, R4, R5). So, the following equation: Equation 1 R2 + R3 V MPP = V IN ------------------------------------ V UVP R1 + R2 + R3 can be rewritten as follows: Equation 2 R2 + R3 V UVP V OC MAX -----------------------------------R1 + R2 + R3 VOC(MAX) stands for the maximum voltage that the source can supply (open circuit voltage). Further, the MPPRATIO = VMPP_SET/VOC is set by the following equation: Equation 3 V MPP SET R3 = V IN -----------------------------------R1 + R2 + R3 R3 MPP RATIO V OC = -----------------------------------R1 + R2 + R3 Finally, the leakage on the input resistor partitioning must be negligible, hence typically it must be: Equation 4 10 M ≤ R1 + R2 + R3 ≤ 20 M If the electrical characteristics of the selected source and battery are such that VOC(MAX) ≤ VUVP, the resistor R1 can be simply replaced by a short-circuit. Consequently, only R2 and R3 have to be selected for a proper setting of MPPRATIO. For the PV panels the VMP is typically in the range between 70% and 80% of VOC. For the TEG the VMPP_SET is equals to 50% of VOC, so the selection is R1 = 0 and R2 = R3. DocID025512 Rev 1 11/18 18 Component selection 4.2 AN4394 Input capacitance Every 16 seconds (typical) the SPV1050 device stops switching for 400 ms. During this time frame the input capacitor C1 is charged up to VOC by the source: the voltage will rise according to the time constant (T1), which depends both on its capacitance and on the equivalent resistance REQ of the source. In case of the PV panel source, assuming IMP(min) as the minimum current at which the MPP must be guaranteed, the REQ can be calculated as follows: Equation 5 V OC – V MPP V OC 1 – MPP RATIO R EQ = -------------------------------- = ------------------------------------------------------------I MP min I MP min Consequently Equation 6 T1 C1 ----------R EQ Figure 10 and Figure 11 show the effect of different value of the C1 on the time constant: too high capacitance might be not charged within the 400 ms time window affecting the MPPT precision. Figure 10. Input stage equivalent circuit Figure 11. Effect of C1 on sampled voltage 9& 92& 5(4 9(4 (55 ,03 & P) & & P) & P) 9& $0 7LPHPV $0 The default C1 = 4.7 F capacitance covers the most typical application cases. The energy extracted from the harvested source, and stored in the input capacitance, is transferred to the load by the DC-DC converter though the inductor. The energy extracted by the inductor depends by the sink current: the higher input currents cause higher voltage drop on the input capacitance and this may result a problem for low voltage (< 1 V) and high energy (> 20 mA) sources. In such application cases the input capacitance has to be increased or, alternatively the L1 inductance has to be reduced. The SPV1050 performances might be further improved by reducing the time constant (e.g. reducing input capacitance) at very low input power. 12/18 DocID025512 Rev 1 AN4394 4.3 Component selection Capacitance on MPP-REF pin It's recommended to use C8 = 10 nF in most of the application cases. 4.3.1 Inductor selection The SPV1050 device controls the switching of the integrated DC-DC by limiting the peak current flowing through the inductor L1. L1 = 22 µH covers the most typical application range: the lower is the series resistance of the selected inductor, the lower is its DC loss. The current capability of the selected inductor must be ≥ 200 mA. 4.3.2 Output voltage ripple In case of battery with high series resistance and a fast load transient, the capacitor on the STORE pin may momentarily discharge and cause the undesired triggering of the VUVP threshold, implying the battery disconnection. Although the fast transient might be masked by a proper capacitance between the UVP and GND pins, if the battery has a low peak current capability, the voltage on the STORE pin may further drop down lower than VUVP. Increasing the capacitance on the STORE pin has the drawback of affecting the output time constant and consequently delays the startup time. The same capacitor might be placed in parallel to the battery, on the BATT pin. The selection of the battery and of the output capacitance on the STORE pin (C9) is strictly related to the following application parameters: The series resistance of the battery (RBATT) The EOC threshold (VEOC) and the UVP threshold (VUVP) The maximum load current (ILOAD(MAX)) The TLOAD(ON), how long the load sink ILOAD(MAX) The maximum allowed voltage drop on LDOs outputs (VDROP(MAX)) The maximum current that can be supplied to the load is the sum of the currents that can be supplied by the battery (IBATT(MAX)) and by the C9 (ISTORE): Equation 7 ILOAD(MAX) = IBATT(MAX) + ISTORE The maximum current that the battery can supply without triggering the UVP threshold is: Equation 8 V BATT – V UVP I BATT MAX = ------------------------------------R BATT The amount of charge that the C9 can supply is: Equation 9 Q9 = C9 • VDROP(MAX) DocID025512 Rev 1 13/18 18 Component selection AN4394 Considering that I = C • dV/dt, it follows: Equation 10 C STORE V DROP MAX I BATT MAX = I LOAD MAX – ------------------------------------------------------------T LOAD ON Thus: Equation 11 I LOAD MAX – I BATT MAX C STORE T LOAD ON -----------------------------------------------------------------V DROP MAX 4.3.3 UVP and EOC setting The pins UVP and EOC have to be connected to the STORE pin by the resistor partitioning R4, R5 and R6 to setup the related thresholds by scaling down those voltage values and by comparing them with the internal voltage reference set at 1.23 V. The design rules to setup the R4, R5 and R6 are the following: Equation 12 R5 + R6 V BG = V UVP -----------------------------------R4 + R5 + R6 Equation 13 R6 V BG = V EOC -----------------------------------R4 + R5 + R6 Further, in order to minimize the leakage due to the output resistor partitioning it has to be typically: Equation 14 10 M ≤ R4 + R5 + R6 ≤ 20 M 14/18 DocID025512 Rev 1 AN4394 5 Board description Board description The STEVAL-ISV019V1 has a full set of connectors, jumpers and switches as described below: Table 2. CN1 connector CN1 pin number Signal 1 2 INPUT+ INPUT- Table 3. CN2 connector CN2 pin number SPV1050 pin signal 1 2 3 4 5 6 VBATT GND LDO2 GND LDO1 GND 7 8 BATT-CON BATT-CHG VBATT: connect this pin to the positive of the battery. LDO2: connect this pin to the load to be supplied at 3.3 V. LDO1: connect this pin to the load to be supplied at 1.8 V. BATT-CON: output logic pin for battery connection monitoring. Please notice that this is an open drain pin, which has to be pulled up by a resistor (typically 10 M) to a voltage rail lower than VSTORE. BATT-CHG: output logic pin for battery charging status monitoring. Please notice that this is an open drain pin, which has to be pulled up by a resistor (typically 10 M) to a voltage rail lower than VSTORE. Table 4. CN3 connector CN3 pin number SPV1050 pin signal 1 2 3 4 LDO1_EN GND GND LDO2_EN LDO1_EN: input logic pin to enable/disable the LDO1. Connect this pin to the control signal from the microcontroller. LDO2_EN: input logic pin to enable/disable the LDO2. Connect this pin to the control signal from the microcontroller. DocID025512 Rev 1 15/18 18 Board description AN4394 Table 5. CN4 connector CN4 pin number SPV1050 pin signal 1 2 STORE GND STORE: connect this pin to the tank capacitor CSTORE. GND: system ground. The MPPT function can be disabled by pulling up the pin MPP-SET and unsoldering the resistor R2. In this case the duty cycle of the switching converter will be regulated according to the fixed end of charge voltage connected to the J3. Table 6. J1, J2, J3: enable/disable MPPT J1 LEAVE IT OPEN Function (signal monitoring) J2 J3 OPEN: MPPT ENABLED CLOSE: MPPT DISABLED(1) LEAVE OPEN IF J2 IS OPEN. CONNECT TO EXTERNAL REFERENCE VOLTAGE IF J2 IS CLOSED 1. The R2 must be unsoldered. Table 7. SW1, SW2: enable/disable LDOs Function 16/18 SW1 SW2 CLOSE 3 - 4: LDO1 DISABLED CLOSE 2 - 3: LDO1 ENABLED FLOATING: EXTERNAL CONTROL BY CN3 CLOSE 3 - 4: LDO2 DISABLED CLOSE 2 - 3: LDO2 ENABLED FLOATING: EXTERNAL CONTROL BY CN3 DocID025512 Rev 1 AN4394 6 Revision history Revision history Table 8. Document revision history Date Revision 15-May-2014 1 Changes Initial release. DocID025512 Rev 1 17/18 18 AN4394 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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